CN106298708B - 封装结构及三维封装结构 - Google Patents
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Abstract
本发明公开了一种封装结构,包含有至少一接脚,用来传递至少一讯号;至少一走线层,连接于该至少一接脚,该至少一走线层中形成有至少一第一通孔或为可电性导通该封装结构的一导电支架的介质;一芯片,设置于该至少一走线层之上,该芯片形成有至少一第二通孔,该芯片产生或接收该至少一讯号,该至少一讯号通过该至少一第二通孔传递于该芯片的一第一面与该芯片的一第二面之间;以及一模封盖,用来包覆该至少一走线层及该芯片;其中,该至少一讯号通过该至少一第一通孔及该至少一第二通孔或该至少一讯号通过该导电支架传递于该芯片与该至少一接脚之间。
Description
【技术领域】
本发明涉及一种封装结构及三维封装结构,尤指一种可降低高频损耗的封装结构及三维封装结构。
【背景技术】
一般而言,高频或超高频行动通讯是指操作于数十GHz的无线通信系统,而目前常见的封装技术在数十GHz的频带下具有显著的损耗。举例来说,目前常见的封装技术为表面贴装技术(Surface Mount Technology,SMT),采用SMT封装技术的组件可大量的组装制造成各类行动装置。然而,已知以SMT封装技术的组件的高频特性不佳,当操作频率高于6GHz时,组件内的损耗随着操作频率高而逐渐显著,进而影响整体效能。
详细来说,请参考图1,图1为已知一封装结构10的剖面示意图。封装结构10包含一芯片100及接脚102,通过一打线接合(Wire Bonding)制程方式,将芯片100与接脚102之间通过金属线104相互接合,最后,通过一模封制程方式,形成一模封盖106以包覆芯片100及金属线104。需注意的是,金属线104包覆于模封盖106中,当操作频率高于6GHz时,因金属线104与模封盖106相互接触而产生寄生电感效应,且当操作频率越高,寄生电感的电感值越大,造成高频损耗增加,进而影响封装结构10的效能。
因此,如何降低高频时所产生的损耗,就成了业界所努力的目标之一。
【发明内容】
因此,本发明的主要目的之一在于提供一种封装结构及三维封装结构,其可降低高频时所产生的损耗。
本发明揭露一种封装结构,包含有至少一接脚,用来传递至少一讯号;至少一走线层,连接于该至少一接脚,该至少一走线层中形成有至少一第一通孔或为可电性导通该封装结构的一导电支架的介质;一芯片,设置于该至少一走线层之上,该芯片形成有至少一第二通孔,该芯片产生或接收该至少一讯号,该至少一讯号通过该至少一第二通孔传递于该芯片的一第一面与该芯片的一第二面之间;以及一模封盖,用来包覆该至少一走线层及该芯片;其中,该至少一讯号通过该至少一第一通孔及该至少一第二通孔或该至少一讯号通过该导电支架传递于该芯片与该至少一接脚之间。
本发明另揭露一种三维封装结构,包含有至少一接脚,用来传递至少一讯号;至少一走线层,连接于该至少一接脚,该至少一走线层中形成有至少一第一通孔或为可电性导通该封装结构的一导电支架的介质;复数个芯片,相互堆栈而设置于该至少一走线层之上,该复数个芯片中至少一芯片中各自形成有至少一第二通孔,该至少一第一芯片产生或接收该至少一讯号;以及一模封盖,用来包覆该至少一走线层及该复数个芯片;其中,该至少一讯号通过该至少一第一通孔及该至少一第二通孔或该至少一讯号通过该导电支架传递于该至少一第一芯片与该至少一接脚之间。
【附图说明】
图1为已知一封装结构的剖面示意图。
图2为本发明实施例的一封装结构的剖面示意图。
图3为图1的封装结构与图2的封装结构的穿透系数-频率响应的示意图。
图4为本发明实施例的一三维封装结构的示意图。
图5为本发明实施例的一封装结构的剖面示意图。
其中的附图标记说明如下:
10、20、40、50 封装结构
100、200、400_1、400_2、400_3、500 芯片
200_gnd 芯片接地部
104 金属线
202_a、202_b、402_a、402_b、502_a、502_b 接脚
202_gnd 接地接脚
106、206、406、506 模封盖
200_via、208_via、400_via、408_via、500_via、508_via 通孔
208_1、208_2、408_1、408_2、508 走线层
【具体实施方式】
请参考图2,图2为本发明实施例的一封装结构20的剖面示意图。在此例中,封装结构20为包含接脚202_1~202_N的一四方扁平无引脚封装(Quad Flat No-lead Package,QFN),接脚202_1~202_N设置在封装结构20的下方,为求简洁,图2仅绘示接脚202_1~202_N中的两个接脚202_a、202_b。如图2所示,封装结构20包含有一芯片200、走线层208_1、208_2、接脚202_1~202_N及一模封盖206,芯片200设置于走线层208_1、208_2之上,其可为未经封装的一晶粒(Die,或称裸晶),其用来实现一单晶微波集成电路(Monolithic MicrowaveIntegrated Circuit,MMIC)的功能,换句话说,芯片200产生或接收复数个讯号。封装结构20可通过接脚202_1~202_N以焊接的方式耦接于一外部电路板(未绘示于第2图),接脚202_1~202_N分别用来传递复数个讯号至外部电路板。其中,讯号RF_a、RF_b为复数个讯号中具有高频特性的讯号,在一实施例中,接脚202_a、202_b分别用来传递高频讯号RF_a、RF_b至外部电路板。走线层208_1可视为上层走线层,走线层208_2可视为下层走线层,走线层208_1、208_2电性连接于接脚202_1~202_N并设置于芯片200与接脚202_1~202_N之间,用来提供芯片200与接脚202_1~202_N之间之走线。模封盖206可为环氧树脂(MoldingCompound)或气腔(Air-Cavity)封装等模封材料所制成,但不在此限。模封盖206用来包覆走线层208_1、208_2及芯片200,使得封装结构20的外观为四方扁平无引脚封装。
详细来说,芯片200可通过一热导孔(Hot Via)制程方式形成有复数个通孔200_via,而走线层208_1、208_2亦可通过钻孔的方式形成有复数个通孔208_via,芯片200的讯号,由芯片200的一正面(芯片200的正面与模封盖206接触),通过通孔200_via连接到芯片200的一背面(芯片200的背面与走线层208_1接触),且电性连接于位于走线层的通孔208_via。换句话说,走线层208_1、208_2通过通孔208_via,利用如微带线(Microstrip Line)等导电材质,以提供芯片200与接脚202_a、202_b之间的走线,如此一来,按上述实施例,讯号RF_a、RF_b即可通过通孔200_via及通孔208_via直接由接脚202_a、202_b传递至芯片200(或由芯片200传递至接脚202_a、202_b)。另外,走线层208_1、208_2可以一薄型印刷电路板(Laminate PCB)或一陶瓷材质所制成,或是可电性导通封装结构20的一导电支架(LeadFrame,未绘示于第2图)的介质,但不在此限。除此之外,藉由热导孔制程方式,芯片200的一芯片接地部200_gnd可通过通孔电性连接于封装结构20的一接地接脚202_gnd,使得封装结构20及芯片200具有较佳的散热特性。另外,形成于上层走线层208_1的通孔208_via可视为内通孔,形成于下层走线层208_2的通孔208_via可视为外通孔,内通孔208_via位于接地接脚202_gnd上方。
需注意的是,高频讯号RF_a、RF_b可透过通孔200_via、208_via或导电支架而电性连接于接脚202_a、202_b,藉此,本发明的通孔200_via、208_via可取代传统利用打线接合(Wire Bonding)的方式使芯片的讯号传递至封装结构的接脚,以避免不必要的电感效应。因此,封装结构20于高频(操作频率高于6GHz)时,封装结构20不会产生(或仅产生轻微的)寄生电感效应,因此可降低封装结构20于高频时所产生的损耗。请参考图3,图3为图1的封装结构10与图2的封装结构20的穿透系数-频率响应的示意图,其中,虚线为封装结构10的穿透系数-频率响应,实线为封装结构20的穿透系数-频率响应。由图3可知,因已知封装结构10的金属线104与模封盖106接触而于高频产生寄生电感效应,使得封装结构10的穿透系数︱S21︱于操作频率高于20GHz时急遽地衰减,以及封装结构10的损耗于操作频率高于20GHz时急遽地恶化。相较之下,本发明即使在操作频率高于20GHz的情况下,封装结构20的损耗极小,衰减幅度仅小于1dB。
因此,本发明的封装结构可大幅降低于高频时所产生的损耗,除此之外,本发明的封装结构可适用于表面贴装技术(Surface Mount Technology,SMT)的封装,可经大量的组装制造成各类行动装置。另外,本发明使用热导孔制程方式于芯片200中形成有通孔200_via,因此,相较于现行倒晶封装技术(Flip Chip),芯片200的电路布局不须配合倒晶封装的接线而另外重新设计,而且本发明使用热导孔制程方式,芯片200具有较佳的散热特性。
前述实施例是用以说明本发明的概念,本领域具通常知识者当可据以做不同的修饰,而不限于此。举例来说,于封装结构20中,因芯片200的面积通常小于封装结构20的面积,而在薄型印刷电路板上进行垂直钻孔已为一成熟技术,故可利用经垂直钻孔的两个走线层208_1、208_2与经适当布线的走线层208_2,将讯号RF_a、RF_b由接脚202_a、202_b传递至芯片200(或由芯片200传递至接脚202_a、202_b),然而,本发明的封装结构不限于两个走线层,亦可仅包含单一走线层。举例来说,请参考图5,图5为本发明实施例的一封装结构50的剖面示意图。封装结构50与封装结构20类似,与封装结构20不同的是,封装结构50仅包含一走线层508,且因封装结构50所包含的一芯片500具有较芯片200宽大的面积,使得芯片500的一垂直投影结果与接脚502_a、502_b重迭,如此一来,走线层508可利用垂直钻孔的方式形成通孔508_via,以建立芯片500与接脚502_a、502_b之间的走线。需注意的是,走线层中通孔的形式可视实际需求而变化,其可透过斜角钻孔或曲线钻孔的方式而形成,并不限于利用垂直钻孔的方式形成通孔,换句话说,只要走线层形成有通孔以建立芯片与接脚之间的走线,即满足本发明需求且属于本发明的范畴。
另一方面,于前述实施例中,封装结构20将高频讯号RF_a、RF_b利用通孔传递于芯片200与接脚202_a、202_b之间,而不限于此。在此情形下,芯片所产生或接收的讯号皆可利用形成于芯片与走线层中的通孔而传递于芯片与接脚之间;或者,若芯片所产生或接收的讯号包含低频或直流讯号及高频讯号,则高频讯号可利用通孔传递于芯片与接脚之间,而其余的低频或直流讯号仍可利用打线接合(Wire Bonding)的方式传递于芯片与接脚之间。换句话说,封装结构中只要有讯号通过走线层的至少一第一通孔与芯片的至少一第二通孔传递于芯片与接脚之间,即满足本发明需求且属于本发明的范畴。
另外,封装结构20可为QFN封装所衍生的变形,如高功率QFN封装(Power QFN,PQFN)、薄型QFN封装(Thin QFN,TQFN)、超薄型QFN封装(Ultra Thin QFN,UTQFN)、极薄型QFN封装(Extreme Thin QFN,XQFN),皆属于本发明的范畴。除此之外,封装结构20亦可为双侧扁平无引脚封装(Dual Flat No-lead Package,DFN)及其衍生的变形,如高功率DFN封装(Power DFN,PDFN)、薄型DFN封装(Thin DFN,TDFN)、超薄型DFN封装(Ultra Thin DFN,UTDFN)、极薄型DFN封装(Extreme Thin DFN,XDFN),皆属于本发明的范畴。
封装结构20是说明封装单一芯片的实施例,其系用以降低封装结构于高频时所产生的损耗。除此之外,本发明亦可应用于多芯片的封装,例如,若将多个芯片于垂直方向上适当地堆栈,则可进一步形成一三维封装结构。举例来说,请继续参考图4,图4为本发明实施例的一三维封装结构40的示意图。封装结构40为包含接脚402_1~402_N的QFN封装,接脚402_1~402_N设置于封装结构40的下方,如图4所示,三维封装结构40包含有芯片400_1~400_3、走线层408_1、408_2、及一模封盖406,为求简洁,第4图仅绘示接脚402_1~402_N中的两个接脚402_a、402_b,而接脚402_a、402_b分别用来传递高频讯号RF_a、RF_b至外部电路板。走线层408_1、408_2电性连接于接脚402_a、402_b并设置于芯片400_3与接脚402_a、402_b之间,走线层408_1、408_2中形成有通孔408_via,走线层408_1、408_2亦可为可电性导通封装结构40的一导电支架(未绘示于第4图)的介质。芯片400_1~400_3皆可为未经封装的晶粒,其相互堆栈(即芯片400_1设置于芯片400_2之上且芯片400_2设置于芯片400_3之上)而设置于走线层408_1之上,芯片400_1~400_3中可透过热导孔制程方式而各自形成有通孔400_via,芯片400_1~400_3用来产生或接收高频讯号RF_a、RF_b。模封盖406可为环氧树脂或气腔封装等模封材料所制成,而不在此限。模封盖406用来包覆走线层408_1、408_2及芯片400_1~400_3,使得封装结构20的外观与一般四方扁平无引脚封装相同。如此一来,讯号RF_a、RF_b即可通过通孔400_via及通孔408_via或导电支架直接由接脚402_a、402_b传递至芯片400_1~400_3(或由芯片400_1~400_3传递至接脚402_a、402_b),即通孔400_via及通孔408_via用来提供芯片400_1~400_3与走线层408_1、408_2之间的走线。需注意的是,三维封装结构40系用以说明本发明的概念,本领域具通常知识者当可据以做不同的修饰,而不限于此。举例来说,三维封装结构所包含的芯片个数并未有所限,可包含复数个芯片,该复数个芯片只要有一芯片利用热导孔制程方式以形成通孔400_via,即满足本发明需求且属于本发明的范畴。另外,三维封装结构的走线层的层数不限于两层,亦可仅包含一层走线层,而走线层中的通孔亦可利用垂直钻孔、斜角钻孔或曲线钻孔的方式来形成,而不在此限。其余变化方式可参考前述相关段落,于此不赘述。
由上述可知,本发明的封装结构利用形成于芯片与走线层的通孔来传递高频讯号,避免高频讯号的传递路径与模封盖接触,于高频时不会产生寄生电感。相较于已知技术,本发明的封装结构于高频时的损耗较小,且适用于表面贴装技术的封装,可经大量的组装制造成各类行动装置。
以上所述仅为本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (10)
1.一种封装结构,包含有:
至少一接脚,用来传递至少一讯号;
多个走线层,连接于该至少一接脚,该多个走线层中形成有多个第一通孔或为可电性导通该封装结构的一导电支架的介质,该多个第一通孔包含多个第一内通孔及多个第一外通孔,该多个第一内通孔形成于该多个走线层中一上层走线层,该多个第一外通孔形成于该多个走线层中一下层走线层;
一芯片,设置于该多个走线层之上,该芯片形成有至少一第二通孔,该芯片产生或接收该至少一讯号,该至少一讯号通过该至少一第二通孔传递于该芯片的一第一面与该芯片的一第二面之间;
一接地接脚,设置于该芯片正下方,其中该多个走线层中另形成有多个接地通孔,该多个接地通孔连接该芯片与该接地接脚;以及
一模封盖,用来包覆该多个走线层及该芯片;
其中,该至少一讯号通过该至少一第一通孔及该至少一第二通孔或该至少一讯号通过该导电支架传递于该芯片与该至少一接脚之间;
其中,该多个第一内通孔位于该接地接脚上方。
2.如权利要求1所述的封装结构,其中该封装结构为一四方扁平无引脚封装或一双侧扁平无引脚封装。
3.如权利要求1所述的封装结构,其中该走线层是以一薄型印刷电路板或一陶瓷材质所制成。
4.如权利要求1所述的封装结构,其中该至少一第二通孔是以一热导孔所制成。
5.如权利要求1所述的封装结构,其中该模封盖为环氧树脂或气腔封装的模封材料所制成。
6.一种三维封装结构,包含有:
至少一接脚,用来传递至少一讯号;
多个走线层,连接于该至少一接脚,该多个走线层中形成有多个第一通孔或为可电性导通该封装结构的一导电支架的介质,该多个第一通孔包含多个第一内通孔及多个第一外通孔,该多个第一内通孔形成于该多个走线层中一上层走线层,该多个第一外通孔形成于该多个走线层中一下层走线层;
复数个芯片,相互堆栈而设置于该多个走线层之上,该复数个芯片中至少一第一芯片形成有至少一第二通孔,该至少一第一芯片产生或接收该至少一讯号;
一接地接脚,设置于该复数个芯片中一芯片正下方,其中该多个走线层中另形成有多个接地通孔,该多个接地通孔连接该芯片与该接地接脚;以及
一模封盖,用来包覆该多个走线层及该复数个芯片;
其中,该至少一讯号通过该至少一第一通孔及该至少一第二通孔或该至少一讯号通过该导电支架传递于该至少一第一芯片与该至少一接脚之间;
其中,该多个第一内通孔位于该接地接脚上方。
7.如权利要求6所述的三维封装结构,其中该封装结构为一四方扁平无引脚封装或一双侧扁平无引脚封装。
8.如权利要求6所述的三维封装结构,其中该走线层是以一薄型印刷电路板或一陶瓷材质所制成。
9.如权利要求6所述的三维封装结构,其中该至少一第二通孔是以一热导孔所制成。
10.如权利要求6所述的三维封装结构,其中该模封盖为环氧树脂或气腔封装的模封材料所制成。
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US11894322B2 (en) | 2018-05-29 | 2024-02-06 | Analog Devices, Inc. | Launch structures for radio frequency integrated device packages |
US11424196B2 (en) | 2018-06-01 | 2022-08-23 | Analog Devices, Inc. | Matching circuit for integrated circuit die |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101471317A (zh) * | 2007-12-26 | 2009-07-01 | 联发科技股份有限公司 | 引线框架封装及引线框架 |
CN102420180A (zh) * | 2010-09-24 | 2012-04-18 | 新科金朋有限公司 | 半导体器件及其制造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63306650A (ja) * | 1987-06-09 | 1988-12-14 | Fujitsu Ltd | マルチチップパッケ−ジ構造 |
JPH05198697A (ja) * | 1992-01-20 | 1993-08-06 | Fujitsu Ltd | シリコン基板金属ビア形成方法およびマルチチップモジュール製造方法 |
JP2721093B2 (ja) * | 1992-07-21 | 1998-03-04 | 三菱電機株式会社 | 半導体装置 |
KR100209760B1 (ko) * | 1996-12-19 | 1999-07-15 | 구본준 | 반도체 패키지 및 이의 제조방법 |
US6661832B1 (en) | 1999-05-11 | 2003-12-09 | Qualcomm Incorporated | System and method for providing an accurate estimation of received signal interference for use in wireless communications systems |
US6577013B1 (en) * | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
JP2006501677A (ja) * | 2002-09-30 | 2006-01-12 | アドバンスド インターコネクト テクノロジーズ リミテッド | ブロック成形集成体用の耐熱強化パッケージ |
TWI442520B (zh) * | 2005-03-31 | 2014-06-21 | Stats Chippac Ltd | 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件 |
KR100782483B1 (ko) * | 2006-01-19 | 2007-12-05 | 삼성전자주식회사 | 내부단자 배선을 갖는 패키지 보드 및 이를 채택하는반도체 패키지 |
US20080217708A1 (en) * | 2007-03-09 | 2008-09-11 | Skyworks Solutions, Inc. | Integrated passive cap in a system-in-package |
US8198716B2 (en) * | 2007-03-26 | 2012-06-12 | Intel Corporation | Die backside wire bond technology for single or stacked die package |
KR100895813B1 (ko) * | 2007-06-20 | 2009-05-06 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
US8629061B2 (en) * | 2012-02-08 | 2014-01-14 | Gtat Corporation | Method for three-dimensional packaging of electronic devices |
US8941244B1 (en) * | 2013-07-03 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
-
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101471317A (zh) * | 2007-12-26 | 2009-07-01 | 联发科技股份有限公司 | 引线框架封装及引线框架 |
CN102420180A (zh) * | 2010-09-24 | 2012-04-18 | 新科金朋有限公司 | 半导体器件及其制造方法 |
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