CN101207117B - 系统级封装体及其制造方法 - Google Patents

系统级封装体及其制造方法 Download PDF

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CN101207117B
CN101207117B CN2007103001010A CN200710300101A CN101207117B CN 101207117 B CN101207117 B CN 101207117B CN 2007103001010 A CN2007103001010 A CN 2007103001010A CN 200710300101 A CN200710300101 A CN 200710300101A CN 101207117 B CN101207117 B CN 101207117B
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leadframe
chip
encapsulation body
semiconductor chip
pair
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CN101207117A (zh
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陈南璋
林泓均
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种具有引脚框置于散热器上类型的系统级封装体及其制造方法。系统级封装体(SiP)包括具有多个延伸的引脚的引脚框，其配置有多个分开的散热器，散热器是作为电源及接地网络。一对半导体芯片，以粘附材料贴附在引脚框的中央区域。芯片踏板，设置于该对半导体芯片之间，用以支撑该对半导体芯片，并且芯片踏板位于散热器之上；多条接合线，将该对半导体芯片分别电性连接至引脚框与散热器。封装材料，封闭引脚框，然而露出延伸的引脚和散热器。上述系统级封装体及其制造方法，提高了系统级封装体的散热效能与电性效能。

Description

系统级封装体及其制造方法
技术领域
本发明是有关于一种半导体封装，特别有关于一种置于散热器上的引脚框类型的半导体封装体及其制造方法。
背景技术
应目前对具有更高频宽容量的电子组件的消费需求，需要更快的信号传输速度。面对这项趋势，半导体封装体产品主要面临两大挑战，其一是由于更高功率消费需求所导致的散热问题，另一是更高信号频宽所导致的电性问题。为能有效解决信号与电力完整性(signal and power integrity)的(即F3dB＝0.35/tr)问题以及散热(即P＝CL×f×VDD 2)的问题，业界需要一种应用于高速整合电路的半导体封装体，其兼具低寄生效应(parasitic effect)与低制造成本的优点。
现有技术的半导体芯片的四侧引脚扁平封装体(Quad Flat Package，简称QFP)主要用于低成本产品。上述低成本产品分别利用插入式散热器(Drop-in HeatSink，以下简称为DHS))、芯片垫散热器(Die Pad Heat Sink，以下简称为DPH)、裸露插入式散热器(Exposed Drop-in Heat Sink，以下简称为EDHS)及裸露芯片垫薄型四侧引脚扁平封装体(Exposed PAD Low profile in QFP，以下简称为E-PADLQFP)等类型，以改善其散热效率。然而，以散热器作为接地面或浮置接地面(floating ground plane)，未能有效地改善其电性效能。
图1A-1D为现有技术的QFP的剖面示意图，其分别具有不同类型的散热器(heat sink)，以改善其热效能。请参阅图1A，DHS-QFP 100a包括半导体芯片110，贴附在芯片垫(die pad)125上。半导体芯片110与芯片垫125之间附着有粘附材料(adhesion)120。芯片垫125置于散热器130上。半导体芯片110通过接合线(bonding wire)140电性连接多个引脚(lead)150。封装材料(encapsulation)160封闭(enclose)半导体芯片110、芯片垫125、散热器130以及半导体芯片110与引脚150之间的接合线140。
或者，如图1B所示的DPH-QFP 100b，半导体芯片110可直接由粘附材料120安置于散热器130上。散热器130也可作为芯片垫。散热器130的两端均透过聚酰亚胺胶带(polyimide tape)135连接至引脚150。然而，此类型的封装体的设计的问题在于，由散热器作为浮置接地面(floating plane)，无法有效地改善其电性效能。
请参阅图1C，散热器130的底部表面132可裸露于外界环境中，而形成EDHS-QFP 100c。再者，散热器130可与引脚框(leadframe)整合为一体以满足薄型化(low profile)的需求，如图1D所示的E-PAD LQFP 100d。E-PAD LQFP 100d为广泛用于各种装置的理想封装体，上述装置包括微处理器、控制器、数字信号处理器、高速逻辑装置、现场可编程门阵列(Field Programmable Gate Array，以下简称为FPGA)装置、可编程逻辑器件(Programmable Logic Device，以下简称为PLD)与专用集成电路(Application Specific Intefrated Circuit，ASIC)，其应用领域包括笔记本计算机、通讯装置、高端(high end)视/听装置及中央处理单元(CPU)/图形使用者界面(GUI)板。因此，通过散热器的底部表面作为接地面，能有效地降低接地电感(Ground Inductance)。
相关技术揭露具有多个散热器的模压塑料封装体(molded plastic package)，其电性效能得到改善。图2A为现有技术的EDHS-QFP封装体200的剖面示意图。请参阅图2A，半导体芯片211通过导热环氧树脂膜(film of thermallyconductive epoxy)210粘附于厚的铜散热器201上。环型陶瓷圈(annular ceramicring)206以介电粘附剂213将环型陶瓷圈206的一面粘于散热器201上，且另一面粘于引脚框205上。封装体200形成引脚框205内的各导线的传输线，同时散热器201作为接地面。此外，引脚框205包括插入环208(图2B)，其环绕位于环型陶瓷圈206的窗口212(图2B)内的半导体芯片211。插入环208可分成四个插入环部分208a-208d(图2B)，使其能分别连接至电源端及接地端。
图2B为移开塑料模铸物204的封装体200的立体示意图，其清楚显示引脚框205和插入环208。插入环208的插入环部分208a-208d通过介电粘附剂213贴附于散热器201上。插入环部分208a-208d更由连接杆(tie bar)241a-241d支撑，连接杆241a-241d嵌入于塑料模铸物204内。引脚框205用于提供电性绝缘的引脚250。各个插入环部分208a-208d以接合线连结至引脚250的其中之一。此外，插入环部分208b和208d通过导电性环氧树脂(electrically conductive epoxy)240电性连接至散热器201，用于连接至接地端。或者，以点焊(spot welding)或其它适合的方式将插入环部分208b和208d电性连接至散热器201。插入环208的设计是环绕并尽可能靠近半导体芯片211，但不与其接触。因此，在半导体芯片211与引脚250之间的接合线可能非常短。于是此非常短的接合线具有低电感，因而，降低了封装体200的寄生阻抗(parasitic impedance)，由此提升封装体200的电性效能。由于插入环部分208a-208d位于封装体200的内部，且可迅速存取用以连接，所以引脚框205上用于电源与接地连结的引脚数目因而减少。由此可有效地增加封装体200的可用的引脚数。然而，封装体200的缺点为其引脚所产生的电感仍非常大，因此不利于电源完整性。
相关技术还公开一种引脚框型半导体封装体及其制造方法。嵌入式及/或裸露式散热器设置于芯片与引脚框之间，以提升其电性与散热效能。
图3为现有技术的芯片于散热器上的引脚框型(Chip On Heat SinkLeadFrame，简称COHS-LF)封装体的剖面示意图。请参阅图3，COHS-LF封装体300包括芯片330以粘附材料342贴附于引脚框336上，引脚框336整合于散热器360的结构上。引脚框336包括内引脚362和外引脚364。介电层344夹置于引脚框336与散热器360之间。芯片330的引线焊盘(bond pad)332透过接合线334电性连接至内引脚362。封装材料338封闭芯片330、散热器360及芯片330与内引脚362之间的接合线334。在将散热器360贴附于芯片330的正面后，将COHS-LF封装体300接地，以改善其散热性并控制引脚的阻抗。此COHS-LF封装体300的缺点为无法兼容于标准引脚框型封装工艺且散热器仅供接地网络用。
有鉴于此，业界亟需一种新型的半导体封装体及兼容的工艺，可满足兼具高效能与低制造成本的优点，且应用于整合高速组件领域的需求，例如利用系统级封装体(System in Package，SiP)，以整合射频(Radio Frequency，RF)芯片和基频(Base Band，BB)芯片或者数字电视(DTV)芯片和双数据率(Double DataRate，DDR)同步动态随机存取存储器(Synchronous Dynamic Random AccessMemory，SDRAM)芯片。
发明内容
为解决上述封装体的散热效能与电性效能，本发明提供一种系统级封装体，可同时改善散热效能与电性效能。
本发明的实施方式提供一种系统级封装体，包括：引脚框，其具有延伸的引脚并配置有多个分开的散热器，散热器是作为电源及接地网络；一对半导体芯片，以粘附材料贴附于引脚框的中央区域；芯片踏板，设置于该对半导体芯片之间，用以支撑该对半导体芯片，并且所述芯片踏板位于散热器之上；多条接合线，将该对半导体芯片分别电性连接至引脚框与分开的散热器；以及封装材料封闭引脚框，然而露出延伸的引脚和分开的散热器。
本发明的实施方式另提供一种系统级封装体的制造方法，包括：装配引脚框，其具有延伸的引脚并配置有多个分开的散热器；以粘附材料贴附一对半导体芯片于引脚框的中央区域；在所述的一对半导体芯片之间设置一芯片踏板，用以支撑所述的一对半导体芯片，并且所述芯片踏板位于散热器之上；以接合线，将该对半导体芯片分别电性连接至引脚框与分开的散热器；以及模压封装材料，以封闭引脚框，然而露出延伸的引脚和分开的散热器。
上述系统级封装体及其制造方法，通过为引脚框配置多个分开的散热器与封装材料露出散热器，提高了系统级封装的散热效能；通过接合线分别连接半导体芯片与散热器，提高了系统级封装体的电性效能。
附图说明
图1A-1D为现有技术的QFP的剖面示意图，其具有不同类型的散热器，以改善其热效能。
图2A为现有技术的EDHS-QFP封装体的剖面示意图。
图2B为移开塑料模铸物的封装体的立体示意图。
图3为现有技术的COHS-LF封装体的剖面示意图。
图4A为根据本发明的一实施方式的LOHS-SiP的剖面示意图。
图4B为图4A的LOHS-SiP的平面示意图。
图5A-5H为根据本发明的一实施方式的LOHS结构的各工艺步骤的剖面示意图。
图6A-6H为根据本发明另一实施方式的LOHS结构的各工艺步骤的剖面示意图。
图7为根据本发明实施方式散热器的裸露面的局部放大示意图。
图8为SiP、引脚的几何结构及所用的材料之间关系的仿真模型示意图。
图9为根据本发明的一实施方式的散热器分成多个电源及接地网络的示意图。
图10A为根据本发明另一实施方式的LOHS-SiP的平面示意图。
图10B为根据本发明又一实施方式的包含RF与BB堆叠芯片的LOHS-SiP的平面示意图。
具体实施方式
以下以各实施方式详细说明并伴随着图式说明的范例，作为本发明的参考依据。在图式或说明书描述中，相似或相同的部分皆使用相同的标号。且在图式中，实施方式中组件的形状或厚度可扩大，以简化或是方便标示。再者，图式中各组件的部分将分别描述说明，值得注意的是，图中未绘示或描述的组件，为本技术领域的技术人员所知的形式，另外，特定的实施方式仅为揭示本发明使用的特定方式，其并非用以限定本发明。
图4A为根据本发明的一实施方式的引脚在散热器上的系统级封装体(LeadOn Heat Sink System in Package，LOHS-SiP)的剖面示意图，图4B为图4A的LOHS-SiP的平面示意图。LOHS-SiP 400包括具有延伸的引脚442的引脚框440，其配置有多个分开的散热器430a-430d，以作为电源(PWR)及接地(GND)网络。介电层435夹置于引脚框440与分开的散热器430a-430d之间。一组半导体芯片420和450，以粘附材料贴附于引脚框的中央区域。半导体芯片420和450为一组垂直堆叠的半导体芯片对，半导体芯片对包括数字芯片和模拟芯片、射频(Radio Frequency，RF)芯片和基频(Base Band，BB)芯片、或数字信号处理(DSP)芯片和双数据率(Double Data Rate，DDR)同步动态随机存取存储器(SynchronousDynamic Random Access Memory，SDRAM)芯片。多条接合线450a-450e，将半导体芯片420和450分别电性连接至引脚框440与分开的散热器430a-430d。封装材料460封闭(enclose)引脚框440，然而露出延伸的引脚442和分开的散热器430a-430d，露出散热底部。
LOHS-SiP 400更包括互连部分(interconnection section)432，通过接合线450d、450e作为电性连接半导体芯片420和450与分开的散热器430b之间的中间架桥体。芯片踏板(die paddle)436可选择性地设置于引脚框440的中央区域，用以支撑该组半导体芯片420和450。LOHS-SiP 400可通过焊料(solder)470和475置于印刷电路板(Printed Circuit Board，PCB)480上。
引脚框与散热器可由兼容的半导体工艺技术制造，之后再与堆叠的芯片组结合。额外加的散热器不仅可促进散热效率，还可产生多个电源面和接地面。例如，散热器可被预先分离成多个电源/接地区域，以减少引脚的数目并进一步降低封装体的尺寸。由于引脚的数目得以减少，此SiP具有较佳的信号完整度与电源完整度，也可达成较密的引脚间距(lead pitch)。更有甚者，电源/接地区域可进一步电性连结至芯片上对应的电源与接地垫(pad)，并接着焊接至PCB上的电源与接地网络。并且，由于电源与接地并不需要透过LOHS-SiP的引脚，因此能使得LOHS-SiP获得更多空间，以设计供高速系统应用的引脚的几何结构，或缩减封装体尺寸。
图5A-5H为根据本发明的一实施方式的LOHS结构的各工艺步骤的剖面示意图。请参阅图5A，首先分别提供顶金属层510、介电材料层520与底金属层530。顶金属层510与底金属层530的材料可为金属(例如铜及铝)或合金(例如C7025、A42及A192)。介电材料层520可为阻燃型环氧玻璃纤维板(flame-retardant substrate，FR-4)、双马来酰亚胺三嗪树脂(Bismaleimide-Triazine，BT)、陶瓷、环氧树脂预浸材料(epoxy prepeg)、聚酰亚胺(polyimide，PI)胶带及粘结膜。接着，如图5B所示，压合顶金属层510、介电材料层520与底金属层530成组合体。
请参阅图5C，蚀刻顶金属层510，以形成引脚框，其具有延伸的引脚、开口515a及中央作为芯片踏板512的高台区域。另一方面，如图5D所示，蚀刻底金属层530以形成凹入区域535供芯片贴附，及多个分开的散热器供电源/接地(PWR/GND)网络。
请参阅图5E，形成多个穿透组合体的通孔540，作为后续以接合线连结的芯片窗口(chip opening)。接着，如图5F所示，以顶金属层510作为屏蔽层(mask)，移除开口515a内露出的介电材料层520。
请参阅图5G，接着，应用防焊漆(solder mask)572，覆盖后续不希望电镀的区域。并且由于引脚框的外围区域的防焊漆572的形成，可同时省略现有技术的形成障碍杆(dam bar)的步骤。接着，如图5H所示，将金属层550电镀于顶金属层510(即引脚框)上。金属层550的材料包括单一金属层(例如金(Au)、银(Ag)、镍(Ni)、铜(Cu)或钯(Pd))，或者用不同的金属迭层(different metal laminated)电镀以强化接合线与引脚之间的粘结性。
图6A-6H为根据本发明另一实施方式的LOHS结构的各工艺步骤的剖面示意图。应注意的是，图6A-6H实施方式的LOHS结构的工艺步骤，实质上与图5A-5H实施方式的LOHS结构的工艺步骤相似，在此省略其相同工艺步骤的详细叙述。上述两种工艺步骤的不同之处在于，本实施方式在顶金属层的蚀刻步骤后，移除中央芯片踏板，如图6C所示。因而，形成中央位置的开口515b，且堆叠的芯片可粘附于散热器的两侧。再者，应注意的是，若散热器于图5B所示的压合成组合体的步骤前，预先分成多个电源/接地区域、形状与穿孔，则可省略后续的图5D-5E所示的步骤。
由于上述LOHS结构包括防焊漆，因此注入模铸材料的接触区域为平坦区域。就其本身而言，现有技术的的障碍杆设计为非必要的，因此现有技术的后续的去除多余的残胶与/或切除不需要的连接用材料及部分凸出的树脂(deflash/trim或dejunk/trim)的步骤亦可省略。
图7为根据本发明实施方式散热器的裸露面的局部放大示意图。模铸(molded)的封装材料560封闭LOHS结构，然而露出分开的散热器530的散热面530’。散热面530’包括多个凸起物(protrusion)或凸起块(bump)，以改善树脂(resin)与分开的散热器530之间的粘结性。再者，由于裸露的散热面530’表面包括小沟槽，可消除由热膨胀系数(Coefficient Thermal Expansion，CTE)不匹配所造成的热应力。
上述位于引脚下方的接地的散热器530允许对阻抗的控制。例如，图8为SiP、引脚的几何结构及所用的材料的仿真模型示意图。引脚框具有延伸的引脚631-638(引脚634与635为目标引脚)，并且引脚框配置有多个分开的散热器610，以作为电源及接地网络。介电层620夹置于引脚框与分开的散热器610之间。封装材料640平坦地覆盖封装体。通过调整引脚的几何结构及介电层620与封装材料640的厚度，目标引脚634与635可设计成所希望的阻抗，例如所需求的单端阻抗为50Ω以及差动阻抗为100Ω，以具有较佳的信号完整性。
热量由高温的芯片流向低温的外界环境。因此，芯片与外界环境之间的较高的热传导系数(κ)，可加速热移除速率(例如铜κ≈400W/mK)。对将芯片表面贴附于裸露的散热器的封装体进行散热性与电性分析的结果显示，相较于现有技术的球栅列阵封装(Ball Grid Array，BGA)封装与引脚在芯片上的薄型小尺寸封装(Lead On Chip-Thin Small Outline PackageLOC-TSOP)封装，其具有较少的温度增加量，较低的信号损失以及较小的串音(cross-talk)。
图9为根据本发明的一实施方式的散热器830分成多个电源及接地网络803a-830d的示意图。相对于现有技术的QFP封装体，由于LOHS-QFP具有较短的接合线及较大的电源及接地网络，因此可预期LOHS-QFP具有较低的寄生参数。
图10A为根据本发明另一实施方式的LOHS-SiP的平面示意图。LOHS-SiP900包括多重芯片堆叠的应用。现有技术的DSP芯片与DDR SDRAM芯片堆叠的缺点为DDR SDRAM芯片的焊接区(bonding pad)必须设置在芯片的中央位置，使得需较长的接合线，进而导致接合线偏移(wire sweep)、较差的电性及较低的制造良率的问题。
请参阅图10A，LOHS-SiP 900包括多个分开的散热器930a-930d，其贴附于上芯片(DSP芯片)910和下芯片(SDRAM芯片)920。散热器(包括分开的散热器930a-930d)包括开口940，开口940环绕芯片焊盘(chip-bonding pad)925，因此可获得较短的接合线950a和950b。下芯片920通过接合线950a通过散热器930上适当的开口940而与上芯片910电性互连。因此，接合线950a的长度可有效地缩短，进而获得较佳的电性效能，且部分的终端亦可因而省略。根据本发明实施方式，可在散热器中两邻近的分开的散热器的外围区域，增加额外的至少一个被动组件980，例如电容组件或电感组件。此外，由于芯片踏板905可作为上、下芯片910和920之间的缓冲区域，因此能有效提升封装体的制造良率(package yield)。同时，由于上金属层(引脚框)可蚀刻成互连部分(interconnectionsection)936a和936b，因此可进一步降低接合线950b和950c的长度。
图10B为根据本发明又一实施方式的包含RF与BB堆叠芯片的LOHS-SiP的平面示意图。包含RF与BB堆叠芯片的LOHS-SiP 1000包括多个分开的散热器1030，其贴附于上芯片(RF芯片)1010和下芯片(BB)1020。散热器1030包括开口1015，开口1015环绕芯片连结座1022，因此可获得较短的接合线1050b。下芯片1020通过接合线1050d通过互连部分1046或共享杆(common bar)而与上芯片1010电性连接。因此，可避免接合线的交越(crossover)情形发生。再者，由于芯片踏板1045可作为上、下芯片1010和1020之间的缓冲区域，因此还能有效提升封装体的制造良率。并且芯片踏板1045可有效地阻隔RF信号干扰。
虽然本发明已以实施方式揭露如上，但是对于本领域的技术人员，依据本发明实施方式的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (16)

1.一种系统级封装体，其特征在于，包括：
引脚框，具有多个延伸的引脚，该引脚框配置有多个分开的散热器，该多个分开的散热器是作为电源及接地网络；
一对半导体芯片，以粘附材料贴附在所述的引脚框的中央区域；
一芯片踏板，设置于所述的一对半导体芯片之间，用以支撑所述的一对半导体芯片，并且所述芯片踏板位于散热器之上；
多条接合线，将所述的一对半导体芯片分别电性连接至所述的引脚框与所述的多个分开的散热器；
以及
封装材料，封闭所述的引脚框，然而露出所述的多个延伸的引脚和所述的多个分开的散热器。
2.如权利要求1所述的系统级封装体，其特征在于，所述的一对半导体芯片包括一对垂直堆叠的半导体芯片。
3.如权利要求2所述的系统级封装体，其特征在于，所述的一对垂直堆叠的半导体芯片包括数字芯片和模拟芯片、射频芯片和基频芯片、或数字信号处理芯片和存储器芯片。
4.如权利要求1所述的系统级封装体，其特征在于，还包括互连部分，通过所述的多条接合线作为电性连接所述的一对半导体芯片与所述的多个分开的散热器之间的中间架桥体。
5.如权利要求4所述的系统级封装体，其特征在于，所述的互连部分设置于跨接两邻近的所述的多个分开的散热器之间。
6.如权利要求1所述的系统级封装体，其特征在于，所述的多个分开的散热器的散热面包括多个凸起物。
7.如权利要求1所述的系统级封装体，其特征在于，所述的多个分开的散热器的散热面包括多个凸起块。
8.如权利要求1所述的系统级封装体，其特征在于，还包括介电层，夹置于所述的引脚框与所述的多个分开的散热器之间。
9.如权利要求1所述的系统级封装体，其特征在于，还包括至少一被动组件，位于所述的多个分开的散热器的外围区域。
10.一种系统级封装体的制造方法，其特征在于，包括：
装配引脚框，该引脚框具有多个延伸的引脚并配置有多个分开的散热器；
以粘附材料贴附一对半导体芯片于所述的引脚框的中央区域；
在所述的一对半导体芯片之间设置一芯片踏板，用以支撑所述的一对半导体芯片，并且所述芯片踏板位于散热器之上；
以多条接合线，将所述的一对半导体芯片分别电性连接至所述的引脚框与所述的多个分开的散热器；以及
模铸封装材料，以封闭该引脚框，然而露出所述的多个延伸的引脚和所述的多个分开的散热器。
11.如权利要求10所述的系统级封装体的制造方法，其特征在于，装配所述的引脚框的步骤包括：
提供顶金属层、介电材料与底金属层；
将所述的顶金属层、所述的介电材料与所述的底金属层压合成组合体；
蚀刻所述的顶金属层以形成所述的引脚框，该引脚框具有所述的多个延伸的引脚与位于其中央区域的开口；
蚀刻所述的底金属层，以形成所述的多个分开的散热器；
形成穿透所述的组合体的多个通孔；
移除所述的开口内的所述的介电材料；
在所述的引脚框的外围区域形成防焊漆；以及
在所述的引脚框上电镀金属层。
12.如权利要求10所述的系统级封装体的制造方法，其特征在于，装配所述的引脚框的步骤包括：
分别提供顶金属层、介电材料与底金属层；
将所述的顶金属层、所述的介电材料与所述的底金属层压合成组合体；
蚀刻所述的顶金属层，以形成所述的引脚框，所述的引脚框具有所述的多个延伸的引脚以及位于其中央区域的具有芯片踏板的开口；
蚀刻所述的底金属层，以形成所述的多个分开的散热器；
形成多个通孔，穿透该组合体；
移除所述的开口内的所述的介电材料；
在所述的引脚框的外围区域形成防焊漆；以及
在所述的引脚框上电镀金属层。
13.如权利要求10所述的系统级封装体的制造方法，其特征在于，所述的多个分开的散热器包括散热面，该散热面包括多个凸起物。
14.如权利要求10所述的系统级封装体的制造方法，其特征在于，所述的多个分开的散热器包括散热面，该散热面包括多个凸起块。
15.如权利要求10所述的系统级封装体的制造方法，其特征在于，所述的一对半导体芯片的贴附包括在所述的引脚框的中央区域的两侧垂直堆叠一对半导体芯片，所述的一对半导体芯片包括数字芯片和模拟芯片、射频芯片和基频芯片、或数字信号处理芯片和存储器芯片。
16.如权利要求10所述的系统级封装体的制造方法，其特征在于，还包括将所述的系统级封装体组装于印刷电路板上。
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