CN108417499A - 空腔封装结构及其制造方法 - Google Patents

空腔封装结构及其制造方法 Download PDF

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Publication number
CN108417499A
CN108417499A CN201611134822.4A CN201611134822A CN108417499A CN 108417499 A CN108417499 A CN 108417499A CN 201611134822 A CN201611134822 A CN 201611134822A CN 108417499 A CN108417499 A CN 108417499A
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China
Prior art keywords
lead
cooling fin
cavity
intermediate structure
lead frame
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Pending
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CN201611134822.4A
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English (en)
Inventor
张小平
单智慧
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Ubotic Co ltd
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Ubotic Co ltd
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Publication of CN108417499A publication Critical patent/CN108417499A/zh
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    • H01L24/93—Batch processes
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

本申请提供了一种空腔封装结构及其制造方法。根据本申请的一个实施例，所述制造方法包括将一个金属散热片通过一个中间结构连接在一个引线框架上，所述中间结构导热且电绝缘；模塑一个塑料体以包围散热片及引线框架裸露的引线，且有选择地和部分地暴露金属引线上表面、散热片上表面、以及散热片下表面；通过一种导热材料将一个半导体芯片与空腔内散热片暴露的上表面相连；将半导体芯片的焊盘和与之对应的引线上表面进行引线接合从而使其接地；以及在塑料体上安装一个盖子，以保护空腔内引线接合后的半导体芯片。

Description

空腔封装结构及其制造方法
交叉引用
本申请要求2015年12月11日提交的申请号为14/966,636的美国申请，其内容以引用方式被包含于此。
技术领域
本申请主要涉及集成电路，特别是一种大功率高频预成型塑料空腔封装集成电路以及一种气密封装的大功率高频预成型空腔封装集成电路。
背景技术
现有技术已经披露了通过陶瓷空腔封装和内置散热片的塑料模塑封装来封装大功率高频电子元件(例如大功率射频晶体管)。陶瓷空腔封装在设计中包含了一个充满空气或氮气的空腔，且在空腔中安装了一个半导体芯片(亦称作集成电路、芯片等)，而塑料模塑封装则基本不含空气。这些封装的基本结构包括一个安装有半导体芯片的引线接合焊盘、导热散热片或使芯片散热的装置、供半导体芯片输入或输出信号的金属引线、以及一个盖子。在空腔封装中，盖子为金属材质，而在塑料模塑封装中，塑料体全部为塑料材质模塑(例如二次注塑)成型，但散热片的一部分暴露在外。
现有技术中的陶瓷空腔封装由于材料的缘故导致其成本较高，由于采用了陶瓷铜基层压材料作为散热片而使其热性能较差，且无法进行大规模生产。
内含散热片的塑料模塑工艺的研发背景原因之一是为了改善陶瓷空腔封装热特性差的问题。塑料封装将芯片安装在一片铜制散热片上，而不使用之前技术所使用的陶瓷铜基外敷材料，因此安装在铜制散热片上时的芯片的热阻值与使用陶瓷铜基外敷材料散热的空腔封装中的芯片的热阻值相比会有所降低。
此外，现有技术中的陶瓷空腔封装一般需要逐个组装，而塑料封装则可以通过一个引线框架结构成批生产。因此可以加快生产速度，减少人工操作。
然而，内含散热片的塑料模塑封装的缺点在于不包含空腔，且由于散热片上表面不与引线框架下表面直接接触，缺乏较理想的从引线框架到散热片的导热路径。
简述
本申请提供了一种能够至少部分改善现有陶瓷和塑料模塑封装技术的缺点的空腔封装结构和制造方法。本申请的一个实施例中，包括将一片金属散热片通过一个中间结构连接在一个引线框架上，所述中间结构导热且电绝缘。通过塑料体包围集成的散热片和引线框架，以形成空腔，且有选择地和部分地暴露引线表面以及散热片的上下表面。芯片安装在空腔内散热片暴露的上表面之上，并引线接合至引线表面上。最后，在塑料体上加装一个盖子以将空腔密封。
根据第一个实施例的另一个方面，还提供了一种制造方法，包括将一片金属散热片通过一个中间结构连接在一个引线框架上，所述中间结构导热且电绝缘；模塑一个塑料体包围散热片和引线框架暴露的引线，以形成一个空腔，且有选择地和部分地暴露引线上表面、散热片的上表面、以及散热片的下表面；通过一种导热材料将一个半导体芯片安装在散热片暴露的上表面之上；并将芯片的焊盘引线接合至与之对应的引线上表面上以进行接地；以及在塑料体上加装一个盖子以保护空腔内引线接合好的半导体芯片。
根据本申请的第二个实施例，将一个金属散热片通过第一环状中间结构连接到引线框架上，所述第一环状中间结构导热且电绝缘。此外，在引线框架顶部安装导热且电绝缘的第二环状中间结构。在一些实施例中，优选地，每一个环状结构为上下两片薄金属片分别与一个陶瓷中间部分的上下表面连接的“夹层”结构。第一环状结构的金属部分上表面粘接至所对应金属引线的下表面，且第一环状结构的金属部分下表面粘接至散热片之上。第二环状中间结构的底部金属部分粘接至金属引线所对应的上表面之上。模塑一个塑料体包围集成的散热片及引线框架以形成一个空腔，且有选择地和部分地暴露金属引线、散热片上下表面、以及第二环状中间结构的金属部分上表面，所述环状中间结构导热且电绝缘。半导体芯片安装在空腔内散热片暴露的上表面之上，并引线接合在引线表面上。最后，在塑料体上安装一个金属盖子，以密封空腔。
根据本申请第二个实施例的另一个方面，还提供了一种制造方法，包括将一个金属散热片通过一个中间结构连接到一个引线框架上，所述中间结构导热且电绝缘；模塑一个塑料体包围散热片及引线框架裸露的引线以形成一个空腔，且有选择地和部分地暴露引线上表面、散热片上表面、以及散热片下表面；通过一种导热材料将一个半导体芯片安装在空腔内散热片暴露的上表面之上；并将芯片的焊盘引线接合至与之对应的引线上表面上以进行接地。最后，在塑料体上安装一个金属盖子以保护空腔内引线接合好的半导体芯片。
根据本申请的另一个方面，所述金属散热片原材料包括铜，或其它合金。
根据本申请第一个实施例的一个变形，所述中间结构为陶瓷材质。
根据本申请的另一个方面，所述引线框架，优选地，包括一个矩形外框架。
根据本申请第一个实施例的另一个方面，所述导热材料包括银胶(银环氧树脂)或焊料。
根据本申请第一个实施例的另一个方面，所述盖子通过环氧树脂固定在所述塑料体之上。
根据本申请第一个实施例的另一个方面，所述盖子由液晶聚合物、环氧树脂塑封料、金属或其它合适的材料制成。
根据本申请第一个实施例的另一个方面，提供了一种空腔封装结构，包括一个包围并部分暴露一个集成的散热片和引线框架的引线的塑料体，和一个盖子。
根据本申请第一个实施例的另一个方面，所述空腔封装包含从引线框架两侧延伸出的一对引线。
根据本申请第一个实施例的另一个方面，所述空腔封装的引线中，从引线框架每一侧延伸出至少两只引线。
根据本申请第二个实施例的另一个方面，每一个所述的“夹层”中间结构均包括直接键合铜(DBC，在陶瓷的上下表面分别连接一片薄铜片)的陶瓷。由于中间陶瓷部分的作用，上下两片薄铜片相互电绝缘。陶瓷部分的形状和薄铜片的形状可以由本领域普通技术人员所知的方法设计和制造。第一中间结构的底部薄铜片与散热片的顶部粘接(例如使用银胶或焊接)。在一些实施例中，底部薄铜片的形状为一整个圆环。由于顶部的薄铜片应与封装的两个引线底部粘接，且两引线在分离后应被电隔离，因此顶部薄铜片的形状可以为断开的圆环形状(例如，对于一个两引线的设计来说，一个像“[]”的形状)。
根据本申请第二个实施例的另一个方面，所述第一和第二中间结构的导热材料包括银胶或焊料。
根据本申请第二个实施例的另一个方面，所述盖子连接(例如焊接)在所述金属引线之上的第二环状中间结构上
根据本申请第二个实施例的另一个方面，所述盖子可以由铜，镀镍和/或锡不锈钢制成，以使焊接过程更加容易。
本申请所提供的空腔封装体积小，重量轻，且热特性和电气特性均较为良好，适合应用于大功率高频使用环境中。本申请所提供的空腔封装与陶瓷空腔封装由于使用了更加常见的材料(例如铜和环氧树脂塑封料)，成本更加低廉，且其多引线框架结构使其可以用于大规模生产当中。
本申请所提供的空腔封装通过集成的散热片将芯片和线路产生的热量发散到引线框架和中间结构中，因此适合用于高频元件(例如射频开关晶体管)。由于芯片和引线接合丝线均位于含有空气的空腔(在高速应用环境当中，空气的介电常数最优)当中，可以用于高频使用环境中。
附图说明
通过以下结合附图一起以示例方式说明本发明的特征的详细描述，将清楚本发明的特征和优点，其中:
图1A和图1B分别是根据第一示例性实施例的空腔封装的顶部透视图和底部透视图。
图2是制造图1A和图1B所示空腔封装的方法流程图。
图3A和图3B分别是根据图2所示的方法，表示散热片和引线框架底部的连接的顶部透视图和底部透视图。
图4A和图4B分别是从两个侧边观察到的顶部透视图，表示根据图2所示的方法将塑料体模塑在图3A和图3B所示的集成的散热片和引线框架上以形成空腔。
图4C是表示根据图2所示的方法将塑料体模塑在图3A和图3B所示的集成的散热片和引线框架的底部透视图。
图5A和图5B分别是根据图2所示的方法，表示半导体芯片(集成电路)连接在空腔内散热片的暴露部分的顶部透视图和平面图。
图6A和图6B分别是根据图2所示的方法，表示芯片通过引线接合连接至引线上表面的顶部透视图的细节和整体视图。
图7A和图7B分别是根据图2所示的方法，表示一个用于遮盖和密封空腔的盖子与空腔的连接的平面视图和顶部透视图。
图8A和图8B分别是根据第二示例性实施例的空腔封装的顶部透视图和底部透视图。
图9是制造图8A和图8B所示的空腔封装的方法流程图。
图10A和图10B分别是根据图9所示的方法，表示散热片和引线框架底部通过导热、电绝缘的环状结构相连的顶部透视图和底部透视图。
图10C，图10D和图10E分别是根据图9所示的方法，表示将一个导热、电绝缘的第二环状结构与引线框架顶部相连的顶部透视图、平面图和正视图。
图11A和图11B分别是根据图9所示的方法，表示塑料体模塑在图10A和图10B所示的集成的散热片和引线框架上以形成空腔的顶部透视图和底部透视图。
图12A和图12B分别是根据图9所示的方法，表示半导体芯片(集成电路)连接在空腔内散热片的暴露部分的顶部透视图和平面图。
图13A和图13B分别是根据图9所示的方法，表示将芯片引线接合至引线上表面的顶部透视图的细节和整体视图。
图14A和图14B分别是根据图9所示的方法，表示用于遮盖和密封空腔的金属盖子的平面视图和顶部透视图。
图15是制造图1A和图1B所示空腔封装的替代方法的流程图。
图16是图1A和图1B中所示的空腔封装的引线框架的顶部透视图。
图17是根据图15所示的制造空腔封装的替代方法，表示引线框架的一对引线各自向下弯曲成阶梯状的顶部透视图。
图18是根据图15所示的制造空腔封装的替代方法，表示散热片和引线框架底部相连的顶部透视图
现在将参考所说明的示例性实施例，并且这里将使用具体语言来描述它们。然而，要理解的是，并不希望其限制本发明的范围。
具体实施方式
在披露和描述本发明之前，要理解本发明不限于这里公开的特定结构、过程步骤或材料，而应当扩展到相关领域的普通技术人员将会认识到的等同物。还应当理解的是，这里采用的术语只是用于描述特定实施例，而并不打算进行限定。
参考图1A和图1B，根据第一示例性实施例，披露了一种大功率高频的塑料预成型空腔封装结构，包括塑料体110，该塑料体110包围并且部分暴露集成的散热片120和引线框架300的引线130(参见图3A和图3B)，以及盖子140。
参考图3A至图7B，根据图2描述的示例性方法步骤，披露了空腔封装100的构造。需要注意的是，图3A至图7B所示的是单空腔封装结构，在实践中，可以制造包含多个空腔封装的阵列，以同时制造多个封装，然后再分割为单个封装。
空腔封装的制造开始于步骤200(如图2所示)，利用导热、电绝缘的中间结构310将金属散热片(例如铜或其他金属合金)连接到引线框架300上。其中，中间结构310也可以为陶瓷材料。如图3A和图3B所示，引线框架300优选地包括形成多个重复单元之一(未示出)的矩形外框，以形成一个可以同时制造上述制造完成后的单个封装的阵列。此外，尽管只示出了一对引线130从引线框架的对边伸出，根据空腔封装的应用，每边可能伸出两条或以上引线。
在步骤210中，塑料体110被模塑在集成的散热片120和引线框架300的引线130的周围以形成空腔400，如图4A-4C所示，空腔400有选择地和部分地暴露的引线上表面410，散热片上表面420和散热片下表面430。暴露的散热片下表面430将空腔400的母板(未示出)上待耗散的热量传导到制造完成后该空腔封装所安置的地方。
在步骤220中，如图5A和图5B所示，半导体芯片500(即集成电路)被安置在空腔400中，位于暴露的散热片上表面420上且通过导热材料连接，例如通过银胶、焊接等。
在步骤230中，如图6A和图6B所示，半导体芯片500的各焊盘通过丝线600与暴露的引线上表面410连接，并与散热片120连接使其接地。例如，在大功率高频的应用如射频开关晶体管中，其中一只引线连接晶体管源极，另一只引线连接晶体管漏极，其中，晶体管薄片的漏极包括完整的芯片背面，则一旦芯片500接触散热片120时，散热片就成为漏极。芯片顶部包括源极焊盘和栅极焊盘，则其中一只引线可以与源极连接，而另一只引线可以与闸极连接。
最后，在步骤240中，盖子140与塑料体110通过环氧树脂连接，以保护空腔400中的引线接合装置。盖子可以是由液晶高分子、环氧树脂塑封料、金属或其他合适材料构成。
如上所述，在实践中，可以制造一个空腔封装阵列(未示出)，则在盖子140连接上后，可将该阵列分割(例如切割)为单个的，与图1A和图1B中所示封装类似的封装。
参考图8A和图8B，根据示例性实施例披露了一种大功率高频的塑料预成型空腔封装结构，包括塑料体110’，该塑料体包围或者部分暴露集成的散热片120’和引线框架300’的引线130’(参见图10A和图10B)，以及盖子140’。
参考图10A至图14B，根据图9描述的示例性方法步骤，披露了空腔封装100的构造。需要注意的是，图10A至图14B所示的是单空腔封装结构，在实践中，可以制造一个包含多个空腔封装的阵列，以同时制造多个封装然后再分割为单个封装。
空腔封装的制造开始于步骤200’(如图9所示)，利用导热、电绝缘的第一环状中间结构310’将金属散热片(例如铜或其他金属合金)连接到引线框架300’上。在一个实施例中，中间结构310’也可以为陶瓷和直接键合铜(DBC)的“夹层”结构，其中，在陶瓷中间部分的上下表面各连接一层薄铜片。陶瓷部分的形状以及薄铜片的样式对于本领域技术人员来说是可以被重新设计和制造的。第一中间结构的底部薄铜片与散热片的上表面连接(例如采用银胶或焊接)。在一个实施例中，如图10A所示，底部薄铜片的样式是完整的环形。由于顶部薄铜片是用于与封装的两只引线的底边连接，且两只引线在分离后被电隔离，因此顶部薄铜片的样式可以为断开的环形(例如，对于一个两引线的封装设计，采用“[]”形状)。
如图10A和图10B所示，引线框架300’优选地包括形成多个重复单元之一(未示出)的矩形外框，以形成一个可以同时制造上述制造完成后的单个封装的阵列。此外，尽管只示出了一对引线130’从引线框架的对边伸出，根据空腔封装的应用，每边可能伸出两条及以上引线。
第二导热、电绝缘的中间环状结构320’与引线框架300’的引线130’的上表面连接(步骤205’)。第二中间结构320’与第一结构310’的“夹层”结构类似。底部薄铜片与金属引线310’连接，则底部薄铜片的样式可以为断开的环形(例如“[]”)或平行线对，其中顶部薄铜片形成一个连接盖子的完整环形样式(如图14A和图14B所示)。
在步骤210’中，塑料体110’模塑在集成的散热片120’和引线框架300’的引线130’的周围以形成空腔400’，如图11-11C所示，空腔400’有选择地和部分地暴露的引线上表面410’，散热片上表面420’，散热片下表面430’和环状结构320’的上表面。暴露的散热片下表面430’将空腔400’的主板(未示出)上待消散的热量传导到制造完成后该空腔封装所安置的地方。
在步骤220’中，如图12A和图12B所示，半导体芯片500’(即集成电路)被安置在空腔400’中，位于暴露的散热片上表面420’上且通过导热材料连接，例如通过银胶、焊接等。
在步骤230’中，如图13A和图13B所示，半导体芯片500’的各焊盘通过丝线600’与暴露的引线上表面410’连接，并与散热片120’连接使其接地。例如，在大功率高频的应用下如射频开关晶体管，其中一只引线连接晶体管源极，另一只引线连接晶体管门，由于芯片背面整体被用做于漏极，则一旦芯片500接触散热片120时，散热片就成为漏极。芯片顶部包括源极焊盘和栅极焊盘，分别与相对应的两只引线130’的其中一只相连。
最后，在步骤240’中，金属盖140’与塑料体110’与第二中间结构320’的顶部暴露的环形结构焊接在一起。该金属盖140’比塑料盖坚固，比陶瓷便宜，而且可以由多种金属的其中一种构成，如铜、镀镍或锡不锈钢。
如上所述，在实践中，可以制造一个空腔封装阵列(未示出)，则在盖子140’连接上后，可将该阵列分割(例如切割)为单个的，与图8A和图8B中所示封装类似的封装。
图15是制造图1A和图1B所示空腔封装的替代方法的流程图，其中步骤210-240与图2中所示的方法一致。图15所示的替代方法是图2所示方法的低成本替代方法，因为它省去了中间结构310.
在步骤195中，如图16所示的引线框架300，通过按预定次数向下弯曲引线端部160以形成阶梯状结构(如图17所示)，从而用于和散热片120连接。
在步骤198中，金属散热片120(例如铜或其他金属合金)通过电绝缘连接体(例如非导电环氧树脂、双面胶等)与引线框架300的底部连接。
在散热片连接步骤198之后，还可以执行如图2中所描述的剩余的模塑步骤，芯片连接步骤，引线接合步骤和盖子连接步骤210-240.
根据本说明书的详细描述，本发明的许多特征和优点是显而易见的，因此，希望通过附带的权利要求覆盖所有落入本发明精神和范围的特征及优点。此外，对于本领域技术人员来说，很容易进行各种修改和改变，因此并不期望将本发明限制于所举例说明和描述的结构和操作，所有适当的修改和等价替换均被认为落入本发明的保护范围。

Claims (7)

1.一种空腔封装制造方法，包括：
通过一个中间结构，将一个金属散热片连接在一个引线框架上，所述中间结构导热且电绝缘；
模塑一个塑料体以包围所述散热片及所述引线框架裸露的引线从而形成一个空腔，且有选择地和部分地暴露所述引线的上表面、所述散热片的上表面、以及所述散热片的下表面；
通过一种导热材料将一个半导体芯片与所述空腔内所述散热片所暴露的上表面相连；
将所述半导体芯片的引线接合焊盘和与之对应的引线上表面以及所述散热片进行引线接合从而使其接地；以及
将一个盖子与所述塑料体相连接，以保护所述空腔内引线接合后的半导体芯片。
2.一种根据权利要求1所述方法制造的空腔封装，包括一个塑料体和一个盖子，所述塑料体包围并部分暴露一个集成的散热片和一个引线框架上的引线。
3.一种空腔封装制造方法，包括：
通过一个第一环状中间结构，将一个金属散热片连接在一个引线框架上，所述第一环状中间结构导热且电绝缘；
将一个第二环状中间结构与所述引线框架上方相连接，所述第二环状中间结构导热且电绝缘；
模塑一个塑料体以包围所述散热片及所述引线框架裸露的引线从而形成一个空腔，且有选择地和部分地暴露所述引线、所述散热片的上表面、所述散热片的下表面、以及导热且电绝缘的所述第二环状中间结构的顶部金属部分；
通过一种导热材料将一个半导体芯片与所述空腔内散热片所暴露的上表面相连；
将所述半导体芯片的引线接合焊盘和与之对应的引线上表面以及所述散热片进行引线接合从而使其接地；以及
通过与所述第二环状中间结构的顶部金属部分进行焊接，将一个金属盖子与所述塑料体进行连接，以保护空腔内引线接合后的半导体芯片。
4.一种根据权利要求3所述方法制造的空腔封装，其中，所述第一环状中间结构和第二环状中间结构分别包括两个薄金属部分和一个陶瓷部分，所述两个薄金属部分分别与所述陶瓷部分的上下表面相连。
5.权利要求4所述的空腔封装，其中，所述第一环状中间结构的顶部金属部分的两侧分别与所述金属引线的各下表面相连接，且所述第一环状中间结构的下表面与所述散热片相连接。
6.权利要求5所述的空腔封装，其中，所述第二环状中间结构的底部金属部分的两侧分别与所述金属引线各上表面相连接。
7.一种空腔封装制造方法，包括：
将一个引线框架的引线尖端弯折成阶梯状结构；
通过一个电绝缘连接体将一个金属散热片连接在所述引线框架上；
模塑一个塑料体以包围所述散热片及所述引线框架裸露的引线从而形成一个空腔，且有选择地和部分地暴露所述引线上表面、所述散热片上表面、以及所述散热片下表面；
通过一种导热材料将一个半导体芯片与所述空腔内散热片所暴露的上表面相连；
将所述半导体芯片的引线接合焊盘和与之对应的裸露的引线上表面以及所述散热片进行引线接合从而进行接地；以及
将一个盖子与所述塑料体相连接，以保护空腔内引线接合后的半导体芯片。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10458826B2 (en) * 2017-08-25 2019-10-29 Ubotic Company Limited Mass flow sensor module and method of manufacture
IT201700103511A1 (it) * 2017-09-15 2019-03-15 St Microelectronics Srl Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione
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US20230395447A1 (en) * 2022-06-06 2023-12-07 Lunar Energy, Inc. Transistor package construction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070029664A1 (en) * 2005-08-05 2007-02-08 Cree Microwave, Llc. Integrated circuit package and method of assembling the same
CN101297404A (zh) * 2005-12-24 2008-10-29 崔显圭 半导体封装，制造半导体封装的方法，以及用于图像传感器的半导体封装模块
US20120051000A1 (en) * 2010-08-31 2012-03-01 Viasat, Inc. Leadframe package with integrated partial waveguide interface
CN102593336A (zh) * 2011-01-17 2012-07-18 三星Led株式会社 发光器件封装件及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077616A1 (en) * 2003-10-09 2005-04-14 Ng Kee Yean High power light emitting diode device
DE102008021618A1 (de) * 2007-11-28 2009-06-04 Osram Opto Semiconductors Gmbh Chipanordnung, Anschlussanordnung, LED sowie Verfahren zur Herstellung einer Chipanordnung
US8963303B2 (en) * 2013-02-22 2015-02-24 Stmicroelectronics S.R.L. Power electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070029664A1 (en) * 2005-08-05 2007-02-08 Cree Microwave, Llc. Integrated circuit package and method of assembling the same
CN101297404A (zh) * 2005-12-24 2008-10-29 崔显圭 半导体封装，制造半导体封装的方法，以及用于图像传感器的半导体封装模块
US20120051000A1 (en) * 2010-08-31 2012-03-01 Viasat, Inc. Leadframe package with integrated partial waveguide interface
CN102593336A (zh) * 2011-01-17 2012-07-18 三星Led株式会社 发光器件封装件及其制造方法

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