CN101471317A - 引线框架封装及引线框架 - Google Patents

引线框架封装及引线框架 Download PDF

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Publication number
CN101471317A
CN101471317A CNA2008101878179A CN200810187817A CN101471317A CN 101471317 A CN101471317 A CN 101471317A CN A2008101878179 A CNA2008101878179 A CN A2008101878179A CN 200810187817 A CN200810187817 A CN 200810187817A CN 101471317 A CN101471317 A CN 101471317A
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China
Prior art keywords
pad
nude film
lead
pad portion
exposed pads
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CNA2008101878179A
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CN101471317B (zh
Inventor
陈南璋
林泓均
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US12/177,879 external-priority patent/US7834435B2/en
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Publication of CN101471317A publication Critical patent/CN101471317A/zh
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Abstract

本发明涉及引线框架封装及引线框架。引线框架封装包含裸片垫、半导体裸片、引脚、第一裸露焊盘部分与第二裸露焊盘部分、导线以及模塑材料。半导体裸片粘附于裸片垫。引脚沿裸片垫的四个外围边缘设置。第一裸露焊盘部分设置在引脚与裸片垫之间。第二裸露焊盘部分与第一裸露焊盘部分分隔开，并且设置在第一裸露焊盘部分与裸片垫之间。多条导线分别电性耦接并且延伸至半导体裸片与各引脚、第一裸露焊盘部分及第二裸露焊盘部分之间。模塑材料至少部分封装裸片垫、引脚、第一裸露焊盘部分与第二裸露焊盘部分以及导线，其中裸片垫、第一与第二裸露焊盘部分的底面未被模塑材料覆盖。上述引线框架封装形成分开的接地系统，避免了噪声，并且减少信号损失。

Description

引线框架封装及引线框架
技术领域
本发明是有关于一种用于半导体装置的引线框架，且特别是关于包含多个裸露的焊盘(exposed pad)的引线框架封装及其制造方法。
背景技术
现有技术的半导体裸片(die)封闭(enclose)在塑料封装中，塑料封装提供针对恶劣环境的防护，并且启用半导体裸片与基板(substrate)之间的电性互连，例如，基板为印刷电路板(Printed Circuit Board，以下简称为PCB)。这样的集成电路封装包含金属引线框架，半导体裸片与连接线(bond wire)。半导体裸片安装在引线框架的单一裸片垫上，并且连接线将半导体裸片上的连接垫(bond pad)电性耦接至引线框架的单独的引脚。最后，引线框架与半导体裸片封装在模塑材料(molding compound)中。
后端封装产业(back-end packaging industry)的技术趋势能够总结为“更小空间中的更多功能”。集成电路芯片(chip)的功能变得越来越复杂，使得引线框架封装的外部连接针脚(pin)的数量增加。随着针脚数量的增加，封装各裸片的成本相应增加。为避免由于连接针脚或者引脚数目增多而引起的所不希望的封装大小的增加，可以采用降低引脚间距(lead pitch)的方法。然而，缩减引脚间距会导致由封装的引脚产生的互感(mutual inductance)与互容(mutual capacitance)水平的提高。因为相对较高的电感与电容可能干扰所传输的信号，所以一般认为引线框架封装并不适用于以高速来传输信号的高速半导体裸片。
考虑到上述问题，一般地，许多配备能够传输高频信号的半导体裸片的移动通信装置(例如移动电话)与个人通信装置采用适应此种半导体裸片的球栅阵列(Ball Grid Array，以下简称为BGA)封装。假若上述半导体裸片安装或者封装在引线框架封装中，则会产生明显的信号损失或者噪声问题，例如交流噪声(ACnoise)问题。
然而，BGA封装的缺陷在于，与引线框架封装相比，BGA封装较贵，并且BGA封装的一贯制程所需时间(Turn-Around-Time，以下简称为TAT)较长。此外，发展射频系统芯片(Radio-Frequency System-on-Chip，RF-SoC)的挑战在于：难以降低射频与模拟电路的功率消耗，并且难以降低被动组件以及模拟晶体管的大小。
因此，业界亟需改进的引线框架结构以及引线框架封装，以具有成本效益，并且特别适用于高速半导体裸片，以及当传输高频信号时，能够降低信号损失或者噪声。
发明内容
为解决上述传输高频信号时，引线框架及引线框架封装产生噪声或者信号损失的问题，本发明提出一种引线框架与引线框架封装，能够降低信号损失或者噪声。
本发明提供一种引线框架封装，包含裸片垫、半导体裸片、引脚、第一与第二裸露焊盘部分、导线以及模塑材料。半导体裸片粘附于裸片垫。引脚沿着裸片垫的四个外围边缘设置。第一裸露焊盘部分设置在引脚与裸片垫之间。第二裸露焊盘部分与第一裸露焊盘部分分隔开，并且设置在第一裸露焊盘部分与裸片垫之间。多条导线分别电性耦接并且延伸至半导体裸片与各引脚、第一裸露焊盘部分及第二裸露焊盘部分之间。模塑材料至少部分封装裸片垫、引脚、第一裸露焊盘部分与第二裸露焊盘部分以及导线，其中裸片垫、第一裸露焊盘部分与第二裸露焊盘部分的底面未被模塑材料覆盖。
本发明提供一种引线框架，包含裸片垫、引脚、第一焊盘部分以及第二焊盘部分。在裸片垫上安装半导体裸片。引脚沿着裸片垫的四个外围边缘设置。第一焊盘部分设置在引脚与裸片垫之间，其中第一焊盘部分自裸片垫的外围边缘伸出。第二焊盘部分与第一焊盘部分分隔开，并且第二焊盘部分设置在第一焊盘部分与裸片垫之间。
上述引线框架及引线框架封装能够通过在引线框架及引线框架封装中，设置在引脚与裸片垫之间的第一焊盘部分与设置在第一焊盘部分与裸片垫之间并且与第一焊盘部分分隔开的第二焊盘部分，形成分开的接地系统，从而避免了噪声，并且减少信号损失。
附图说明
图1为引线框架封装的顶透视图。
图2为根据本发明一实施方式的引线框架封装的顶透视图。
图3为引线框架封装沿A-A方向的剖面示意图。
图4为根据本发明分离的焊盘部分与围绕分离的焊盘部分的缝隙沿B-B方向的放大剖面示意图。
图5为缝隙的变形例。
图6为缝隙的另一变形例。
图7为根据本发明的裸片垫以及裸片垫上的范例电感部分的示意图。
图8为根据本发明的包含多个裸露焊盘的引线框架封装的制造过程的示意图。
图9、图10、图11、图12与图13为根据本发明在使用二阶蚀刻法制造引线框架封装期间中间步骤的引线框架封装剖面示意图。
图14、图15、图16与图17为根据本发明另一实施方式具有图4所示反向T形缝隙的引线框架封装制造期间，中间步骤时引线框架封装的剖面示意图。
图18为Sip引线框架封装的顶视图。
图19为倒装芯片引线框架封装的平面透视图。
图20为倒装芯片引线框架封装的剖面示意图。
图21为根据本发明的引线框架封装的剖面示意图。
图22为根据本发明的引线框架的范例布局的示意图。
图23、图24与图25为图22所示的引线框架的部分放大顶透视图。
图26为连接垫、焊盘部分与导线的示意图。
图27为范例引线框架的堵住杆(dam bar)的示意图。
具体实施方式
后文所述的改进的引线框架封装结构所适用的应用范围包含，但不限定于：小外形四方扁平封装(Low profile Quad Flat Pack，以下简称为LQFP)封装、薄型四方扁平封装(Thin Quad Flat Pack，以下简称为TQFP)封装、四侧无引脚扁平(Quad Flat Non-leaded，以下简称为QFN)封装、双排扁平无引脚(Dual FlatNo-lead，以下简称为DFN)封装、多区域QFN以及多裸片倒装芯片(multi-dieflip-chip)封装。
本发明能够通过减少用于引线键合(wire bond)至接地垫(ground pad)、电源垫或者封装半导体裸片上一些信号垫的引脚的数目或者使上述引脚空闲以用于其它地方，来改进现有技术引线框架封装的效能。此外，本发明能够通过利用裸片垫上分开的接地系统来改进集成电路封装的电性效能。
图1为引线框架封装10的顶透视图(perspective top view)。如图1所示，引线框架封装10包含半导体裸片12，即安装在裸片垫14上的范例半导体装置。提供多个连接垫13在半导体裸片12的上表面。各连接垫13通过连接线18电性耦接至相应引脚16。
连接垫13也被称为输入/输出垫或者I/O垫。一般地，连接垫13包含电源垫13a、13b、13c、13d、13e与13f、接地垫13g与13h、以及信号垫等。电源垫13a～13f通过连接线18(即信号线)与各自的引脚16a、16b、16c、16d、16e、16f相连接。接地垫13g与13h通过连接线26与裸片垫14相连接。
引脚16沿着裸片垫14的四边设置。引脚16最后安装在PCB的插口(socket)上。半导体裸片12、裸片垫14、引脚16的内端(inner end)与连接线18封装在模塑材料(molding compound)20中。
本范例中，裸片垫14为单一的矩形平面区域，包含四个从裸片垫14的四角向外延伸的细支承杆(supporting bar)15。但是，请注意，其它形状的裸片垫，例如没有四个细支承杆的裸片垫，也可应用于本发明。裸片垫14的底面(图未示)特意裸露在封装体中，以驱散半导体裸片12所产生的热量，这也称为裸露裸片垫(Exposed die pad，以下简称为E-pad)配置结构。一般地，裸片垫14的裸露底面电性耦接至PCB的接地层。
一些系统芯片应用中，半导体裸片12包含模拟/数字混合电路，并且能够传输高频信号。然而，由于数字接地噪声会对模拟信号路径产生不利影响，这些系统芯片应用存在缺陷。
请参阅图2与图3。图2为根据本发明一实施方式的引线框架封装10a的顶透视图。图3为引线框架封装10a沿A-A方向的剖面示意图。本发明的附图中，相同的数字标号代表相似的组件、区域或者层。
如图2与图3所示，引线框架封装10a包含安装在裸片垫14之上的半导体裸片12。裸片垫14为铜或者铜合金，例如标号为C7025、A192的铜合金。相似的，提供多个连接垫13在半导体裸片12的上表面上。一些连接垫13通过连接线18电性耦接至相应引脚16。
连接垫13包含电源垫13a～13f、数字接地垫13g与13h、模拟接地垫13i与13j、与信号垫等。本发明一独特的特性在于：电源垫13a～13f通过较短的连接线28与分离的焊盘部分14a相连接，而非与引脚16a～16f相连接。由此，能够将原来与各自的电源垫13a～13f相连接的引脚16a～16f节省下来，用于其它用途，例如，耦接在半导体裸片12上的其它信号垫；或者仅省略引脚16a～16f以减少引脚数目，从而降低引线框架封装10a的大小与成本。
从一方面看，引线框架封装10a的效能可通过省略引脚16a～16f而得以提高，其中引脚16a～16f原来用于耦接半导体裸片12上的电源垫13a～13f。这是因为引脚间距得以增加，也因为芯片与PCB之间的信号传输路径变得更短。
本发明另一独特的特性在于：从裸片垫14分割的分离的焊盘部分(separatepad segment)14a未与裸片垫14直接接触，并且完全与裸片垫14隔离。此外，分离的焊盘部分14a未与任何引脚16直接接触，或者由任何引脚16支持。因此分离的焊盘部分14a未占用任何引脚16。相似于裸片垫14，分离的焊盘部分14a的底面也裸露在封装体中，以使得分离的焊盘部分14a能够电性耦接至PCB的电源层，电源层例如为双倍数据速率(Double Data Rate，以下简称为DDR)电源层，用以提供电源信号至半导体裸片12。
本发明又一特性在于：半导体裸片12上的数字接地垫13g与13h通过连接线26与裸片垫14相连接，并且半导体裸片12上的模拟接地垫13i与13j通过连接线36与分离的焊盘部分14b相连接。
根据本发明，裸片垫14耦接于数字接地信号，而分离的焊盘部分14b耦接于模拟接地信号。这种裸片垫上的分离接地系统能够防止数字电路噪声影响模拟信号路径。此外，模拟接地垫13i与13j接地，并且引线键合至分离的焊盘部分14b，意味着此实施方式的信号传输路径比通过引脚16的信号传输路径更短。
相似的，从裸片垫14分割的分离的焊盘部分14b未与裸片垫14直接接触，并且完全与裸片垫14隔离。
如图3所示，与分离的焊盘部分14a相似，分离的焊盘部分14b未与任何引脚16直接接触。更明确的说，分离的焊盘部分14b不需要任何来自引脚16或者裸片垫14的结构支持。分离的焊盘部分14a与裸片垫14之间的缝隙40a以及分离的焊盘部分14b与裸片垫14之间的缝隙40b都填充环氧树脂(epoxy)模塑材料20。
请注意，裸片垫14上的多个部分可分为三类，即主要部分、至少一次要部分、以及至少一分离部分。分离部分将主要部分与次要部分分离。图2中，分离的焊盘部分14a与14b为次要部分的范例。缝隙40a与40b用作分离部分，用以从裸片垫14的主要部分分离次要部分(例如分离的焊盘部分14a与14b)。
分离的焊盘部分14b的底面裸露在封装体中，以使得分离的焊盘部分14b能够电性耦接于PCB的模拟接地层。裸片垫14的裸露底面耦接于数字接地层。如前所述，这种裸片垫上的分离接地系统能够防止数字电路噪声影响模拟信号路径。
图4为根据本发明引线框架封装10a的分离的焊盘部分14b与围绕分离的焊盘部分14b的缝隙40b沿B-B方向的放大剖面示意图。如图4所示，电镀贵金属(plated noble metal)层52a(例如，贵金属为金、银、钯、铂、铱、铼、钌、锇、镍银、镍金或其组合物)设置在裸片垫14与分离的焊盘部分14b的模制上面(upper side)(裸片面)上。裸片垫14与分离的焊盘部分14b的裸露底面(PCB面)都涂有贵金属层52b。被动组件60可跨越缝隙40b，安装在裸片垫14与分离的焊盘部分14b之间，用于去耦、静电放电(electrostatic discharge)或者其它特定电路(例如过滤或匹配)的设计目的。
本发明另一特性在于：缝隙40b(或者缝隙40a)包含反向T形剖面。环氧树脂模塑材料20填充反向T形缝隙40b，由此改善引线框架主体的可靠度及变形程度。由于反向T形缝隙40b，注入的模塑材料20能够将悬浮的分离的焊盘部分14b牢固地保持在其位置上。
图5为缝隙40b(或者40a)的变形例。如图5所示，沙漏状缝隙40b包含位于模制的上面或者裸片面上的梯形的上面部分。图6为缝隙40b(或者40a)的另一变形例。如图6所示，分离的焊盘部分14b包含类似锯齿形边缘70。这提高了分离的焊盘部分14b与填充在缝隙40b中的模塑材料20之间的粘附程度。
图7为根据本发明的裸片垫14以及裸片垫14上的范例电感部分82与84的示意图。蜿蜒的电感部分82与螺旋状的电感部分84与引线框架的裸片垫形成一整体，其中蜿蜒的电感部分82与螺旋状的电感部分84能够用于形成垫上电感(on-pad inductor)。蜿蜒的电感部分82与螺旋状的电感部分84未与裸片垫14直接接触。更明确地说，电感部分82与84不需要任何来自引脚16或者裸片垫14的结构支持。
环氧树脂模塑材料被填充至蜿蜒的电感部分82与裸片垫14之间的缝隙82a内，并且被填充至螺旋状的电感部分84与裸片垫14之间的缝隙84a内。缝隙82a与84a可包含如图4所示的反向T形剖面。
因为电感部分82与84未与任何引脚16耦接，电感部分82与84的电感具有高的质量因子(quality Q factor)，减小的寄生电容以及较低的共振频率。
图8为根据本发明的包含多个裸露的焊盘的引线框架封装制造过程的流程示意图。从一方面，本发明的引线框架可利用二阶蚀刻法制造。也就是说，在第一阶段100期间，由引线框架制造组对裸片垫进行第一半蚀刻(firsthalf-etched)(如标号102所示的裸片垫上第一蚀刻的步骤)，也称为“初步蚀刻”。并且，在完成封装模制之后，第二阶段200期间，由后续装配车间对裸片垫进行第二半蚀刻(如标号202所示的第二蚀刻的步骤)，也称为“分离蚀刻”。如图8所示，除去步骤“背面打标”、“移除背面打标”以及“模制”之后的“蚀刻”之外，可以使用现有技术引线框架封装的装配程序。“背面打标”为将工艺图(artwork)或者光致抗蚀剂(photoresist)打印在底部金属的连接杆上，以达成防止电镀(plating resistant)的目的。在除去连接杆之外的封装被电镀锡或者贵金属之后，包含裸露引线框架的模制封装得到保护，并且能够防腐蚀。接着，移除连接杆底面的工艺图或者光致抗蚀剂。连接杆在光化学(photochemical)机器中被蚀刻掉，并且各裸露的焊盘是绝缘的。第二半蚀刻将分离的焊盘部分14a与14b从主裸片垫14上分割并且分隔开。或者，可利用钻孔机器或者PCB雕刻机来对连接杆进行钻孔或者雕刻。
请参阅图9、图10、图11、图12与图13，并且请同时参阅图8。图9-图13为根据本发明在使用二阶蚀刻法制造引线框架封装期间，中间步骤中引线框架封装剖面示意图。请注意，出于简洁的目的，图9-图13省略了一些组件或者层(layer)。如图9所示，蚀刻(或者压印)及电镀之后，得到引线框架300。引线框架300包含单一裸片垫314与外围引脚316。裸片垫314的两面皆涂有蚀刻膜322，例如贵金属、金属合金或者光致抗蚀剂。蚀刻膜322包含缝隙孔324。缝隙孔324设定待转变为基本裸片垫314的独立(isolated)焊盘式样350。
如图10所示，在芯片面上执行第一半蚀刻程序，以通过蚀刻膜322的缝隙孔来蚀刻预定厚度的裸片垫314。如前所述，第一半蚀刻程序能够在引线框架制造群组中完成。接着，运送半蚀刻后的引线框架300至装配车间。
如图11所示，装配车间中，将半导体裸片312粘附在裸片垫314上。提供连接线318与336，以形成连接垫313与引脚316之间的电性连接以及半导体裸片312上的连接垫313与裸片垫314之间的电性连接。
如图12所示，在引线键合之后，使用热固性复合材料(thermosettingcompound)320模制图11所示的全部装配组件。热固性复合性材料可为低温硬化树脂。随后，对模制封装进行固化工艺(curing process)。如特别指出的，模制封装的底面或者PCB面是裸露的。
如图13所示，模制之后，对模制封装的裸露PCB面进行第二半蚀刻程序，以通过蚀刻膜322的对应缝隙孔324来蚀刻剩余厚度的裸片垫314，由此形成自裸片垫314分割的分离的焊盘部分314a。分离的焊盘部分314a完全与裸片垫314隔离，并且未与裸片垫314直接接触。第二半蚀刻程序可由雕刻机器所执行的雕刻程序所替代，雕刻程序能够中PCB上的雕刻图样(carving pattern)上执行。
图14、图15、图16与图17为根据本发明另一实施方式的具有图4所示反向T形缝隙的引线框架封装的制造期间，中间步骤时引线框架封装的剖面示意图。如图14所示，蚀刻(或者压印)及电镀之后，得到引线框架300。引线框架300包含单一裸片垫314与外围引脚316。裸片垫314的两面都涂有蚀刻膜322。裸露的底面上，蚀刻膜322包含支撑杆(图未示)的式样以临时耦接在分离的焊盘部分314a与裸片垫314之间。蚀刻膜322可由贵金属、金属合金或者光致抗蚀剂制成。蚀刻膜322包含缝隙孔324。缝隙孔324设定待转变为基本裸片垫314的独立焊盘式样350。
随后，如图15所示，在裸片垫314的双面上都执行第一蚀刻程序(包含从裸片面开始的一半蚀刻程序以及从裸片垫314的底面开始的另外一半蚀刻程序)，以通过蚀刻膜322的缝隙孔来蚀刻掉全部厚度的裸片垫314，由此形成反向T形缝隙孔340与分离的焊盘部分314a。此阶段中，前述临时的支撑杆仍耦接在分离的焊盘部分314a与裸片垫314之间，以防止分离的焊盘部分314a从裸片垫314上掉落。第一蚀刻程序可以完成于引线框架制造组中。接着，引线框架300被传送至装配车间。
如图16所示，装配车间中，将半导体裸片312粘附在裸片垫314上。提供连接线318与336，以形成连接垫313与引脚316之间的电性连接以及半导体裸片312上的连接垫313与分离的焊盘部分314a之间的电性连接。
如图17所示，在引线键合之后，接着使用热固性复合材料320来模制图16所示的全部装配组件。热固性复合材料可为低温硬化树脂。随后，对模制封装进行加工程序。如特别指出的，模制封装的底面或者PCB面是裸露的。
根据本发明的另一实施方式，引线框架封装为多芯片模块(Multi-ChipModule，MCM)或者系统级封装(System-in-Package，以下简称为Sip)。系统级封装将多个半导体裸片与被动组件包含在单一封装中。图18为Sip引线框架封装的顶视图。如图18所示，Sip引线框架封装400包含安装在主要裸片垫414上的第一半导体裸片412。主要裸片垫414包含四个从主要裸片垫414的四角向外延伸的细支承杆415。主要裸片垫414的底面裸露在封装体中，以驱散第一半导体裸片412所产生的热量。主要裸片垫414的裸露底面可电性耦接至PCB的接地层。
第一半导体裸片412包含位于其上的多个连接垫413。连接垫413通过连接线418电性耦接各自的引脚416。Sip引线框架封装400更包含次要裸片垫514。第二半导体裸片512安装在次要裸片垫514上。次要裸片垫514从主要裸片垫414分割，并且未与主要裸片垫414直接接触。第二半导体裸片512上的一些连接垫513通过连接线518电性耦接各自的引脚416。根据本发明，第一半导体裸片412为数字芯片，并且第二半导体裸片512为模拟芯片。
相似的，次要裸片垫514的底面裸露在封装体中，以驱散第二半导体裸片512所产生的热量。次要裸片垫514的裸露底面可电性耦接至接地层(例如PCB的模拟接地)，此种设置能够防止数字电路噪声影响模拟信号路径。此外，提供多个分离的焊盘部分614于主要裸片垫414上，分离的焊盘部分614包含与图3至图6所示分离的焊盘部分14b相同的分隔垫结构。
分离的焊盘部分614的功能提供高速差分信号至第二半导体裸片512，以使得能够建立更短的电性路径以及达到更少信号损失的目的。分离的焊盘部分614与主要裸片垫414分离，并且不需要任何来自主要裸片垫414或者引脚416的结构支持。
可选择的，将被动组件560跨越缝隙540来安装于主要裸片垫414与次要裸片垫514上，缝隙540位于主要裸片垫414与次要裸片垫514之间。一些连接垫413通过连接线618引线键合至第二半导体裸片512上的各自的连接垫513。第二半导体裸片512上的一些连接垫513通过连接线718引线键合至分离的焊盘部分614。由模塑材料420封装或者模制全部装配组件。
图19与图20为根据本发明另一实施方式的倒装芯片(flip-chip)引线框架封装900的示意图。图19为倒装芯片引线框架封装900的平面图。图20为倒装芯片引线框架封装900的剖面示意图。如图19与图20所示，倒装芯片引线框架封装900包含裸片垫914。裸片垫914包含四个从裸片垫914的四角向外延伸的细支承杆(supporting bar)915。裸片垫914的底面裸露在封装体中。举例而言，裸片垫914的裸露底面电性耦接至PCB的数字接地层。在裸片垫914的另一面(即与裸片垫914的裸露底面相反的芯片面)上提供凸起块(bump)或者焊球(solderball)924，以在主要裸片垫与安装在芯片面上的倒装芯片912之间形成电性连接。
倒装芯片引线框架封装900更包含多个悬浮的焊盘部分(suspended padsegment)914a、914b、914c与914d，每一悬浮的焊盘部分耦接一特定信号。例如，悬浮的焊盘部分914a耦接于VDD1电源信号，悬浮的焊盘部分914b耦接于VDD2电源信号，悬浮的焊盘部分914c耦接于VDD3电源信号，并且悬浮的焊盘部分914d耦接于模拟接地信号。凸起块924a、924b、924c与924d设置在各悬浮的焊盘部分914a～914d上，以在悬浮的焊盘部分与倒装芯片912之间进行电性连接。
如前所述，悬浮的焊盘部分914a～914d是从裸片垫914分割，并且未与裸片垫914直接接触。更进一步地说，悬浮的焊盘部分914a～914d与多个引脚916的任一引脚相分离。缝隙940a、940b、940c、940d可包含图4所示的反向T形剖面。各悬浮的焊盘部分的底面914a～914d是裸露的。
引脚916沿着裸片垫914的四边设置。凸起块916a设置在各引脚916上，以在引脚916与倒装芯片912之间进行电性连接。除去倒装芯片912、裸片垫914、悬浮的焊盘部分914a～914d与引脚916的底面，倒装芯片912、裸片垫914、悬浮的焊盘部分914a～914d与引脚916封装在模塑材料920中。模塑材料920填充缝隙940a～940d，由此将悬浮的焊盘部分914a～914d牢固地保持在各自的位置上。
请参阅图21、图22、图23、图24与图25。图21为根据本发明的引线框架封装侧面的内部示意图。图22为根据本发明引线框架的范例布局(layout)的示意图。图23至图25为图22所示的引线框架的一侧的放大顶视图。如图21所示，引线框架封装200可为LQFP裸露焊盘封装(LQFP exposed pad package)。LQFP裸露焊盘封装包含单一裸片垫214，粘附在裸片垫214的半导体裸片212、多个沿着裸片垫214的四个外围边缘设置的引脚216、多个设置在裸片垫214与多个引脚216之间的裸露的焊盘部分(exposed pad segment)224、多条电性耦接并且延伸至半导体裸片212与各引脚216之间的导线218、多条电性耦接并且延伸至半导体裸片212与多个裸露的焊盘部分224之间的导线228、以及模塑材料220，模塑材料220至少部分封装裸片垫214、导线216、裸露的焊盘部分224、导线218与导线228。裸片垫214的底面与裸露的焊盘部分224的底面裸露在模塑材料220内。裸露的焊盘部分224可沿着裸片垫214的四个外围边缘的其中之一与内向引脚216延伸。裸露的焊盘部分224的跨距(span)取决于半导体裸片212上连接垫213的电特性。例如，半导体裸片212上的两个或者三个信号垫(例如数字电源垫)可引线键合于单一裸露的焊盘部分(例如图22所示的M2)，用以接收数字电源。
如图22所示，根据本发明，范例引线框架210包含单一裸片垫M1。裸片垫M1设置在引线框架210的中央开孔内。由四个支撑杆215支持的裸片垫M1包含方形配置，方形配置设定四个实质上长度相等的外围边缘。多个焊盘部分M2、M3、M4、M5、M6、M7、M8、M9、M10、M11、M12、M13、M14、M15、M16、M17、M18、M19、M20、M21、M22、M23、M24、M25、M26、M27、M28、M29、M30、M31、M32、M33、M34、M35、M36、M37、M38、M39、M40、M41、M42、M43、M44、M45、M46、M47、M48、M49、M50、M51、M52、M53延伸至裸片垫M1的四个外围边缘与内向引脚216之间。焊盘部分M2～M53可由耦接杆支持，例如耦接焊盘部分M2～M6与裸片垫M1的耦接杆C2、C3、C4、C5、C6。可选择地，焊盘部分可由如图27所示的堵住杆(dam bar)230所支持。在之后的装配或者封装阶段，可通过激光、锯、蚀刻、雕刻或者去纬/去胶(dejunk/trim)方法将耦接杆切掉，以使各焊盘部分相互间电性绝缘。
如图23所示，焊盘部分M2非常相似于开垦地(reclaimed land)，焊盘部分M2占据引脚216与裸片垫M1的四个外围边缘其中之一之间很大的开放区域。焊盘部分M2包含一个边缘233，边缘233符合由引脚216的内端所设定的形状。本发明的一特点在于：焊盘部分M2包围至少一个小区域的焊盘部分，例如M3与M4。焊盘部分M2大于被包围的焊盘部分M3或者M4，也就是说，焊盘部分M2的表面区域大于被包围的焊盘部分M3或者M4的表面区域。如图23所示，焊盘部分M3或者M4设置在焊盘M2与裸片垫M1之间。根据本发明，焊盘部分M2电性耦接于第一信号，并且被包围的焊盘部分电性耦接于第二信号，其中相比于第一信号，第二信号对噪声更敏感。根据本发明，相比于第二信号，第一信号具有更低的状态切换率。例如，第一信号可为DDR数字电源，而第二信号可为DDR参考电源(VREF)或者模拟电源。另一种状况下，第二信号可为控制信号或者差分信号。焊盘部分M2可包含Z字形侧面的边缘235，边缘235与相邻焊盘部分(例如焊盘部分M5与M6)的对应Z字形边缘相配合。
如图24所示，焊盘部分M11与M13共同包围敏感的焊盘部分M7。通过这种配置，电源或者接地的焊盘部分M11与M13保护敏感的焊盘部分M7，例如焊盘部分M7为模拟电源或者模拟接地信号时，为焊盘部分M7遮蔽噪声信号。相似的，图24中，受保护的敏感的焊盘部分包含焊盘部分M14、M19与M22。图25为多个设置在引脚与裸片垫M1之间的带状的焊盘部分M51～M53。受保护的敏感的焊盘部分包含焊盘部分M44～M47与M49，其中敏感焊盘部分M44～M47由焊盘部分M10与M12保护，并且敏感焊盘部分M49由焊盘部分M48与M50保护。如图25所示，焊盘M49设置在焊盘M50与裸片垫M1之间。图26为连接垫213、焊盘部分M30～M32与导线228的示意图。本发明一实施方式中，多个裸露的焊盘部分224包含大的表面区域，足够用于多于四条导线228的引线键合，并且电源/接地电感与热阻抗得到减小。
以上所述仅为本发明的较佳实施方式，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (19)

1.一种引线框架封装，包含：
裸片垫；
半导体裸片，粘附于该裸片垫；
多个引脚，沿着该裸片垫的四个外围边缘设置；
第一裸露焊盘部分，设置于该多个引脚与该裸片垫之间；
第二裸露焊盘部分，与该第一裸露焊盘部分分隔开，并且该第二裸露焊盘部分设置于该第一裸露焊盘部分与该裸片垫之间；
多条导线，分别电性耦接并且延长至该半导体裸片与各引脚之间、该半导体裸片与该第一裸露焊盘部分之间及该半导体裸片与该第二裸露焊盘部分之间；以及
模塑材料，至少部分封装该裸片垫、该多个引脚、该第一裸露焊盘部分、该第二裸露焊盘部分以及该多条导线，其中该裸片垫的底面、该第一裸露焊盘部分的底面与该第二裸露焊盘部分的底面未被该模塑材料覆盖。
2.如权利要求1所述的引线框架封装，其特征在于，该第一裸露焊盘部分包围并且保护该第二裸露焊盘部分。
3.如权利要求2所述的引线框架封装，其特征在于，该第一裸露焊盘部分电性耦接于第一信号，并且该第二裸露焊盘部分电性耦接于第二信号，其中该第二信号比该第一信号对噪声更敏感。
4.如权利要求3所述的引线框架封装，其特征在于，该第一信号比该第二信号具有较低的状态切换率。
5.如权利要求3所述的引线框架封装，其特征在于，该第二信号为模拟电源与模拟接地其中之一。
6.如权利要求3所述的引线框架封装，其特征在于，该第二信号为多个控制信号其中之一或者多个差分信号其中之一。
7.如权利要求1所述的引线框架封装，其特征在于，该第一裸露焊盘部分的表面区域大于该第二裸露焊盘部分的表面区域。
8.如权利要求1所述的引线框架封装，其特征在于，该第一裸露焊盘部分沿着该裸片垫的四个外围边缘之一延伸，并且该第一裸露焊盘部分的跨距取决于该半导体裸片上的连接垫的电特性。
9.如权利要求1所述的引线框架封装，其特征在于，该第一裸露焊盘部分的表面区域与该第二裸露焊盘部分的表面区域皆足够用于多于四条该导线的引线键合。
10.一种引线框架，包含：
裸片垫，用于在该裸片垫上安装半导体裸片；
多个引脚，沿着该裸片垫的四个外围边缘设置；
第一焊盘部分，设置于该多个引脚与该裸片垫之间，其中该第一焊盘部分从该裸片垫的该多个外围边缘其中之一伸出；以及
第二焊盘部分，与该第一焊盘部分分隔开，并且该第二焊盘部分设置在该第一焊盘部分与该裸片垫之间。
11.如权利要求10所述的引线框架，其特征在于，该多个外围边缘为直边，并且没有在该多个外围边缘的任一外围边缘上形成凹槽。
12.如权利要求10所述的引线框架，其特征在于，该第一焊盘部分用于耦接第一信号，并且该第二焊盘部分用于耦接第二信号，其中该第二信号比该第一信号对噪声更敏感。
13.如权利要求12所述的引线框架，其特征在于，该第一信号比该第二信号具有较低的状态切换率。
14.如权利要求12所述的引线框架，其特征在于，该第二信号为模拟电源与模拟接地其中之一。
15.如权利要求12所述的引线框架，其特征在于，该第二信号为多个控制信号其中之一或者多个差分信号其中之一。
16.如权利要求10所述的引线框架，其特征在于，该第一焊盘部分的表面区域大于该第二焊盘部分的表面区域。
17.如权利要求10所述的引线框架，其特征在于，该第一焊盘部分沿着该裸片垫的四个外围边缘之一延伸，并且该第一焊盘部分的跨距取决于该半导体裸片上的连接垫的电特性。
18.如权利要求10所述的引线框架，其特征在于，该第一焊盘部分的表面区域与该第二焊盘部分的表面区域皆足够用于至少四条该导线的引线键合。
19.如权利要求10所述的引线框架，其特征在于，该第一焊盘部分包围并且保护该第二焊盘部分。
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CN110190051A (zh) * 2019-05-29 2019-08-30 广州致远电子有限公司 混合信号微控制器、设备及制备方法
CN110190051B (zh) * 2019-05-29 2021-03-19 广州致远电子有限公司 混合信号微控制器、设备及制备方法

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