TWI573236B - 以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法 - Google Patents

以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法 Download PDF

Info

Publication number
TWI573236B
TWI573236B TW100133588A TW100133588A TWI573236B TW I573236 B TWI573236 B TW I573236B TW 100133588 A TW100133588 A TW 100133588A TW 100133588 A TW100133588 A TW 100133588A TW I573236 B TWI573236 B TW I573236B
Authority
TW
Taiwan
Prior art keywords
semiconductor die
semiconductor
die
encapsulant
conductive
Prior art date
Application number
TW100133588A
Other languages
English (en)
Other versions
TW201246483A (en
Inventor
具俊謨
潘迪Ｃ 瑪莉姆蘇
尹承昱
沈一權
Original Assignee
史達晶片有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 史達晶片有限公司 filed Critical 史達晶片有限公司
Publication of TW201246483A publication Critical patent/TW201246483A/zh
Application granted granted Critical
Publication of TWI573236B publication Critical patent/TWI573236B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2105—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H01L2224/221—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法
本發明一般有關於一種半導體元件，以及本發明更特別有關於一種以晶圓等級接合不同尺寸半導體晶粒之半導體元件及方法。
在現代電子產品中通常可以發現半導體元件。半導體元件之電性組件之數目與密度可以改變。離散半導體元件通常包含一種型式電性組件，例如：發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效應電晶體(MOSFET)。積體半導體元件典型地包括數百至數百萬電性組件。積體半導體元件之例包括：微控制器、微處理器、電荷耦合裝置(CCD)、太陽電池、以及數位微鏡裝置(DMD)。
半導體元件可以實施廣泛範圍功能，例如：信號處理、高速計算、發射與接收電磁信號、控制電子元件、將太陽光轉換成電力、以及產生用於電視顯示之視覺投影。在娛樂、通訊、電力轉換、網路、電腦、以及消費者產品領域中可以發現半導體元件。在軍事應用、航空、汽車、工業控制器、以及辦公室設備領域中亦可以發現半導體元件。
半導體元件使用半導體材料之電氣性質。半導體材料之原子結構允許藉由施加電場或基極電流、或透過掺雜過程，以操縱其導電性。掺雜將雜質導入於半導體材料中，以操縱且控制半導體元件之導電性。
半導體元件包括主動與被動電性結構。主動結構包括雙載子電晶體與場效應電晶體，以控制電流之流動。藉由改變掺雜位準與所施加電場或基極電流，電晶體可以增進或限制電流之流動。被動結構包括電阻器、電容器、以及電感器，產生電壓與電流間所須關係，以實施各種電性功能。將被動結構與主動結構電性連接以形成電路，其使得此半導體元件可以實施高速計算與其他有用功能。
通常使用兩個複雜製造過程、即前端製造過程與後端製造過程、其各可能涉及數百個步驟，以製造半導體元件。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒。各半導體晶粒典型地等同，且包含藉由將主動組件與被動組件電性連接所形成之電路。後端製造過程涉及將製成晶圓單粒化成個別半導體晶粒，且將晶粒封裝以提供結構支撐與環境隔離。在此使用此專用語「半導體晶粒」以指其單數與複數形式，且因此可以指單粒半導體元件與多個半導體元件。
半導體製造之目的為產生較小半導體元件。較小元件典型地消耗較少功率、具有較高性能表現、且可以更有效率地製成。此外，較小半導體元件典型地具有較小佔用面積，此對於較小終端產品為令人所欲。較小半導體晶粒尺寸可以藉由前端製造過程之改善而達成，以產生具有較小尺寸較高密度主動與被動組件之半導體晶粒。後端製造過程可以產生半導體元件封裝，其藉由改善電性互連與封裝材料而具有較小佔用面積。
圖1顯示傳統半導體封裝10，其具有以凸塊16安裝至基板14之半導體晶粒12。形成複數個導電通孔18以通過半導體晶粒12。將半導體晶粒20安裝至具有凸塊22之半導體晶粒12。將包封物24沉積在半導體晶粒12與20以及基板14上。將複數個凸塊26形成於在半導體晶粒12與20對面之基板14之表面上。
半導體晶粒12可以為邏輯元件，且半導體晶粒20可以為大儲存記憶體元件。因此，半導體晶粒20典型地大於半導體晶粒12。不同尺寸半導體晶粒使得晶圓等級接合困難。將半導體晶粒20接合至個別半導體晶粒12會增加製造成本，且會造成由於處理所產生之裂開缺陷。
目前須要以晶圓等級接合不同尺寸半導體晶粒。因此，在一實施例中，本發明為一種半導體元件製造方法，其包括以下步驟：提供一半導體晶圓，其具有相對之第一表面與第二表面；形成複數個導電通孔以部份地通過此半導體晶圓之第一表面，；將此半導體晶圓單粒化成複數個第一半導體晶粒；提供一載體，將此第一半導體晶粒安裝至此載體，將第二半導體晶粒安裝至第一半導體晶粒；將包封物沉積在第一與第二半導體晶粒及載體上；將載體與第二表面之一部份去除，以曝露導電通孔：以及在第二半導體晶粒對面之第一半導體晶粒之表面上形成互連結構。
在另一實施例中，本發明為一種半導體元件製造方法，其包括以下步驟：提供複數個第一半導體晶粒，形成複數個導電通孔以通過第一半導體晶粒；提供一載體，將此第一半導體晶粒安裝至此載體，將第二半導體晶粒安裝至第一半導體晶粒；以及將包封物沉積在第一與第二半導體晶粒以及載體上。第二半導體晶粒之占用面積大於第一半導體晶粒之占用面積。
在另一實施例中，本發明為一種半導體元件製造方法，其包括以下步驟：提供複數個第一半導體晶粒，形成複數個導電通孔以通過第一半導體晶粒；提供一載體，將此第一半導體晶粒安裝至此載體；將第一包封物沉積在第一與第一半導體晶粒與載體上；將載體去除；將第二半導體晶粒安裝至第一半導體晶粒；以及將第二包封物沉積在第二半導體晶粒與載體上。
在另一實施例中，本發明為一種半導體元件，其包括：第一半導體晶粒，其具有通過此第一半導體晶粒所形成之複數個導電通孔。將第二半導體晶粒安裝至第一半導體晶粒。第二半導體晶粒之占用面積大於第一半導體晶粒之占用面積。將包封物沉積在第一與第二半導體晶粒上。在第二半導體晶粒對面之第一半導體晶粒上形成互連結構。
在以下說明中參考所附圖式，以說明本發明之一或更多個實施例，其中相同數字代表相同或類似元件。雖然，本發明是以用於達成本發明目的之最佳模式說明，熟習此技術人士瞭解，其用意為包括符合本發明精神與範圍之替代、修正、以及等同物，而本發明精神與範圍是由以下內容與圖式所支撐之所附申請專利範圍與其等同物所界定。
通常使用兩個複雜製造過程以製造半導體元件：前端製造過程與後端製造過程。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒。在晶圓上各晶粒包含主動與被動電性組件，將其電性連接以形成功能性電路。主動式電性組件例如電晶體與二極體，具有能力以控制電流之流動。被動式電性組件例如電容器、電感器、電阻器、以及變壓器，在需要實施電路功能之電壓與電流之間建立關係。
此等主動與被動組件藉由一系列過程步驟形成於半導體晶圓之表面上，此等步驟包括：掺雜、沉積、微影術、蝕刻、以及平坦化。掺雜藉由像是離子植入與熱擴散之技術，將雜質導入於半導體材料中。此掺雜過程可以修正在主動元件中半導體材料之導電性，將半導體材料轉換成絕緣體、導體、或動態地改變半導體材料之導電性，以響應於電場或基極電流。電晶體包括改變型式之區域，且如同所須配置其掺雜程度，以使得當施加電場或基極電流時，可以增強或限制電流之流動。
主動與被動組件以具有不同電氣性質之材料層所形成。此等層可以藉由各種沉積技術形成，而此技術部份取決於所沉積材料之型式。例如，薄膜沉積可以涉及：化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解質電鍍、以及無電極電鍍過程。通常將各層圖案化，以形成主動組件、被動組件、以及組件之間電性連接之部份。
使用微影術將此等層圖案化，此涉及在將被圖案化之層上沉積光敏材料例如光阻。使用光線將圖案由光罩移轉至光阻。在一實施例中，使用溶劑將光阻圖案受光照射之部份去除，以曝露被圖案化下層之部份。在另一實施例中，使用溶劑將光阻圖案未受光照射之部份、即負光阻去除，以曝露被圖案化下層之部份。將光阻之其餘部份去除，而留下圖案化層。以替代方式，可以使用例如無電極與電解質電鍍技術，直接將材料沉積於由先前沉積/蝕刻過程所形成之區域或洞孔中，將某些形式材料圖案化。
將薄膜材料沉積於現有圖案上，可以擴大其下之圖案且產生不均勻平坦表面。須要均勻平坦表面以製成較小且更緊密封裝主動與被動組件。可以使用平坦化從晶圓表面去除材料，以產生均勻平坦表面。平坦化涉及以拋光墊將晶圓表面拋光。在拋光期間，將研磨與腐蝕化學劑添加至晶圓表面。此化學劑之研磨與腐蝕作用之組合機械作用可以移除任何不規則地形，以產生均勻平坦表面。
後端製造過程涉及將所製成晶圓切割或單粒化成個別晶粒，且然後將晶粒封裝用於結構支撐與環境隔離。為了將半導體晶粒單粒化，沿著稱為鋸道或劃線之晶圓非功能性區域，將晶圓劃線與斷開。使用雷射切割工具或鋸刀將晶圓單粒化。在單粒化之後，將個別半導體晶粒安裝至封裝基板，此基板包括用於與其他系統組件互連之接腳與接觸墊。在半導體晶粒上形成接觸墊，然後將其連接至封裝內之接觸墊。此電性連接可以焊料凸塊、柱(stud)凸塊、導電漿、或接線製成。將包封物或其他模製材料沉積在封裝上，以提供實體支撐與電性隔離。然後，將所完成封裝插入於電性系統中，且此半導體元件之功能可供其他系統組件使用。
圖2說明電子裝置50，其具有晶片載體基板或印刷電路板(PCB)52，在其表面上安裝複數個半導體封裝。取決於其應用，此電子裝置50可以具有一種型式半導體封裝、或多種型式半導體封裝。為了說明目的，在圖2中顯示不同型式半導體封裝。
電子裝置50可以為一種獨立設置式系統，其使用半導體封裝以實施一或更多個電性功能。以替代方式，電子裝置50可以為一較大系統之次組件。
例如，電子裝置50可以為行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)或其他電子通訊裝置之一部份。以替代方式，電子裝置50可以為可插入於電腦中之圖形卡、網路介面卡、或其他信號處理卡。此半導體封裝可以包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散裝置、或其他半導體晶粒或電性組件。對於這些製品微型化與減輕重量為重要，因為如此才可被市場接受。必須縮短此等半導體元件間之距離，以達成較高密度。
在圖2中，PCB 52提供一種一般性基板，用於安裝在PCB上半導體封裝之結構支撐與電性互連。使用蒸鍍、電解質電鍍、無電極電鍍、網版印刷、或其他合適金屬沉積過程，在PCB之表面上或層中形成導電信號跡線54。信號跡線54提供各此等半導體封裝、所安裝組件、以及其他外部系統組件間之電性通訊。跡線54亦提供至各此等半導體封裝之電力與接地連接。
在一些實施例中，半導體元件具有兩種封裝等級。第一等級封裝為一種技術，用於將半導體晶粒機械地與電性地裝附於一中間載體。第二等級封裝涉及將此中間載體機械地與電性地裝附於PCB。在其他實施例中，半導體元件可能僅具有第一等級封裝，將此晶粒機械地與電性地直接裝附於PCB。
為了說明目的而顯示，在PCB 52上數種型式第一等級封裝，此包括接線封裝56與覆晶58。此外，亦顯示在PCB 52上所安裝數種型式第一等級封裝，此包括：球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙內線封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四平非導線封裝(QFN)70、以及四平封裝72。取決於系統需求，可以將半導體封裝之任何組合、以第一與第二等級封裝型式之任何組合組態，而與其他電子組件互連至PCB 52。在一些實施例中，電子裝置50包括單一裝附半導體封裝，而其他實施例須要多個互連封裝。藉由將一或更多個半導體封裝組合在單一基板上，製造商可以將預製組件包括於電子裝置與系統中。因為半導體封裝包括精密複雜功能，可以使用較便宜組件與合理製造過程以製造電子裝置。此所製成裝置較不容易故障，且製造較便宜，以便可以對消費者提供低成本產品。
圖3a至3c顯示典範半導體封裝。圖3a說明安裝在PCB 52上DIP 64進一步細節。半導體晶粒74包括：作用區域，其包含類比或數位電路執行作為主動元件、被動元件、導電層、及形成於晶粒中之介電層，且根據晶粒之電性設計電性互連。例如，此電路可以包括：一或更多電晶體、二極體、電感器、電容器、電阻器、以及形成於半導體晶粒74之作用區域中之其他電路元件。接觸墊76為一或更多層之導電材料，例如：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)，且電性互連至半導體晶粒74中所形成之電路元件。在DIP 64之組裝期間，使用金-矽共晶層或黏著材料，例如熱環氧樹脂或環氧樹脂，將半導體晶粒74安裝至中間載體78。此封裝體包括一絕緣封裝材料，例如聚合物或陶瓷。導線80與接線82提供介於半導體晶粒74與PCB 52間之電性互連。包封物84沉積在封裝上，其藉由防止濕氣與粒子進入封裝且污染半導體晶粒74或接線82，而達成環境保護。
圖3b說明安裝在PCB 52上BCC 62之進一步細節。使用填料或環氧樹酯黏著材料92將半導體晶粒88安裝於載體90上。接線94提供在接觸墊96與98間之第一等級封裝互連。將模製複合物或包封物100沉積在半導體晶粒88與接線94上，以提供用於此元件之實體支撐與電性隔離。使用適當金屬沉積過程，例如電解質電鍍或無電極電鍍，將接觸墊102形成於PCB 52之表面上，以防止氧化。接觸墊102電性互連至在PCB 52中一或更多個導電信號跡線54。在BCC 62之接觸墊98與PCB 52之接觸墊102間形成凸塊104。
在圖3c中以覆晶式第一等級封裝將半導體晶粒58面向下安裝於中間載體106上。半導體晶粒58之作用區域108包括：類比或數位電路執行作為主動元件、被動元件、導電層、及根據晶粒之電性設計所形成之介電層。例如，此電路可以包括：一或更多電晶體、二極體、電感器、電容器、電阻器、以及在作用區域108中之其他電路元件。半導體晶粒58通過凸塊110電性地且機械地互連至載體106。
以BGA式第二等級封裝使用凸塊112，將BGA 60電性地且機械地互連至PCB 52。將半導體晶粒58電性互連至在PCB 52中之導電信號跡線54以通過凸塊110、信號線114、以及凸塊112。將模製複合物或包封物116沉積在半導體晶粒58與載體106上，以提供用於此元件之實體支撐與電性隔離。此覆晶半導體元件提供從半導體晶粒58上主動元件至PCB 52上導電跡線之短的導電路徑，以縮短信號傳送距離、降低電容、以及改善電路整體性能表現。在另一實施例中，可以使用覆晶式第一等級封裝將半導體晶粒58機械地且電性地直接互連至PCB 52，而無須中間載體106。
圖4a顯示半導體晶粒120，其具有基本基板材料122，例如：矽、鍺、鎵、砷、磷化銦、或碳化矽，而用於結構支撐。於晶圓120上形成複數個半導體晶粒或組件124，其藉由晶粒間之晶圓區域或鋸道126分開，如同以上說明。鋸道126提供切割區域，將半導體晶圓120單粒化成個別半導體晶粒124。
圖4b顯示半導體晶圓120之一部份之橫截面圖。各半導體晶粒124具有：後表面128，作用表面130、其包含類比或數位電路以執行主動元件、被動元件、導電層、及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括：一或更多電晶體、二極體、以及形成於作用表面130中之其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、ASIC、記憶體、或其他數位處理電路。半導體晶粒124亦可以包含積體被動元件(IPD)，例如：電感器、電容器、電阻器，用於射頻(RF)信號處理。在一實施例中，半導體晶粒124為覆晶式半導體晶粒。
使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解質電鍍、以及無電極電鍍過程、或其他合適金屬沉積過程，在作用表面130上形成導電層132。導電層132可以為一或更多層之鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他合適導電材料。導電層132可以操作為接觸墊，其電性互連至在作用表面130上之電路。此等接觸墊132可以側靠側地設置而距半導體晶粒124邊緣第一距離，如同於圖4b中顯示。以替代方式，此等接觸墊132可以在多個列中偏移，以致於將第一列接觸墊設置距此晶粒邊緣第一距離，且第二列接觸墊與第一列接觸墊交替設置，而距此晶粒邊緣第二距離。
在圖4c中，使用鋸刀或雷射切割工具134，透過鋸道126將半導體晶圓120單粒化成個別半導體晶粒124。
圖5a至5p說明有關於圖2、圖3a至3c以晶圓等級將不同尺寸半導體晶粒接合之過程。圖5a顯示半導體晶圓或基板140，其包含基本材料例如：矽、鍺、砷化鎵、磷化銦、或碳化矽，而用於結構支撐。於晶圓140上形成複數個半導體晶粒或組件142，其藉由晶粒間之晶圓區域或鋸道143分開，如同以上說明。鋸道143提供切割區域，將半導體晶圓140單粒化成個別半導體晶粒142。
各半導體晶粒142具有：後表面145，作用表面144、其包含類比或數位電路執行作為主動元件、被動元件、導電層、以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括：一或更多電晶體、二極體、以及形成於作用表面144中之其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、ASIC、記憶體、或其他數位處理電路。半導體晶粒142亦可以包含積體被動元件(IPD)，例如：電感器、電容器、電阻器，用於射頻(RF)信號處理。
在圖5b中，使用機械鑽孔、雷射鑽孔、或深離子反應性蝕刻(DRIE)形成複數個盲通孔146以部份地通過基板140。通孔146從作用表面144部份地但並未完全地延伸通過基板140。在一實施例中，通孔146係被切割到基板140厚度之60%。在隨後之製造過程期間，在通孔146與後表面145間之基板140之其餘部份提供用於基板之結構支撐。
在圖5c中，使用電解質電鍍、無電極電鍍過程、或其他適當金屬沉積過程將通孔146填以鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈦(Ti)、鎢(W)、多晶矽、或其他適當導電材料，以形成z方向中通過矽之導電直通矽晶通孔(TSV)148。
在圖5d中，使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解質電鍍、無電極電鍍過程、或其他適當金屬沉積過程，在基板140之作用表面144上形成導電層150。導電層150可以為一或更多層之銀(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他適當導電材料。導電層150操作為接觸墊或下凸塊金屬化(UBM)層，用於電性互連。導電層150亦包括重新分配層(RDL)與z-方向導電通孔，用於將電氣信號水平地與垂直地傳送。導電層150之一部份電性互連至導電通孔148。取決於半導體晶粒124與142之設計與功能，導電層150之其他部份可以電性共用或電性隔離。
使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴霧塗佈、燒結、或熱氧化，在基板140之作用表面144上或導電層150之周圍形成絕緣層或鈍化層152。此絕緣層152包括一或更多層之二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、以及具有類似絕緣與結構性質之其他材料。藉由蝕刻過程去除絕緣層152之一部份，透過一光阻層(未圖示)以曝露導電層152。以替代方式，可以在導電層150之前形成絕緣層152。
在圖5e中，使用蒸鍍、電解質電鍍、無電極電鍍過程、球滴、或網版印刷過程，在導電層150被曝露之一部份上沉積導電凸塊材料。此凸塊材料可以為銀(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、或焊料、以及上述之組合，而具有選擇性通量溶液。例如，此凸塊材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。使用適當裝附或接合過程，將凸塊材料接合至導電層150。在一實施例中，藉由將材料加熱至其熔點以上使凸塊材料回流以形成球或凸塊154。在一些應用中，將凸塊154第二次回流，以改善至導電層150之電性接觸，可以將凸塊154壓縮接合至導電層150。凸塊154代表形成於導電層150上之互連結構之一類型。此互連結構亦可使用柱凸塊、微凸塊、或其他電性互連。
在圖5f中，以鋸刀或雷射切割工具158透過鋸道143，將TSV基板140單粒化成個別TSV半導體晶粒142。在一實施例中，TSV半導體晶粒142包含一邏輯電路。
在圖5g中，一暫時基板或載體162包含犧牲基礎材料，例如：矽、聚合物、氧化鈹、或其他用於結構支撐之合適低成本的堅硬材料。將介面層或雙面帶164形成於載體162上，作為暫時黏著接合薄膜或蝕刻停止層。使用擷取與設置操作，將TSV半導體晶粒142設置且安裝至介面層164與載體162上，而以凸塊154背向載體。將TSV半導體晶粒142安裝至載體162，以構成一重新組態晶圓168，如同於圖5h中所示。
在圖5i中，使用擷取與設置操作，將來自圖4a-4c之半導體晶粒124安裝至TSV半導體晶粒142，而以作用表面130面向TSV半導體晶粒。以低於220℃之低溫使凸塊154回流，將TSV半導體晶粒142之導電層150電性連接至半導體晶粒124之導電層132。圖5j顯示，以重新建構晶圓等級，將半導體晶粒124冶金地與電性地連接至TSV半導體晶粒142。半導體晶粒124可以為記憶體元件，其具有大儲存容量；而TSV半導體晶粒142包含邏輯電路，其與記憶體元件相互作用。半導體晶粒124藉由其大儲存容量記憶體元件之性質，具有較此包含邏輯電路之TSV半導體晶粒142更大佔用面積。在一實施例中，在記憶體應用中，半導體晶粒124具有10mm x 10mm之佔用面積；而在行動CPU、GPU、以及基帶信號處理應用中，TSV半導體晶粒142具有8mm x 8mm之佔用面積。
將TSV半導體晶粒142設置在載體162上，此載體具有足夠空間以允許安裝半導體晶粒124，而具有在半導體晶粒間之開放區域，用於沉積包封物一直下至載體162與介面層164。將選擇性填充材料166沉積在凸塊154周圍的半導體晶粒124與TSV半導體晶粒142之間。
在圖5k中，使用漿印刷、壓擠模製、移轉模製、液體包封模製、真空堆疊、旋轉塗佈、或其他合適塗佈器，以重新建構晶圓等級，將包封物或模製複合物170沉積在半導體晶粒124、TSV半導體晶粒142、以及載體162之上與周圍。如果沒有填充材料166，可以將包封物170沉積在半導體晶粒124與TSV半導體晶粒142之間。包封物170可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹酯丙烯酸酯(acrylate)、或具有適當填料之聚合物。包封物170並不導電，且環境地保護半導體元件，防止受到外部元件與污染物之損害。
在另一實施例中，以重新建構晶圓等級，以一MUF過程，將模製填充(MUF)材料172沉積在半導體晶粒124與TSV半導體晶粒142之上與周圍，如同於圖51中所示。此追蹤模型174具有一上模型支撐176與一下模型支撐178，其在一起以開放空間180圍繞半導體晶粒124與TSV半導體晶粒142。一噴嘴182將液體狀態之MUF材料172注入於此追蹤模型174之一側；同時選擇性真空輔助器184，應用來自相對側之壓力，以MUF材料均勻地填入於半導體晶粒124與TSV半導體晶粒142周圍之開放空間180。MUF材料172可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸酯、或具有適當填料之聚合物。MUF材料172形成於半導體晶粒124與TSV半導體晶粒142之間與周圍且被固化，如同於圖5m中所示。
繼續圖5k之說明，藉由化學蝕刻、機械剝離、化學機械拋光(CMP)、機械研磨、熱烤、紫外線照射、雷射掃瞄、或濕性剝離，去除載體162與介面層164，以曝露半導體晶粒142之後表面145，如同於圖5n中所示。藉由研磨器190將基板140之基礎材料之一部份、以及包封物170或MUF材料172去除，以曝露導電通孔148。
圖5o顯示在研磨操作後，由包封物170或MUF材料172所覆蓋之半導體晶粒124與TSV半導體晶粒142。在半導體晶粒124對面之TSV半導體晶粒142表面上形成一積層(build-up)互連結構194。此積層互連結構194包括：使用圖案化與金屬沉積過程例如：濺鍍、電解質電鍍、無電極電鍍所形成之導電層或RDL 196。導電層196可以為一或更多層之銀(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他適當導電材料。導電層196包括，用於電性互連之水平部份與垂直部份。導電層196之一部份電性連接至導電通孔148。取決於半導體124或142之設計與功能，導電層196之其他部份可以為電性共用或電性隔離。
使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴霧塗佈、燒結、或熱氧化，在導電層196之周圍與之間形成絕緣或鈍化層198，用於電性電性隔離。絕緣層198包括：一或更多層之二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、或具有類似絕緣與結構性質之其他材料。藉由蝕刻過程去除絕緣層198之一部份，透過光阻層以曝露用於凸塊形成或額外封裝互連之導電層196。
藉由導電層150、凸塊154、以及導電通孔148，將此積層互連結構194電性互連至半導體晶粒124。
在圖5p中，使用蒸鍍、電解質電鍍、無電極電鍍過程、球滴、或網版印刷過程，在積層互連結構194之被曝露導電層196上沉積導電凸塊材料。此凸塊材料可以為銀(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、或焊料、以及上述之組合，而具有選擇性通量溶液。例如，此凸塊材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。使用適當裝附或接合過程將凸塊材料接合至導電層196。在一實施例中，藉由將材料加熱至其熔點以上使凸塊材料回流以形成球或凸塊200。在一些應用中，將凸塊200第二次回流，以改善至導電層196之電性接觸。可以在凸塊200下形成一UBM層，亦可以將凸塊200壓縮接合至導電層196。凸塊200代表形成於導電層196上之一種形式互連結構。此互連結構亦可使用柱凸塊、微凸塊、或其他電性互連。
可以經過包封物170與積層互連結構194，以鋸刀或雷射切割工具202將半導體晶粒124單粒化成個別散開式晶圓等級晶片尺寸封裝(FO-WLCSP)或內嵌式晶圓等級球狀柵格陣列(eWLB)204。圖6顯示在單粒化後之FO-WLCSP 204。半導體晶粒124可以大於TSV半導體晶粒142，特別是在以下情形中：此半導體晶粒為一記憶體元件，其具有大儲存容量且用於例如32-40nm之高節點技術。藉由以足夠空間形成重新結構晶圓、且將TSV半導體晶粒142安裝至載體162，可以此重新建構晶圓等級，將此較大半導體晶粒124接合至TSV半導體晶粒，而具有開放區域，用於在半導體晶粒與TSV半導體晶粒之間沉積包封物170或MUF材料172。亦可以此重新建構晶圓等級形成此積層互連結構194。此具有包封物170之重新建構晶圓保護半導體晶粒124，且提供支撐，用於形成此積層互連結構194。此重新建構晶圓等級包封物與形成互連結構，亦可以減輕處理損害與破裂之風險，以及提供一簡單且低成本製造過程。TSV半導體晶粒142之後背研磨可以曝露用於垂直互連之導電通孔148，且減少FO-WLCSP 204之厚度。
半導體晶粒124通過凸塊154、導電層150、以及導電通孔148電性連接至此積層互連結構194。此具有導電通孔148、導電層150、絕緣層152、以及凸塊154之TSV半導體晶粒142提供：用於半導體晶粒124垂直互連之簡單且成本效益的結構，以及通過TSV半導體晶粒之導電層與積層互連結構194之有效封裝堆疊。由於TSV半導體晶粒142可以與半導體晶粒124類似材料製成，且此積層互連結構194形成於半導體晶粒124與包封物170對面之TSV半導體晶粒142之表面上，TSV半導體晶粒142可以將半導體晶粒與積層互連結構間之CTE匹配不良抵消。TSV半導體晶粒142操作為：在TSV半導體晶粒之一側上之半導體晶粒124、與在TSV半導體晶粒之對面側上積層互連結構194之間之緩衝器，以減少翹曲(warpage)。TSV半導體晶粒142提供用於半導體晶粒124之精細間距垂直互連，而適用於高輸入/輸出(I/O)計數應用。
圖7a-7q說明有關於圖2以及圖3a-3c之另一個過程，以晶圓等級接合不同尺寸半導體晶粒。圖7a顯示半導體晶圓或基板210，其包括用於結構支撐之基礎材料，例如：矽、鍺、砷化鎵、磷化銦、或碳化矽。如同以上說明，將形成於晶圓210上複數個半導體晶粒或組件212，藉由晶粒間晶圓區域或鋸道213分開。鋸道213提供切割區域，將半導體晶圓210單粒化成個別半導體晶粒212。
各半導體晶粒212具有後表面215與作用表面214，其包括：類比或數位電路以執行作為主動元件與被動元件、導電層、以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括一或更多個電晶體、二極體、以及形成於作用表面214中其他電路元件，以執行類比電路或數位電路，例如：DSP、ASIC、記憶體、或其他信號處理電路。半導體晶粒212亦可以包括IPD，例如：電感器、電容器、以及電阻器，用於射頻(RF)信號處理。
在圖7b中，使用機械鑽孔、雷射鑽孔、或DRIE，形成複數個盲通孔216以部份地通過基板210。通孔216從表面212部份地但並未完全地延伸通過基板210。
在一實施例中，通孔216係被切割到基板210厚度之60%，在隨後製造過程期間，在通孔216與後表面215之間基板210之剩餘部份提供用於基板之結構支撐。
在圖7c中，使用電解質電鍍、無電極電鍍過程、或其他合適金屬沉積過程，以鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈦(Ti)、鎢(W)、或其他合適導電材料填入通孔216，以形成z-方向之導電TSV218。
在圖7d中，以鋸刀或雷射切割工具219，透過鋸道213將TSV基板210單粒化成個別TSV半導體晶粒212。在一實施例中，此TSV半導體晶粒212包括一邏輯電路。
在圖7e中，此暫時基板或載體222包括犧牲基礎材料，例如：矽、聚合物、氧化鈹、或其他合適低成本的堅硬材料用於結構支撐。將介面層或雙面帶224形成於載體222上，作為暫時黏著接合薄膜或蝕刻停止層。使用擷取與設置操作，將半導體晶粒212設置且安裝至介面層224與載體222上，而以後表面215朝向載體。將TSV半導體晶粒212安裝至載體162，以構成一重新組態晶圓226，如同於圖7f中所示。
在圖7g中，使用漿印刷、壓擠模製、移轉模製、液體包封模製、真空堆疊、旋轉塗佈、或其他合適塗佈器，以重新建構晶圓等級，將包封物或模製複合物228沉積在TSV半導體晶粒212與載體222上。包封物228可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸酯、或具有適當填料之聚合物。包封物228並不導電，且環境地保護半導體元件，防止受到外部元件與污染物之傷害。
在圖7h中，藉由化學蝕刻、機械剝離、化學機械拋光(CMP)、機械研磨、熱烤、紫外線照射、雷射掃瞄、或濕性剝離，將載體222與介面層224去除，以曝露基板210之後表面215。藉由研磨器229將基板210之基礎材料之一部份與包封物228去除，以曝露導電通孔218。
在圖7i中，使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解質電鍍、以及無電極電鍍過程、或其他合適金屬沉積過程，在TSV半導體晶粒212之表面227上形成導電層230。導電層230可以為一或更多層之鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他合適導電材料。導電層230可以操作為用於電性互連之接觸墊或UBM層。導電層230亦包括重新分配層與z-方向導電通孔，用於水平地與垂直地傳送電氣信號。導電層230之一部份電性連接至導電通孔218。取決於半導體晶粒124與212之設計與功能，導電層230之其他部份可以電性共用或電性隔離。
使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴霧塗佈、燒結、或熱氧化，在TSV半導體晶粒212之表面227上與導電層230周圍，形成絕緣或鈍化層232。此絕緣層232包括一或更多層之二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、或具有類似絕緣與結構性質之其他材料。藉由蝕刻過程去除絕緣層232之一部份，透過一光阻層以曝露導電層230。以替代方式，可以在導電層230形成之前形成絕緣層232。
在圖7j中，使用擷取與設置操作，將來自圖4a-4c之半導體晶粒124、在此情形中具有凸塊234，安裝至TSV半導體晶粒212，而以作用表面130朝向TSV半導體晶粒。以低於220℃之溫度使凸塊234回流，將導電層230電性互連至半導體晶粒124之導電層132。圖7k顯示，以重新建構晶圓等級，將半導體晶粒124冶金地與電性地互連至TSV半導體晶粒212。半導體晶粒124可以為記憶體元件，其具有大儲存容量；而TSV半導體晶粒212包含邏輯電路，其與記憶體元件交互作用。半導體晶粒124藉由其大儲存容量記憶體元件之性質，具有較此包含邏輯電路之TSV半導體晶粒212更大佔用面積。在一實施例中，在記憶體應用中，半導體晶粒124具有10mm x 10mm之佔用面積；而在行動CPU、GPU、以及基帶信號處理應用中，TSV半導體晶粒212具有8mm x 8mm之佔用面積。設置TSV半導體晶粒212，以具有足夠空間以允許安裝半導體晶粒124，而具有在半導體晶粒間之開放區域，用於沉積包封物一直下至導電層230與絕緣層232。將選擇性填充材料236沉積在凸塊234周圍的半導體晶粒124與TSV半導體晶粒212之間。
在圖71中，使用漿印刷、壓擠模製、移轉模製、液體包封模製、真空堆疊、旋轉塗佈、或其他合適塗佈器，以重新建構晶圓等級將包封物或模製複合物240沉積在半導體晶粒124與TSV半導體晶粒212上與周圍。如果沒有填充材料236，可以將包封物240沉積在半導體晶粒124與TSV半導體晶粒212之間。包封物240可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸酯、或具有適當填料之聚合物。包封物240並不導電，且環境地保護半導體元件，防止受到外部元件與污染物之損害。
在另一實施例中，以晶圓等級且以一MUF過程，將模製填充材料(MUF)242沉積在半導體晶粒124與TSV半導體晶粒212之上與周圍，如同於圖7m中所示。此追蹤模型244具有一上模型支撐246與一下模型支撐248，其在一起以開放空間250圍繞半導體晶粒124與TSV半導體晶粒212。以噴嘴252將液體狀態之MUF材料242注入於此追蹤模型244之一側中；同時選擇性真空輔助器254，應用來自相對側之壓力，以MUF材料均勻地填入於半導體晶粒124與TSV半導體晶粒212周圍之開放空間250。MUF材料242可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸酯、或具有適當填料之聚合物。MUF材料242形成於半導體晶粒124與TSV半導體晶粒212之間與周圍且被固化，如同於圖7n中所示。
在圖7o中，藉由研磨器258將包封物240或MUF材料242之一部份去除，以曝露導電通孔218。
圖7p顯示在研磨操作後，由包封物240或MUF材料242所圍繞之半導體晶粒124與TSV半導體晶粒212。在半導體晶粒124對面之TSV半導體晶粒212之作用表面214上形成一積層互連結構260。此積層互連結構260包括：使用圖案化與金屬沉積過程例如：濺鍍、電解質電鍍、無電極電鍍所形成之導電層或RDL 262。導電層262可以為一或更多層之鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他適當導電材料。導電層262包括，用於電性互連之水平部份與垂直部份。導電層262之一部份電性互連至導電通孔218。取決於半導體124與212之設計與功能，導電層262之其他部份可以為電性共用或電性隔離。
使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴霧塗佈、燒結、或熱氧化，在導電層262之間與周圍形成用於電性隔離之絕緣或鈍化層264，用於電性隔離。此絕緣層264包括一或更多層之二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、以及具有類似絕緣與結構性質之其他材料。藉由蝕刻過程去除絕緣層264之一部份，透過一光阻層以曝露導電層262，用於凸塊形成或額外封裝互連。通過導電層230、凸塊234、以及導電通孔218，將積層互連結構260電性互連至半導體晶粒124。
在圖7q中，使用蒸鍍、電解質電鍍、無電極電鍍過程、球滴、或網版印刷過程，在積層互連結構260之經曝露導電層262上沉積導電凸塊材料。此凸塊材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、或焊料、以及上述之組合，而具有選擇性通量溶液。例如，此凸塊材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。使用適當裝附或接合過程將凸塊材料接合至導電層262。在一實施例中，藉由將材料加熱至其熔點以上使凸塊材料回流以形成球或凸塊266。在一些應用中，將凸塊266第二次回流，以改善至導電層262之電性接觸。在凸塊266下形成UBM層，亦可以將凸塊266壓縮接合至導電層262。凸塊266代表可以形成於導電層262上之一種形式互連結構。此互連結構亦可使用柱凸塊、微凸塊、或其他電性互連。
可以通過包封物240與積層互連結構260，以鋸刀或雷射切割工具268將半導體晶粒124單粒化成個別FO-WLCSP或eWLB 270。圖8顯示在單粒化後之FO-WLCSP 270。半導體晶粒124可以大於TSV半導體晶粒212，特別是在以下情形中：此半導體晶粒為一記憶體元件，其具有大儲存容量且用於例如32-40nm之高節點技術。藉由以足夠空間形成重新結構晶圓、且將TSV半導體晶粒212安裝至載體222，可以此重新建構晶圓等級，將此較大半導體晶粒124接合至TSV半導體晶粒212，而具有開放區域以在半導體晶粒124與TSV半導體晶粒212之間沉積包封物240或MUF材料242。亦可以此重新建構晶圓等級形成此積層互連結構260。此具有包封物240之重新建構晶圓保護半導體晶粒124，且提供支撐，用於形成此積層互連結構260。此重新建構晶圓等級包封物與形成互連結構，亦可以減輕處理損害與破裂之風險，以及提供一簡單且低成本製造過程。基板210之後背研磨可以曝露用於垂直互連之導電通孔218，且減少FO-WLCSP 270之厚度。
半導體晶粒124通過凸塊234、導電層230、以及導電通孔218電性互連至此積層互連結構260。此具有導電通孔218、導電層230、絕緣層232、以及凸塊234之TSV半導體晶粒212提供：用於半導體晶粒124之垂直互連之簡單且成本效益的結構，以及通過TSV半導體晶粒導電層與積層互連結構260之有效率封裝堆疊。由於TSV半導體晶粒212可以由與半導體晶粒124類似材料製成，且此積層互連結構260形成於半導體晶粒124與包封物240對面之TSV半導體晶粒212之作用表面214上，TSV半導體晶粒212可以將半導體晶粒124與積層互連結構260間之CTE匹配不良抵消。TSV半導體晶粒212操作為：在TSV半導體晶粒之一側上之半導體晶粒124、與在TSV半導體晶粒之對面側上積層互連結構260之間之緩衝器，以減少翹曲。TSV半導體晶粒212提供用於半導體晶粒124之精細間距(pitch)垂直互連，而適用於高輸入/輸出(I/O)計數應用。
圖9顯示FO-WLCSP 272之實施例，類似於圖6，其具有堆疊在TSV半導體晶粒212上之多個半導體晶粒。類似於圖4a-4c，半導體晶粒274與276來自半導體晶圓。各半導體晶粒274與276具有一後表面與一作用表面，其包括類比或數位電路，以執行主動元件，被動元件，導電層，以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括：一或更多電晶體、二極體、以及形成於作用表面中之其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、ASIC、記憶體、或其他數位處理電路。半導體晶粒274-276亦可以包含積體被動元件(IPD)，例如：電感器、電容器、電阻器，用於射頻(RF)信號處理。將複數個接觸墊形成於作用表面上，且電性互連至作用表面上之電路。在用於半導體晶粒274-276之接觸墊上形成複數個凸塊。在一實施例中，半導體晶粒274-276為覆晶式半導體晶粒。
形成複數個導電通孔278以通過半導體晶粒124、典型地以圖4a-4b中晶圓等級，用於z-方向之垂直互連。同樣地，形成複數個導電通孔280以通過半導體晶粒274，用於z-方向之垂直互連。以凸塊282將半導體晶粒274安裝至半導體晶粒124，以冶金地且電性地互連至導電通孔278。以凸塊284將半導體晶粒276安裝至半導體晶粒274，以冶金地且電性地互連至導電通孔280。在一實施例中，TSV半導體晶粒142為邏輯元件，或DSP與半導體晶粒124與274-276為記憶體元件。將包封物286沉積在半導體晶粒124、274、以及276之上與周圍。
圖10顯示用於FO-WLCSP 290之實施例，其類似於圖6，具有通過包封物170所形成之導電通孔292，用於垂直電性互連至積層互連結構194。使用雷射鑽孔、機械鑽孔、蝕刻、或深離子反應性蝕刻(DRIE)，通過包封物170形成複數個通孔。使用電解質電鍍、無電極電鍍過程、或其他適當金屬沉積過程，將通孔填以鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈦(Ti)、鎢(W)、多晶矽、或其他適當導電材料，以形成z方向之垂直互連導電通孔292。
雖然，在以上已經詳細說明本發明之一或更多個實施例。熟習此技術人士瞭解，可以對其作修正與調整，而不會偏離在以下申請專利範圍中所設定本發明之範圍。
12．．．半導體晶粒
14．．．基板
16．．．凸塊
18．．．導電通孔
20．．．半導體晶粒
22．．．凸塊
24．．．包封物
26．．．凸塊
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．導電信號跡線
56．．．接線封裝
58．．．半導體晶粒
60．．．球狀柵格陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙內線封裝(DIP)
66．．．平台柵格陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四平非導線封裝(QFN)
72．．．四平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．接線
84．．．包封物
88．．．半導體晶粒
92．．．環氧樹脂黏著材料
94．．．接線
96．．．接觸墊
98．．．接觸墊
100．．．包封物
102．．．接觸墊
104．．．凸塊
106．．．中間載體
108．．．作用區域
110．．．凸塊
112．．．凸塊
114．．．信號線
116．．．包封物
120．．．半導體晶粒
122．．．基板材料
124．．．半導體晶粒
126．．．鋸道
128．．．後表面
130．．．作用表面
132．．．導電層
134．．．雷射切割工具
140．．．基板
142．．．半導體晶粒
143．．．鋸道
144．．．作用表面
145．．．後表面
146．．．通孔
148．．．導電通孔
150．．．導電層
152．．．鈍化層
154．．．凸塊
158．．．雷射切割工具
162．．．載體
164．．．雙面帶
168．．．重新組態晶圓
170．．．包封物
172．．．模製填充材料
174．．．追蹤模型
176．．．上模型支撐
178．．．下模型支撐
180．．．開放空間
182．．．噴嘴
184．．．真空輔助器
190．．．研磨器
194．．．積層互連結構
196．．．導電層
198．．．絕緣層
200．．．凸塊
204．．．球狀柵格陣列
210．．．基板
212．．．半導體晶粒
213．．．鋸道
214．．．作用表面
215．．．後表面
216．．．通孔
218．．．TSV
219．．．雷射切割工具
222．．．載體
224．．．介面層
226．．．重新組態晶圓
227．．．表面
228．．．包封物
229．．．研磨器
230．．．導電層
232．．．鈍化層
234．．．凸塊
240．．．包封物
242．．．模製填充材料
244．．．追蹤模型
246．．．上模型支撐
248．．．下模型支撐
250．．．開放空間
252．．．噴嘴
254．．．真空輔助器
258．．．研磨器
260．．．積層互連結構
262．．．導電層
264．．．鈍化層
266．．．凸塊
270．．．FO-WLCSP
272．．．FO-WLCSP
274．．．半導體晶粒
276．．．半導體晶粒
278．．．導電通孔
280．．．導電通孔
282．．．凸塊
284．．．凸塊
286．．．包封物
290．．．FO-WLCSP
292．．．導電通孔
圖1說明具有不同尺寸半導體晶粒之傳統FO-WLCSP；
圖2為具有不同型式封裝安裝至其表面之印刷電路板(PCB)；
圖3a至3c為安裝至PCB之示例半導體封裝之進一步細節；
圖4a至4c為半導體晶圓，具有以鋸道分開複數個半導體晶粒；
圖5a至5p為以晶圓等級接合不同尺寸半導體晶粒之過程；
圖6為FO-WLCSP，其具有根據圖5a至5p接合在一起之不同尺寸半導體晶粒；
圖7a至7q為以晶圓等級接合不同尺寸半導體晶粒之另一過程；
圖8為FO-WLCSP，其具有根據圖7a至7q接合在一起之不同尺寸半導體晶粒；
圖9為安裝至TSV半導體晶粒之三個堆疊半導體晶粒；以及
圖10為通過在TSV半導體晶粒周圍包封物所形成之導電通孔。
124．．．半導體晶粒
128．．．後表面
130．．．作用表面
132．．．導電層
142．．．半導體晶粒
144．．．作用表面
148．．．導電通孔
150．．．導電層
152．．．鈍化層
154．．．凸塊
170．．．包封物
194．．．積層互連結構
196．．．導電層
198．．．絕緣層
200．．．凸塊
204．．．球狀柵格陣列

Claims (16)

  1. 一種製造半導體元件之方法，其包括以下步驟：提供一半導體晶圓，其包含一作用表面以及在該作用表面對面的一第二表面；形成複數個導電通孔，其部份地通過該半導體晶圓之該作用表面；將該半導體晶圓單粒化，以分開一第一半導體晶粒；將一第二半導體晶粒置放於該第一半導體晶粒上，使該作用表面配置成朝向該第二半導體晶粒；將一包封物沉積在該等第一與第二半導體晶粒上以及周圍；將該第二表面之一部份去除，以曝露該等導電通孔的一表面；以及在該第二半導體晶粒對面之該第一半導體晶粒之一表面上形成一互連結構，該互連結構包含一第一絕緣層和一第一導電層。
  2. 如申請專利範圍第1項之方法，其中該第二半導體晶粒之佔用面積大於該第一半導體晶粒之佔用面積。
  3. 如申請專利範圍第1項之方法，更包括：在安裝該第二半導體晶粒前，在該第一半導體晶粒之該作用表面上形成一第二導電層，該第二導電層電性連接至該等導電通孔；以及在該第一半導體晶粒之該作用表面上形成一第二絕緣層。
  4. 如申請專利範圍第1項之方法，其中該第二半導體晶粒包括一記憶體元件。
  5. 如申請專利範圍第1項之方法，更包括將複數個第二半導體晶粒堆疊在該第一半導體晶粒上。
  6. 一種製造半導體元件之方法，包括以下步驟：提供一第一半導體晶粒；形成複數個導電通孔以通過該第一半導體晶粒；將一第一包封物沉積在該第一半導體晶粒周圍；形成一導電層，其係在該第一半導體晶粒的一第一表面上，且其係電性連接至該等導電通孔；形成一第一絕緣層在該第一半導體晶粒的該第一表面和該第一包封物的一第一表面上；將一第二半導體晶粒置放於該第一半導體晶粒的該第一表面、該第一絕緣層和該導電層上，以使得該第一絕緣層的全部是被置放在該第二半導體晶粒下；將一第二包封物沉積在該第二半導體晶粒上，該第二包封物接觸該第一絕緣層；以及在該第一包封物和在該第一半導體晶粒之該第一表面對面的該第一半導體晶粒之一第二表面上形成一互連結構。
  7. 如申請專利範圍第6項之方法，其中該第二半導體晶粒之佔用面積大於該第一半導體晶粒之佔用面積。
  8. 如申請專利範圍第6項之方法，其中形成該互連結構包括： 形成一導電層於該第一半導體晶粒之該第二表面上；以及形成一第二絕緣層於該第一半導體晶粒之該第二表面上。
  9. 如申請專利範圍第6項之方法，更包括：形成該等複數個導電通孔以部份地通過該第一半導體晶粒之該第一表面；以及將該第一半導體晶粒的該第一表面對面之該第一半導體晶粒之一第二表面之一部份去除以曝露該等導電通孔。
  10. 如申請專利範圍第6項之方法，更包括將該第一包封物之一部份去除以曝露該等導電通孔。
  11. 一種半導體元件，包括：一第一半導體晶粒，其具有通過該第一半導體晶粒所形成之複數個導電通孔；一第二半導體晶粒，其安裝於該第一半導體晶粒之一第一表面上，其中該第二半導體晶粒之佔用面積大於該第一半導體晶粒之佔用面積；一包封物，其沉積於該等第一與第二半導體晶粒上以及周圍並且包括沉積於該第二半導體晶粒的一後表面上；一互連結構，其形成於該包封物和該第一半導體晶粒的該第一表面對面之該第一半導體晶粒的一第二表面上；以及一通孔，其形成以通過該包封物而從該互連結構連續地延伸至形成在該第二半導體晶粒的該後表面上之該包封 物的一表面。
  12. 如申請專利範圍第11項之半導體元件，其中該第二半導體晶粒包括一記憶體元件。
  13. 如申請專利範圍第11項之半導體元件，更包括一模製填充材料，其沉積在該等第一與第二半導體晶粒之間。
  14. 如申請專利範圍第11項之半導體元件，更包括：一導電層，其形成於該第一半導體晶粒上且電性連接至該等導電通孔；以及一絕緣層，其形成於該第一半導體晶粒上。
  15. 如申請專利範圍第11項之半導體元件，更包括複數個第二半導體晶粒，其堆疊於該第一半導體晶粒上。
  16. 如申請專利範圍第11項之半導體元件，其中該互連結構包括：一導電層，其形成於該第一半導體晶粒之該第二表面上；以及一絕緣層，其形成於該第一半導體晶粒之該第二表面上。
TW100133588A 2010-09-29 2011-09-19 以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法 TWI573236B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38759510P 2010-09-29 2010-09-29
US13/231,839 US8993377B2 (en) 2010-09-29 2011-09-13 Semiconductor device and method of bonding different size semiconductor die at the wafer level

Publications (2)

Publication Number Publication Date
TW201246483A TW201246483A (en) 2012-11-16
TWI573236B true TWI573236B (zh) 2017-03-01

Family

ID=45869837

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100133588A TWI573236B (zh) 2010-09-29 2011-09-19 以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法

Country Status (4)

Country Link
US (1) US8993377B2 (zh)
CN (1) CN102543772B (zh)
SG (2) SG2014010557A (zh)
TW (1) TWI573236B (zh)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US8810024B2 (en) 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9443783B2 (en) * 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9209156B2 (en) * 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
KR101965127B1 (ko) 2012-10-29 2019-04-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) * 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9000599B2 (en) * 2013-05-13 2015-04-07 Intel Corporation Multichip integration with through silicon via (TSV) die embedded in package
US20160380172A1 (en) * 2013-11-28 2016-12-29 Osram Opto Semiconductors Gmbh Component arrangement and method for producing a component arrangement
US9728415B2 (en) * 2013-12-19 2017-08-08 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer thinning involving edge trimming and CMP
US9583460B2 (en) * 2014-02-14 2017-02-28 Qualcomm Incorporated Integrated device comprising stacked dies on redistribution layers
US10020211B2 (en) * 2014-06-12 2018-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level molding chase design
CN104157617B (zh) 2014-07-29 2017-11-17 华为技术有限公司 芯片集成模块、芯片封装结构及芯片集成方法
US9786623B2 (en) 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US9761571B2 (en) * 2015-09-17 2017-09-12 Deca Technologies Inc. Thermally enhanced fully molded fan-out module
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI824467B (zh) 2016-12-14 2023-12-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11239217B2 (en) 2020-03-30 2022-02-01 Nanya Technology Corporation Semiconductor package including a first sub-package stacked atop a second sub-package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200947628A (en) * 2008-02-12 2009-11-16 United Test & Assembly Ct Lt Semiconductor package and method of making the same
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3516592B2 (ja) 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
JP2001176899A (ja) 1999-12-21 2001-06-29 Sanyo Electric Co Ltd 半導体装置の製造方法
US6867501B2 (en) * 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
US6908784B1 (en) 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6649445B1 (en) 2002-09-11 2003-11-18 Motorola, Inc. Wafer coating and singulation method
JP4205613B2 (ja) * 2004-03-01 2009-01-07 エルピーダメモリ株式会社 半導体装置
JP4983049B2 (ja) * 2005-06-24 2012-07-25 セイコーエプソン株式会社 半導体装置および電子機器
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
KR100896883B1 (ko) 2007-08-16 2009-05-14 주식회사 동부하이텍 반도체칩, 이의 제조방법 및 이를 가지는 적층 패키지
US20090212420A1 (en) 2008-02-22 2009-08-27 Harry Hedler integrated circuit device and method for fabricating same
US7880293B2 (en) 2008-03-25 2011-02-01 Stats Chippac, Ltd. Wafer integrated with permanent carrier and method therefor
US8101460B2 (en) 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US8183087B2 (en) 2008-09-09 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US20100072600A1 (en) * 2008-09-22 2010-03-25 Texas Instrument Incorporated Fine-pitch oblong solder connections for stacking multi-chip packages
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
US8169059B2 (en) 2008-09-30 2012-05-01 Infineon Technologies Ag On-chip RF shields with through substrate conductors
US8158456B2 (en) 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US8168470B2 (en) 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8067308B2 (en) 2009-06-08 2011-11-29 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
KR101078740B1 (ko) * 2009-12-31 2011-11-02 주식회사 하이닉스반도체 스택 패키지 및 그의 제조방법
TWI427753B (zh) * 2010-05-20 2014-02-21 Advanced Semiconductor Eng 封裝結構以及封裝製程

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200947628A (en) * 2008-02-12 2009-11-16 United Test & Assembly Ct Lt Semiconductor package and method of making the same
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias

Also Published As

Publication number Publication date
CN102543772B (zh) 2016-03-02
TW201246483A (en) 2012-11-16
US8993377B2 (en) 2015-03-31
SG2014010557A (en) 2014-04-28
SG179385A1 (en) 2012-04-27
CN102543772A (zh) 2012-07-04
US20120074587A1 (en) 2012-03-29

Similar Documents

Publication Publication Date Title
TWI573236B (zh) 以晶圓等級接合不同尺寸的半導體晶粒之半導體元件及方法
US10607946B2 (en) Semiconductor device and method of forming interconnect substrate for FO-WLCSP
TWI557862B (zh) 形成具有半導體晶粒的ｔｓｖ插入物並在插入物的對置表面上形成增長式的互連結構之半導體元件及方法
TWI488264B (zh) 半導體元件以及形成無載體的薄晶圓的方法
US9337116B2 (en) Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US8994184B2 (en) Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSP
US8895440B2 (en) Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI515810B (zh) 半導體元件以及在垂直互連結構附近形成非流動的底部填充材料的方法
US9064859B2 (en) Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US8921161B2 (en) Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
TWI557872B (zh) 半導體裝置及用於形成具有垂直互連之薄剖面wlcsp於封裝覆蓋區的方法
TWI508226B (zh) 在基板的孔穴中鑲嵌具有直通矽晶穿孔的晶粒用以扇入封裝疊加的電互連之半導體裝置和方法
US8518746B2 (en) Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8883561B2 (en) Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8263435B2 (en) Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
TWI508199B (zh) 半導體元件以及提供具有內部聚合物核心的ｚ互連傳導柱的方法
TWI579960B (zh) 形成具有絕緣環形圈的導電性直通矽晶穿孔（ｔｓｖ）之半導體裝置及方法
US8318541B2 (en) Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
US20130214398A1 (en) Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die
TWI523128B (zh) 為了絕緣層的局部平坦化而在半導體晶粒附近形成保護結構之半導體元件及方法
TW201411746A (zh) 於扇出晶圓級封裝形成當作垂直互連之導線柱的半導體裝置及方法
TW201347052A (zh) 形成低輪廓的嵌入式晶圓級球柵陣列模製的雷射封裝之半導體裝置及方法
TWI524439B (zh) 半導體元件和使用凸塊形成垂直互連結構之方法