TWI599008B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

Info

Publication number
TWI599008B
TWI599008B TW105129743A TW105129743A TWI599008B TW I599008 B TWI599008 B TW I599008B TW 105129743 A TW105129743 A TW 105129743A TW 105129743 A TW105129743 A TW 105129743A TW I599008 B TWI599008 B TW I599008B
Authority
TW
Taiwan
Prior art keywords
semiconductor
wire
conductive
conductive structures
carrier substrate
Prior art date
Application number
TW105129743A
Other languages
English (en)
Other versions
TW201719834A (zh
Inventor
周哲雅
許文松
陳南誠
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/238,454 external-priority patent/US10991669B2/en
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201719834A publication Critical patent/TW201719834A/zh
Application granted granted Critical
Publication of TWI599008B publication Critical patent/TWI599008B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體封裝
本發明係關於一種半導體封裝，特別係關於一種使用覆晶技術的半導體封裝。
為了確保電子產品或通信設備(諸如可穿戴設備)的小型化和多功能性，會要求半導體封裝具有小尺寸，以支援多針連接、高速和高功能。輸入/輸出(1/O)引腳數的增加再加上對高性能積體電路(IC)的需求增加，導致了覆晶封裝的發展。覆晶技術係使用芯片/晶粒上之凸塊以與一封裝基板互連，諸如印刷電路板(Printed Circuit Board，PCB)。倒置晶片並正面向下地接合至該封裝基板。覆晶技術實現了與設備的高密度互連。
但是，隨著晶片尺寸變小，相應地要求PCB的線寬及間距進一步縮小。如此，PCB的製造過程變得更加困難和複雜。而且PCB需要由適合微小佈局的特殊材料製成。相應地，難以降低PCB及含該PCB的半導體封裝的製造成本。
因此，期望一種使用覆晶技術並且具有更低製造成本的新的半導體封裝。
有鑑於此，本發明之目的在於提供一種半導體封裝，可以降低其製造成本。
本發明之實施例係提供了一種半導體封裝，包括：一基座；複數個第一導電結構；以及一半導體組件，通過該等第一導電結構接合至該基座；其中，該半導體組件包括：一載體基底；複數個第二導電結構；以及一第一半導體主體，通過該等第二導電結構接合在該載體基底；其中，該等第一導電結構和該等第二導電結構分別設置在該載體基底的兩相對表面上；其中，該載體基底及該基座均為該第一半導體主體的一扇出結構。
本發明實施例，半導體主體(例如晶粒)並非直接接合至基座，而係先通過一載體基底(作為扇出結構)來使得第一導電結構之間的間距擴大，然後再通過第一導電結構接合至基座，從而使得基座可以無需採用昂貴的ABF1-2-1基座，而可以採用普通的廉價基座，從而降低了半導體封裝的成本。
500a、500b、500c、500d、500e、500f、500g、500h、500i‧‧‧半導體封裝
200、200c、200d、450、660‧‧‧基座
202a、202b、202c、202d、454、100、690、630、670、690‧‧‧導線
204a、204b、204c、204d、462‧‧‧側壁
206a、206b、206c、206d‧‧‧底面
208‧‧‧絕緣層
210、458‧‧‧開口
212a、212b、212c、212d、401、451、460‧‧‧頂面
214、614‧‧‧元件貼附面
216、140‧‧‧銅層
218、130‧‧‧導電緩衝層
220、120‧‧‧焊錫蓋層
222、110、160、600、604、650、700‧‧‧導電結構
230‧‧‧底膠填充材質或底膠
300‧‧‧半導體組件
301‧‧‧半導體主體
302‧‧‧絕緣層
304‧‧‧導電接墊
306、150‧‧‧凸塊下金屬層
400‧‧‧載板
403‧‧‧底面
402a、402b‧‧‧導電種晶層
404a、404b‧‧‧第一導線
410a、410b‧‧‧第二導線
406a‧‧‧第一基座材料層
406b‧‧‧第二基座材料層
408a、408b‧‧‧介層孔插塞
412、414‧‧‧第一表面
416、418‧‧‧第二表面
456‧‧‧額外絕緣材料
W1‧‧‧寬度
610‧‧‧載體基底
640‧‧‧模塑料
P1、P2、P3‧‧‧間距
620‧‧‧IMD層
710‧‧‧散熱基座
720、602‧‧‧黏合層
730‧‧‧散熱界面材料
680‧‧‧導電插塞
通過閱讀接下來的詳細描述及參考所附圖示所做的示例可以更容易地理解本發明，其中：第1-4圖為本發明不同實施例之半導體封裝之剖面示意圖。
第5A-5E圖為本發明一實施例之一形成半導體封裝的過程的各階段的剖面示意圖。
第6A-6E圖為本發明一實施例之一形成半導體封裝的過程的各階段的剖面示意圖。
第7A圖為根據本發明一些實施例之一半導體封裝的一部 分的透視圖。
第7B及7C圖為根據本發明一些實施例之一半導體封裝的一部分的剖面示意圖。
第8A~8D圖為本發明不同實施例之半導體封裝的剖面示意圖。
以下描述為實現本發明的較佳預期模式。該描述僅係出於說明本發明一般原理的目的，而不應視為限制。本發明的範圍可參考所附的申請專利範圍來確定。
參考特定實施例與參考確定的圖式來描述本發明，但是本發明不限制於此，並且本發明僅由申請專利範圍來限定。描述的圖式僅是示意圖而非限制。在圖式中，出於說明目的而誇大了某些元件的尺寸，並且某些元件的尺寸並非按比例繪制。圖示中的尺寸及相對尺寸不對應本發明實踐中的真實尺寸。
第1-4圖為本發明不同實施例之半導體封裝之剖面示意圖。在一些實施例中，上述半導體封裝可為一覆晶封裝(flip chip package)，該覆晶封裝使用一導電結構以將一半導體組件(semiconductor device)連接至一基座。可替換地，上述半導體封裝可為使用一接合線技術的封裝，以將一半導體組件連接至一基座。
例如，導電結構可為一焊料凸塊、銅柱凸塊或者其他合適的導電結構。上述的半導體組件可以為一半導體晶粒/晶片或者含有一半導體晶粒的半導體封裝。該基座可以為一 PCB或者另一合適的基底。
第1圖顯示本發明一實施例之半導體封裝500a之剖面示意圖。請參考第1圖，上述半導體封裝500a可包括一基座200，上述基座200具有一元件貼附面(device attacb surface)214。在本發明一實施例中，基座200，例如為一印刷電路板(PCB)，可由聚丙烯(polypropylene，PP)或者另一合適的材料來形成。並且注意基座200可為一單一層(single layer)結構或一多層(multilayer)結構。
複數條導線(conductive trace)202a，內嵌於基座200中。在本發明一實施例中，導線202a可包括訊號線段或接地線段，上述訊號線段或接地線段可用於半導體組件300的輸入/輸出(input/output，I/O)連接，其中半導體組件300直接安裝(mounted)至基座200上。換言之，導線202a攜帶輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號穿過基座200的至少一部分。因此，每條導線202a的至少一部分作為基座200之一外部連接區。
在一些實施例中，導線202a的寬度W1係設計為大於5μm，諸如介於10μm~20μm之間。然而，應注意導線202a的寬度W1並無限制。對於不同的設計，如果有需要的話，導線的寬度W1可以小於5μm或者為另一合適的值。在一些實施例中，導線202a的長度大於其寬度。因此，導線202a為細長的線(elongated lines)或者為條紋(stripe)。
相反地，接墊結構則又短又厚(stout)。例如，接墊結構的寬度大約為100μm或者大於100μm。接墊結構一般為 矩形、橢圓形或者多邊形。相應地，於同一預定大小的區域內，接墊結構的面積大於導線202a的面積。另外，導線202a的形狀遠不同於接墊結構的形狀。應注意導線202a和接墊結構在形狀和面積上具有本質區別。
更具體地，由於導線202a為細長的並且其寬度遠小於接墊結構的寬度，因此導線202a比接墊結構承受更小的接合應力。由於導線202a比接墊結構更窄，因此在相同區域內，導線202a比接墊結構允許更密集的間距及更多的線路。相反地，導線202a比接墊結構具有更高的I/O密度。每片IC的更多的I/O連接提供更好的設備性能。更小和更靠近的間隔連接符合小型化的要求。
另外，導線202a比接墊結構，能提供基座200的更好的佈局密度，從而降低封裝尺寸及基座200的層數(如能夠需要2~4層導電層，而不是6層)，進而降低了製造成本。應注意導線202a在應力承受、I/O密度和製造成本上，與接墊結構具有本質不同。
半導體組件300可透過一接合製程用面向基座200的主動表面(active surface)而固接於基座200的元件貼附面214上。在本發明一實施例中，半導體組件300可包括一晶片(die)、一被動構件(passive component)、一封裝(package)或一晶圓級封裝(wafer level package)。在本實施例中，半導體組件300可為一覆晶封裝(flip chip package)。半導體組件300的一電路係設置於上述主動表面上，且導電接墊(conductive pad)304係設置於上述電路的一頂部上。上述半導體組件300的上述電路 係藉由設置於半導體組件300的主動表面上的複數個導電結構222互連至基座200之電路。本發明實施例的一訊號流向例如可以為：來自半導體組件300的訊號經過導電結構222直接傳遞至導線202a而不通過接墊來傳遞至導線，然後導線202a攜帶該訊號穿過該基座200的至少部分。
如第1圖所示，半導體組件300可包括一半導體主體301，位於上述半導體主體301上(overlying)之導電接墊304，以及覆蓋導電接墊304之一絕緣層302。在本實施例中，半導體主體301可包括但並非限制於一半導體基板、形成於上述半導體基板的主要表面(main surface)上的電路元件、層間介電層(Inter-Layer Dielectric，ILD)和互連結構。在本發明一實施例中，上述互連結構可包括複數個金屬層、與金屬層交錯堆疊(laminate)的複數個介電層，以及穿過位於半導體主體301上的該些介電層的複數個介層孔插塞(via)。半導體主體301也可以稱為半導體晶粒。
上述導電接墊304可包括上述互連結構的上述金屬層的一最上層金屬層。在一些實施例中，導電接墊304可以包括但不限於鋁、銅或者他們的合金。在一些實施例中，絕緣層302可以為一單一層結構或一多層結構。在一些實施例中，絕緣層302可包括但並非限制於氮化矽、氧化矽、氮氧化矽、聚醯亞胺(polyimide)或上述任意組合。並且，絕緣層302可具有諸如應力緩衝和絕緣等功能。可於絕緣層302中形成複數個開口。每一個開口暴露出導電接墊304的至少一部分。導電接墊304在形狀、面積、應力耐受、I/O密度和製造成本方面不同 於導線202a。
在一些實施例中，導電結構222可包括一導電凸塊結構(例如一銅凸塊結構或一焊錫凸塊結構)、一導線結構，或一導電膏結構(conductive paste structure)。在一些實施例中，導電結構222可為由一金屬堆疊構成的銅凸塊結構，上述金屬堆疊包括一凸塊下金屬層(under bump metallurgy(UBM)layer)306、一銅層216(例如一電鍍銅層)、一導電緩衝層218和一焊錫蓋層(solder cap)220。但是，應注意第1圖所示的導電結構222僅為示例而不是對本發明的限制。
在一些實施例中，可利用例如一濺鍍(sputtering)法或電鍍(plating)法的一沉積製程以及後續的一非等向性蝕刻製程(anisotropic etching process)，於開口中暴露出來的導電接墊304上形成凸塊下金屬層(UBM layer)306。上述非等向性蝕刻製程係於形成導電柱狀物之後進行。凸塊下金屬層306也可延伸於絕緣層302的一頂面上。在本實施例中，凸塊下金屬層306可包括鈦、銅或上述組合。
銅層216(例如一電鍍銅層)，可形成於凸塊下金屬層306上。銅層216可以幫助增強導電結構222的機械強度。絕緣層302中的開口可利用銅層216和凸塊下金屬層306來填充。且位於絕緣層302中的開口內的銅層216和凸塊下金屬層306可形成導電結構222的一集成插塞(integral plug)。銅層216的形成位置(圖未顯示)可利用一乾膜光阻(dry film photoresist)圖型(pattern)或一液態光阻(liquid photoresist)圖型來定義。
可透過電鍍焊錫和圖案化光阻層或透過網印(screen printing)製程和後續的一回焊製程於銅層216上形成焊錫蓋層220。在一些實施例中，導電結構222(例如為導電柱狀結構)可作為導電接墊304的焊點(solder joint)，而導電接墊304係用於傳輸形成於其上的半導體組件300的輸入/輸出(I/O)訊號、接地(ground)訊號或電源(power)訊號。
可利用電鍍法於銅層216和焊錫蓋層220之間形成導電緩衝層218。上述導電緩衝層218可作為形成於其上的焊錫蓋層220的種晶層(seed layer)、一黏著層(adhesion layer)以及一阻障層(barrier layer)。上述的導電緩衝層218可以包括：鎳(Ni)或者另一合適的材料。
在本發明一實施例中，可於半導體組件300和基座200之間的間隙中導入一底膠填充材質230。該底膠填充材質230圍繞該導電結構222。部分的底膠填充材質230可以直接接觸基座200的元件貼附面214。當導線202a從基座200的元件貼附面214凹進時，部分的底膠填充材質230可以延伸進入基座200中。在本發明一實施例中，底膠填充材質或底膠230可包括毛細填充膠(capillary underfill，CUF)、成型底部填充膠(molded underfill，MUF)、非導電性絕緣膠(nonconductive paste，NCP)、非導電性絕緣膜(nonconductive film，NCF)或上述任意組合。
在本發明一實施例中，導線具有一頂面，上述頂面可位於上述基座的一表面的上方、下方或對齊上述基座的一表面，以改善高密度半導體封裝的繞線能力。如第1圖所示，導線202a的頂面212a設置於上述基座200的元件貼附面214的 下方。意即導線202a的一底面206a和導線202a的至少一部分側壁204a係設計連接至或者直接接觸基座200。在一些實施例中，導電結構222的焊錫蓋層220設置為直接觸基座200的元件貼附面214及導線202a的頂面212a。由於導線202a的頂面凹陷於基座200的元件貼附面214內，因此導電結構222的焊錫蓋層220延伸進入基座200。增加凸塊接合至導線的空間(bump-to-trace space)，且有效地避免凸塊接合至導線的橋接問題(the problerm of bump-to-trace bridging)。
第2圖顯示本發明另一實施例之半導體封裝500b之剖面示意圖。上述圖式中的各元件如有與第1圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。在本實施例中，半導體封裝500b包括：一內嵌於基座200中的導線202b。上述的導線202b可具有一頂面212b，上述頂面212b係設計為對齊於基座200的元件貼附面214，以改善用於高密度半導體封裝的繞線能力。意即導線202b的一底面206b和一側壁204b係設計為完全連接至基座200。因此，導電結構222的焊錫蓋層220係設置於基座200的元件貼附面214上，且僅直接接觸導線202b的一頂面212b。
第3圖顯示本發明又一實施例之半導體封裝500c之剖面示意圖。上述圖式中的各元件如有與第1和2圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。在本實施例中，半導體封裝500c包括：一內嵌於基座200中的導線202c。上述的導線202c可具有一頂面212c係設計為位於基座200的元件貼附面214的上方，以改善用於高密度半導體 封裝的繞線能力。意即導線202c的一底面206c和導線202c的僅一部分側壁204c係設計連接至或者直接接觸基座200。在本實施例中，導電結構222的焊錫蓋層220係設置於基座200的元件貼附面214上，且包裹導線202c的一頂面212c和導線202c一部分側壁204c。
如第1~3圖所示，基座200包括：一單層結構。可替換地，基座可以包括：一多層結構。但是，本發明的實施例不限制於此。在其他的一些實施例中，基座200可以包括：多層結構。
第4圖顯示本發明又另一實施例之半導體封裝500d之剖面示意圖。上述圖式中的各元件如有與第1-3圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。在本發明一些實施例中，半導體封裝500d包括：內嵌於基座200中的導線202d。上述的導線202d可具有一頂面212d，上述頂面212d係設計對齊於基座200的元件貼附面214，以改善用於高密度半導體封裝的繞線能力。意即導線202d的一底面206d和一側壁204d係設計為連接至基座200。並且，具有開口210的一絕緣層208係設置於基座200上。上述絕緣層208設置於基座200的元件貼附面214及導線202d的上方。在本實施例中，基座200和絕緣層208可一起視為一多層基座。
如第4圖所示，導線202d從開口210中暴露出來。因此，導電結構222的焊錫蓋層220係形成於絕緣層208上並且延伸進入開口210。如此，焊錫蓋層220通過開口210直接接觸導線202d的頂面212d。應注意絕緣層208不需對齊於導線202d 的側壁204d。可替換地，絕緣層208可設計為位於如第4圖所示的導線202d的側壁204d的外側或內側。
第5A-5E圖為本發明一實施例之一半導體封裝的基座的製造方法的剖面示意圖。第5A-5E圖中的各元件如有與第1-4圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。第5A~5E圖示出了製造兩個基座200c和200d的方法，其中基座200c和200d類似於半導體封裝500a、500b、500c和500d中的基座200。在一些實施例中，製造基座200c和200d的方法也可稱為一雙側基座製程(double-sided base fabricating process)。
如第5A圖所示，提供一載板400，上述載板400具有導電種晶層(conductive seed layer)402a和導電種晶層402b。在本發明一實施例中，載板400可包括FR4環氧玻璃(FR4 glass epoxy)或不鏽鋼(stainless steel)或者另一合適的材料。並且，導電種晶層402a和導電種晶層402b分別位於載體400的一頂面401和一底面403上。導電種晶層402a和導電種晶層402b係作為種晶層以用於後續形成之位於上述載板400的頂面401和底面403上的基座的互連導線。在本發明一實施例中，導電種晶層402a和導電種晶層402b可包括銅或者另一合適的材料。
接著，如第5B圖所示，分別於載板400的頂面401和底面403上形成第一導線404a和第一導線404b。第一導線404a和第一導線404b的底部係連接至導電種晶層402a和導電種晶層402b的頂部。在本發明一實施例中，可利用一電鍍製程(plating process)和一非等向性蝕刻製程形成第一導線404a 和第一導線404b。上述電鍍製程和非等向性蝕刻製程係同時於上述載板400的頂面401和底面403進行。在本發明一實施例中，電鍍製程可包括一有電電鍍製程(electrical plating process)。
在本發明一實施例中，第一導線404a和第一導線404b可包括銅或者另一合適的材料。在本發明一實施例中，第一導線404a和第一導線404b的寬度可設計為大於5μm。然而，應注意導線的寬度並無限制。對於不同的設計，如果有需要的話，導線的寬度可以小於5μm。在本實施例中，上述非等向性蝕刻製程可精確地控制第一導線404a和404b的寬度。
接著，如第5C圖所示，進行一堆疊製程，將一第一基座材料層406a和一第二基座材料層406b分別堆疊於載板400的頂面401和底面403上。其中第一基座材料層406a和第二基座材料層406b分別覆蓋第一導線404a和第一導線404b。在本實施例中，同時於上述載板400的頂面401和底面403上進行第一基座材料層406a和第二基座材料層406b的堆疊製程。在本發明一實施例中，第一基座材料層406a和第二基座材料層406b可包括聚丙烯(polypropylene，PP)或者另一合適的材料。
接著，請再參考第5C圖，進行一鑽孔製程，以形成穿過第一基座材料層406a和第二基座材料層406b的開口(圖未顯示)，以定義後續形成的介層孔插塞408a和介層孔插塞408b的位置。在本發明一實施例中，上述鑽孔製程包括一雷射鑽孔製程、一蝕刻鑽孔製程或一機械鑽孔製程。在本實施例中，上述鑽孔製程同時在上述第一基座材料層406a和第二基座 材料層406b上進行。
接著，進行一電鍍製程，將一導電材料填入上述開口中，以分別在頂面401和底面403上形成介層孔插塞408a和介層孔插塞408b。其中上述介層孔插塞408a和介層孔插塞408b將第一導線404a和第一導線404b互連至後續形成的第二導線410a和第二導線410b。在一些實施例中，上述電鍍製程同時在上述第一基座材料層406a和第二基座材料層406b上進行。
接著，請再參考第5C圖，分別於上述第一基座材料層406a的第一表面412上和第二基座材料層406b的第一表面414上形成複數個第二導線410a~410b。上述第一基座材料層406a的第一表面412和第二基座材料層406b的第一表面414分別遠離上述載板400的頂面401和底面403。可利用一電鍍製程和一非等向性蝕刻製程形成第二導線410a和第二導線410b。上述電鍍製程和非等向性蝕刻製程係同時於上述第一基座材料層406a的第一表面412上和第二基座材料層406b的第一表面414上進行。在本發明一實施例中，電鍍製程可包括一有電電鍍製程。
在本發明一實施例中第二導線410a和第二導線410b可包括銅。在本發明一實施例中，第二導線410a和第二導線410b的寬度可設計為大於5μm。然而，應注意導線的寬度並無限制。對於不同的設計，如果有需要的話，導線的寬度可以小於5μm。在本實施例中，上述非等向性蝕刻製程可精確地控制第二導線410a和第二導線410b的寬度。
接著，如第5D圖和第5E圖所示，將帶有第一導線 404a和第二導線410a的第一基座材料層406a以及帶有該第一導線404b和該第二導線410b的第二基座材料層406b分別從如上述載板400的頂面401和底面403分離，以形成彼此分離的一基座200c和一基座200d。接著，分別從基座200c和基座200d上移除導電種晶層402a和導電種晶層402b。
如第5D圖和第5E圖所示，第一導線404a和第一導線404b係分別對齊於基座200c的第二表面416和基座200d的第二表面418，其中第二表面416和第二表面418分別相對於第一表面412和第一表面414。在本實施例中，係利用雙側基座製程(double-sided base fabricating process)，同時於相對表面(載體400的頂面401和底面403)上製造基座200c和基座200d。
可對本發明實施例做出各種變形和/或修改。在其他的一些實施例中，分離如第5D圖和第5E圖所示的基座200c和基座200d之後，可選擇性分別於基座200c的第二表面416上和基座200d的第二表面418上形成具有開口的保護層(passivation layer)或絕緣層(圖未示)。在本實施例中，基座200c/基座200d和其上的鈍化層或絕緣層可一起視為一多層基座(multilayer base)。在本實施例中，基座200c的第一導線404a或基座200d的第一導線404b從鈍化層或絕緣層的開口中暴露出來。具有開口的絕緣層或鈍化層以及第一導線404a/第一導線404b可類似於如第4圖所示的具有開口210的絕緣層208以及導線202d。
第6A-6E圖為本發明另一實施例之一半導體封裝的製造方法的剖面示意圖。上述圖式中的各元件如有與第1-4 圖、第5A-5E圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。第6E圖顯示本發明另一實施例之半導體封裝500e之剖面示意圖。
如第6A圖所示，提供具有一頂面451之一基座450。接著，如第6B圖所示，於上述基座450的頂面451上形成至少一條導線454。在本發明一實施例中，可利用一電鍍製程和一非等向性蝕刻製程形成導線454。在本發明一實施例中，電鍍製程可包括一有電電鍍製程。在本發明一實施例中，導線454可包括銅或者另一合適的材料。在本發明一實施例中，導線454的寬度可設計大於5μm。然而，應注意導線的寬度並無限制。對於不同的設計，如果有需要的話，導線的寬度可以小於5μm。在本實施例中，上述非等向性蝕刻製程可精確地控制導線454的寬度。
接著，如第6C圖所示，進行一堆疊製程，於上述基座450的頂面451上設置一額外絕緣材料456。並且，上述額外絕緣材料456覆蓋導線454的頂面460和側壁462。在一些實施例中，基座450及其上的絕緣層456可一起視為多層基座。
接著，請參考第6d圖，進行一鑽孔製程，以形成穿過上述額外絕緣材料456的至少一開口458，以定義後續形成的導電結構的位置，上述導電結構例如可為一銅凸塊結構或一焊錫凸塊結構。在本發明一實施例中，上述鑽孔製程包括一雷射鑽孔製程、一蝕刻鑽孔製程或一機械鑽孔製程。在本實施例中，導線454的頂面460會從上述額外絕緣材料456的開口458中暴露出來。
接著，請參考第6E圖，進行一接合製程，將一半導體組件300藉由導電結構222固接於基座450。上述圖式中的半導體組件300和導電結構222之元件如有與第1-4圖所示相同或相似的部分，則可參考前面的相關敍述，在此不做重複說明。進行接合製程之後，導電結構222係設置穿過上述額外絕緣材料456的開口458，且直接接觸至導線454的頂面460。接著，可於半導體組件300和上述額外絕緣材料456之間的一間隙中導入一底膠填充材質230。在本發明一實施例中，底膠填充材質230可包括毛細底膠填充材質(capillary underfill，CUF)、成型底膠填充材質(molded underfill，MUF)、非導電性絕緣膠(nonconductive paste，NCP)、非導電性絕緣膜(nonconductive film，NCF)或上述任意組合。最後，上述基座450、上述額外絕緣材料456、上述半導體組件300、上述導線454和上述導電結構222一起形成一半導體封裝500e。
本發明實施例係提供一種半導體封裝。上述半導體封裝係設計包括內嵌於一基座(例如為印刷電路板(PCB))中的導線。上述導線具有一頂面，上述頂面可位於上述基座的一表面的上方、下方或對齊上述基座的一表面，以改善用於高密度半導體封裝的繞線能力。並且，上述導線的寬度可設計大於5μm。再者，上述基座可包括一單一層結構或一多層結構。本發明實施例也提供一種用於一半導體封裝的一基座的製造方法。在本發明一實施例中，上述方法可同時於一載板的兩側製造兩個基座。並且，導線內嵌於上述基座中。再者，可利用一電鍍製程和一非等向性蝕刻製程形成導線，且上述非等向性 蝕刻製程可精確地控制上述導線的寬度。在本發明另一實施例中，上述方法可製造包括一單一層結構或一多層結構的一基座，以增加設計選擇。
第7A圖為根據本發明一實施例的半導體封裝的一部分之透視圖。第7B和7C圖為根據本發明一實施例的半導體封裝的一部分之剖面示意圖。第7A~7C圖所示的半導體封裝的一部分可以為半導體封裝500a、500b、500c、500d或500e的一部分。
第7A~7C圖所示的導線100為細長的線或者條紋。也就是，導線100的長度遠大於其寬度。在一些實施例中，導線100的至少一部分嵌入於基座(未示出)中，諸如基座200，200c或200d。導線100的一部分作為基座的外部連接區。在一些實施例中，導線100相同或者相似於導線202a、202b、202c、202d、404a、404b或454，並且出於簡潔而不再描述。
如第7A~7C圖所示，導電結構110係設置在導線100的作為外部連接區的部分上。在一些實施例中，導電結構110包括：一焊錫蓋層120，一導電緩衝層130，一銅層140及一UBM層150。在一些實施例中，上述焊錫蓋層120，導電緩衝層130及銅層140的寬度大於導線100的寬度。對於不同實施例，可以替換或者移除上述焊錫蓋層120、導電緩衝層130、銅層140及UBM層150中的至少一個。可以將另外的層添加至導電結構110。
上述焊錫蓋層120夾在導線100及導電緩衝層130之間。上述銅層140夾在導電緩衝層130和UBM層150之間。在 一些實施例中，上述焊錫蓋層120、導電緩衝層130、銅層140及UBM層150可以分別相同或者類似於焊錫蓋層220、導電緩衝層218、銅層216及UBM層306。相應地，出於簡潔而不再描述。
如第7A~7C圖所示，一導電結構160設置在導電結構110上。在一些實施例中，導電結構160為一導電接墊。上述導電接墊可以包含於互連結構或者RDL結構的最上層金屬層中。導電結構160可以相同或者類似於導電接墊304。在一些實施例中，導電結構160的形狀為矩形或者八邊形，使得導電結構160的長度大致相等於其寬度。在一些實施例中，導電結構160比導線100短，如第7B圖所示。在一些實施例中，導電結構160比導線100寬，如第7C圖所示。在一些實施例中，導線100的形狀和面積不同於導電結構160。
第8A~8D圖為根據本發明不同實施例的半導體封裝之剖面示意圖。如第8A圖所示，一半導體封裝500f包括：一半導體組件300、一導電結構650、一基座660及一導電結構700。上述半導體組件300為一封裝並且使用覆晶技術安置在基座660的元件貼附面614上。如此，半導體組件300經由導電結構650和基座660電性連接至導電結構700。在一些實施例中，半導體組件300可以使用接合製程(相同於上述提及的接合製程)安置在基座660的元件貼附面614上。也就是說，半導體組件300通過導電結構650接合至嵌入於基座660中的導線690。
如第8A圖所示，半導體組件300包括：一半導體主體301、一導電結構600、一載體基底610及一模塑料640。在一些實施例中，上述半導體主體301可以包括但不限於：一半導 體層、於該半導體層的主要表面上製造的電路元件、ILD層和一互連結構。在一些實施例中，該互連結構可以包括：導電層、與該導電層交替層壓的介電層、以及複數個穿過該半導體層上的介電層而形成的介層孔插塞。
在半導體主體301的主動面上存在導電接墊304和絕緣層302。半導體主體301的主動面面向基座660的元件貼附面614。導電接墊304包含於互連結構中的最上層導電層中。在一些實施例中，導電接墊304類似或者相同於第7A~7C圖所示的導電結構160。在一些實施例中，導電接墊304可以包括但不限於：鋁、銅或者他們的合金。在一些實施例中，絕緣層302可以為單層結構或者多層結構。在一些實施例中，絕緣層302可以包括但不限於：氮化矽、氧化矽、氮氧化矽、聚酰亞胺或者他們的任意組合。於絕緣層302中形成複數個開口，以部分地暴露導電接墊304。
導電結構600將導電接墊304連接至載體基底610。每個導電結構600的頂面直接接觸一個導電接墊304。導電結構600的底面直接接觸載體基底610中的一條導線。在一些實施例中，導電結構600為導電凸塊、導電柱、導電膠結構、或者另一合適的導電結構。導電結構600可以包括：焊料(solder)、銅或者另一合適的導電材料。在一些實施例中，導電結構600相同或者類似於第1~4圖所示的導電結構222或者第7A~7C圖所示的導電結構110。例如，導電結構600可以包括：焊錫蓋層、導電緩衝層、銅層和UBM層。在一些實施例中，導電結構600的尺寸小於導電結構650的尺寸。在一些實施例中， 導電結構600之間的間距P1小於導電結構650之間的間距P2。
載體基底610也可稱為“基座”，相同或者類似於第1~4圖所示的基座200。在一些實施例中，半導體主體301使用與上述提及的接合製程相同的接合製程安置在載體基底610上。也就是說，半導體主體301通過導電結構600接合至嵌入於載體基底610中的導線。如此，導電結構600的底面直接接觸嵌入於載體基底610中的導線，而不接觸接墊結構/部分。
在一些實施例中，載體基底610可以為RDL結構。載體基底610包括：一條或者複數條導線630，係設置在IMD層620中並且被IMD層620圍繞。最上層的導線630電性連接至導電結構600。最底層的導線630電性連接至導電結構650。最上層的導線630相同或者類似於導線202a、202b、202c、202d、404a、404b或454。導線630的至少一部分嵌入於載體基底610中。例如，導線630的底面低於載體基底610的頂面，該頂面面向半導體主體301。另外，導線630的至少下面部分的側壁埋入於載體基底610中。導線630可以包括：訊號線段或者接地線段。訊號線段或者接地線段用於安置於載體基底610上的半導體主體301的I/O連接。
根據本發明實施例，最頂層的導線630具有一頂面，該頂面位於該載體基底610的頂面的上方、下方或者對齊該載體基底610的頂面。如此，可以顯著地改善高密度半導體封裝的繞線能力。在一些實施例中，導線630的寬度小於導電接墊304的寬度，類似於第7A~7C圖所示的導線100和導電結構160之間的關係。在一些實施例中，導線630不包括：接墊結構 /部分。導線630在形狀、面積、應力承受、I/O密度和製造成本等方面不同於接墊結構。但是，在其他實施例中，導電結構600可以不直接接合至導線630上，而係在載體基底610的頂面上設置導電接墊(可嵌入於載體基底610中)，然後將導電結構600設置在該導電接墊上，例如該導電接墊直接接觸導電結構600的底面；另外，將該導線630電性連接至該導電接墊，例如該導線630與該導電接墊可以一體成形。
IMD層620可以包括：複數個次介電(sub-dielectric)層。為了簡化示意圖，在此中僅繪示了單個介電層作為示例。在一些實施例中，IMD層620可以由有機材料、非有機村料或者類似物形成，其中有機材料包括：聚合物基材料，非有機材料包括：氮化矽(SiNx)、氧化矽(SiOx)、石墨烯或者類似物。在一些實施例中，IMD層620為高k值介電層(k為介電層的介電常數)。在其他的一些實施例中，IMD層620可以由光敏材料形成，該光敏材料包括：乾膜光阻(dry film photoresist)或者貼膜(taping film)。
如第8A圖所示，載體基底610的寬度大於半導體主體301的寬度，並且基座660的寬度大於載體基底610的寬度。如此，半導體主體301的電路通過大於一次的扇出(即通過載體基底610和基座660)連接至導電結構700。
模塑料640圍繞半導體主體301及導電結構600。在一些實施例中，模塑料640直接接觸載體基底610的導線630。在一些實施例中，模塑料640由諸如環氧樹脂、樹脂、可塑聚合物或者另一合適的模塑材料等非導電材料形成。在一些實施 例中，模塑料640在實質為液體時應用，接著通過化學反應固化。在其他一些實施例中，模塑料640為UV(紫外)或者熱固化的聚合物，該聚合物可作為凝膠或者可塑固定來應用，並且接著通過UV或者熱固化製程來固化。模塑料640可以按照模型進行固化。
在一些實施例中，導電結構650可以為導電凸塊、導電柱、導電膏結構、或者另一合適的導電結構。導電結構650可以包括：焊料、銅或者另一合適的導電材料。在一些實施例中，導電結構650相同或者類似於導電結構110或222。例如，導電結構650可以包括：焊錫蓋層、導電緩衝層、銅層和UBM層。
根據一些實施例，基座660為一PCB並且可以由含有玻璃纖維的聚丙烯(polypropylene，PP)、環氧樹脂、聚酰亞胺、氰酸酯、另一合適的材料或者他們的組合。在一些實施例中，基座660可以為一多層結構，諸如兩層或者四層。圖示的基座660的配置僅為示例並且不是對本發明的限制。應注意根據一些實施例，基座660為非ABF(Ajinomoto Build-Up Film，味之素複合膜)1-2-1基座。在一些實施例中，基座660的材料不同於ABF，以便基座660的成本低於ABF1-2-1基座的成本。
基座660也包括：導線670、690和位於導線670與690之間的導電插塞680。導電插塞680和導線670、690攜帶輸入/輸出訊號、接地訊號或電源訊號穿過基座660的至少部分。基座660上方的導電結構650通過導線670、690及導電插塞680 電性連接至基座660下方的導電結構700。在一些實施例中，導電插塞680之一夾在導線670之一和導線690之一之間。在其他的一些實施例中，基座660進一步包括：一條或者複數條導線，位於導線670及690之間，以及導電插塞680之一穿透基座660中的所有導線。
導電結構700接合至基座660的底面，該底面背向載體基底610並且比基座660的元件貼附面614更遠離導線690。在一些實施例中，導電結構700為導電凸塊或者另一合適的導電結構。導電結構700可以包括：焊料或者另一合適的導電材料。在一些實施例中，導電結構700的尺寸大於導電結構650及600的尺寸。在一些實施例中，導電結構700之間的間距P3大於導電結構650之間的間距P2。在一些實施例中，間距P3大於導電結構600之間的間距P1。
在一些實施例中，間距P3與間距P1之間的比值大於3，諸如大約介於5~9之間。在一些實施例中，間距P3與間距P2之間的比值大於1並且小於等於3。但是，應注意對於上述比值沒有限制。對於不同的設計，如果有需求，間距P3與間距P2之間的比值可以大於3。
在一些實施例中，底膠填充材質(諸如如第1~4圖所示的底膠填充材質230)設置在半導體組件300與基座660之間的間隙中。該底膠填充材質圍繞該導電結構650。
如第8A圖所示，該半導體封裝500f另外包括：一散熱基座(heat slug)710、一黏合層720、以及一散熱界面材料(thermal interface material，TIM)730。該散熱基座710通 過該黏合層720附著在基座660的元件貼附面614上。如此，散熱基座710覆蓋半導體組件300。在一些實施例中，黏合層720直接接觸基座660中的導線690之一。
TIM730位於半導體組件300及散熱基座710之間，以消散來自半導體組件300的熱量。在一些實施例中，TIM730夾在半導體主體301的非主動面及散熱基座710之間。在其他一些實施例中，半導體封裝500f不包括：該散熱基座710，該黏合層720和/或該TIM730。
儘管第8A圖所示的實施例提供了含有半導體主體301的封裝，但是本發明的實施例不限制於此。第8B圖示出了一半導體封裝500g，類似於該半導體封裝500f。第8B圖與第8A圖中，相同的元件使用相同的參考符號，並且出於簡潔而不贅述。
如第8B圖所示，該半導體組件300包括：複數個半導體主體301。該等半導體主體301可以為複數個具有相同或者不同功能的半導體晶粒。該等半導體晶粒具有相同或者不同的尺寸。半導體組件300中的半導體晶粒的實際數量、功能和尺寸由設計要求決定，並且不是限制。可替換地，半導體主體301之一可以由IPD(Integrated Passive Device，集成被動元件)、電容、電感、變容二極體或者另一合適的被動元件替換。半導體主體301由模塑料640圍繞。TIM730介於半導體組件300及散熱基座710之間，以消散來自半導體組件300的熱量。
可以對本發明實施例做出各種變化和/或修改。第8C圖示出了一半導體封裝500h，類似於該半導體封裝500g。第 8C圖和第8A圖及第8B圖中相同的元件，使用相同的參考符號來標記，並且出於簡潔而不贅述。
如第8C圖所示，倒置半導體主體301之一，並且通過導電結構600將其導電接墊304電性連接至載體基底610。另一半導體主體301中正面向上並且通過黏合層602附著至載體基底610上。另外，該另一半導體主體301的導電接墊304通過導電結構604電性連接至載體基底610，該導電結構604可不同於導電結構600。例如，導電結構600為導電柱，而導電結構604為接合線。導電結構604封閉於模塑料640中。模塑料640的一部分在半導體主體301之一和TIM730之間延伸。用於電性連接導電接墊304及載體基底610的真實的導電結構由設計要求決定，並且不受限制。
儘管第8B及8C圖示出的實施例提供了含有複數個並排設置的半導體主體301的封裝，但是本發明的實施例不限制於此。第8D圖示出了一半導體封裝500i，類似於半導體封裝500h。第8D圖中與第8A~8C圖相同的元件，使用相同的參考附號來標記，並且出於簡潔而不再贅述。
如第8D圖所示，半導體組件300包括：複數個垂直堆疊的半導體主體301。翻轉下面的半導體主體301並且通過導電結構600將其導電接墊304電性連接至載體基底610。上面覆蓋的半導體主體301正面向上並且通過黏合層602附著至下面的半導體主體301上。另外，其導電接墊304通過導電結構604電性連接至載體基底610，其中該導電結構604不同於導電結構600。例如，導電結構600為導電柱而導電結構604為接合線。 半導體主體301由模塑料640圍繞並且通過模塑料640與TIM730分隔開。在其他的一些實施例中，在半導體組件300與散熱基座710之間可以沒有TIM。
根據本發明一些實施例的半導體封裝提供了各種優勢。該半導體封裝包括：一半導體組件，使用覆晶技術接合在一基座上。該半導體組件為一封裝。該封裝包括：至少一半導體晶粒及一扇出結構(諸如一載體基底)，該扇出結構設置在該半導體晶粒及該第一導電結構之間。具體地，半導體晶粒接合至嵌入於扇出結構中的導線，而不是接墊結構。扇出結構通過第一導電結構將半導體晶粒電性連接至基座下方的第二導電結構。由於扇出結構，因此第一導電結構之間的間距變大。另外，第二導電結構之間的間距與第一導電結構之間的間距的差變小。如此，基座不限定於具有小線寬及間距的基座。顯著的增強了基座的設計靈活性。例如，基座可以為用於PCB的普通的廉價基座，而不是昂貴的ABF1-2-1基座。相應地，可以顯著地降低基座和含有該基座的半導體封裝的製造成本。本發明實施例提供了具有改善的集成靈活性及更低的製造成本的半導體封裝。
雖然本發明已以實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
500f‧‧‧半導體封裝
610‧‧‧載體基底
640‧‧‧模塑料
P1、P2、P3‧‧‧間距
620‧‧‧IMD層
710‧‧‧散熱基座
720‧‧‧黏合層
730‧‧‧散熱界面材料
630、670、690‧‧‧導線
614‧‧‧元件貼附面
660‧‧‧基座
680‧‧‧導電插塞
304‧‧‧導電接墊
301‧‧‧半導體主體
302‧‧‧絕緣層
600、650、700‧‧‧導電結構
300‧‧‧半導體組件

Claims (14)

  1. 一種半導體封裝，包括：一基座；複數個第一導電結構；以及一半導體組件，通過該等第一導電結構接合至該基座；其中，該半導體組件包括：一載體基底；複數個第二導電結構；以及一第一半導體晶粒，通過該等第二導電結構接合至該載體基底；其中，該等第一導電結構和該等第二導電結構分別設置在該載體基底的兩相對表面上；其中，該載基基底及該基座均為該第一半導體晶粒的一扇出結構；其中，該等第一導電結構之間的間距大於該等第二導電結構之間的間距；其中，該載體基底包括：複數條導線，該等第二導電結構直接接合在該等導線上。
  2. 如申請專利範圍第1項所述半導體封裝，其中，進一步包括：複數個第三導電結構，接合在該基座上，並且該等第一導電結構和該等第三導電結構分別設置在該基座的兩相對表面上。
  3. 如申請專利範圍第2項所述半導體封裝，其中，該等第一導電結構的尺寸大於該等第二導電結構的尺寸且小於該等第 三導電結構的尺寸。
  4. 如申請專利範圍第2項所述半導體封裝，其中，該等第一導電結構之間的間距小於該等第三導電結構之間的間距。
  5. 如申請專利範圍第2項所述半導體封裝，其中，該等第三導電結構之間的間距與該等第二導電結構之間的間距之比值介於5~9之間，並且該等第三導電結構之間的間距與該等第一導電結構之間的間距之比值大於1且小於等於3。
  6. 如申請專利範圍第1項所述半導體封裝，其中，該半導體組件進一步包括：一模塑料，設置在該載體基底上，並且圍繞該第一半導體晶粒及該等第二導電結構。
  7. 如申請專利範圍第6項所述半導體封裝，其中，進一步包括：一底膠填充材質，設置在該基座上，並且圍繞該半導體組件及該等第一導電結構，以及填充該半導體組件與該基座之間的間隙。
  8. 如申請專利範圍第1項所述半導體封裝，其中，該載體基底的寬度大於該第一半導體晶粒的寬度，且小於該基座的寬度。
  9. 如申請專利範圍第1項所述半導體封裝，其中，該半導體組件還包括：一第二半導體晶粒，與該第一半導體晶粒並排設置在該載體基底上或者堆疊在該第一半導體晶粒上。
  10. 如申請專利範圍第9項所述半導體封裝，其中，該第一半導體晶粒使用覆晶方式接合至該載體基底； 當該第二半導體晶粒與該第一半導體晶粒並排設置在該載體基底上時，該第二半導體晶粒使用覆晶或者線接合方式接合至該載體基底；該第二半導體晶粒堆疊在該第一半導體晶粒上時，該第二半導體晶粒使用線接合方式接合至該載體基底。
  11. 如申請專利範圍第1項所述半導體封裝，其中，進一步包括：一散熱基座，通過一黏合層附著至該基座，並且覆蓋該半導體組件。
  12. 如申請專利範圍第11項所述半導體封裝，其中，進一步包括：一散熱界面材料，位於該散熱基座與該半導體組件之間。
  13. 如申請專利範圍第1項所述半導體封裝，其中，該導線為細長形的；或者，該導線用於攜帶輸入/輸出訊號、接地訊號或電源訊號穿過該載體基底的至少一部分；或者，該導線的頂面位於該載體基底面向該第一半導體晶粒的表面的上方、下方或者對齊；或者，該導線的寬度小於該第一半導體晶粒上的連接至該第二導電結構的接墊的寬度；或者，該導線的形狀不同於該第一半導體晶粒上的連接至該第二導電結構的接墊的形狀。
  14. 如申請專利範圍第1項所述半導體封裝，其中，該第二導電結構包括：一焊錫蓋層，直接接觸該導線；或者，該第二導電結構包括：寬度大於該導線的寬度的一銅層和/或寬度 大於該導線的寬度的焊錫蓋層。
TW105129743A 2015-09-16 2016-09-13 半導體封裝 TWI599008B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562219247P 2015-09-16 2015-09-16
US15/238,454 US10991669B2 (en) 2012-07-31 2016-08-16 Semiconductor package using flip-chip technology

Publications (2)

Publication Number Publication Date
TW201719834A TW201719834A (zh) 2017-06-01
TWI599008B true TWI599008B (zh) 2017-09-11

Family

ID=56893786

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105129743A TWI599008B (zh) 2015-09-16 2016-09-13 半導體封裝

Country Status (3)

Country Link
EP (1) EP3154084A3 (zh)
CN (1) CN106910732A (zh)
TW (1) TWI599008B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI701981B (zh) * 2019-05-07 2020-08-11 欣興電子股份有限公司 線路載板及其製作方法
US10888001B2 (en) 2018-06-08 2021-01-05 Unimicron Technology Corp. Circuit carrier board structure and manufacturing method thereof
US10999939B2 (en) 2018-06-08 2021-05-04 Unimicron Technology Corp. Circuit carrier board and manufacturing method thereof
US11032917B2 (en) 2018-06-08 2021-06-08 Unimicron Technology Corp. Circuit carrier board and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI701747B (zh) * 2018-02-12 2020-08-11 晶元光電股份有限公司 半導體裝置及其製造方法
KR102140554B1 (ko) 2018-09-12 2020-08-03 삼성전자주식회사 반도체 패키지 및 패키지 실장 기판

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003163459A (ja) * 2001-11-26 2003-06-06 Sony Corp 高周波回路ブロック体及びその製造方法、高周波モジュール装置及びその製造方法。
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
JP5221315B2 (ja) * 2008-12-17 2013-06-26 新光電気工業株式会社 配線基板及びその製造方法
KR101780423B1 (ko) * 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9099340B2 (en) * 2011-10-07 2015-08-04 Volterra Semiconductor Corporation Power management applications of interconnect substrates
JP5893387B2 (ja) * 2011-12-22 2016-03-23 新光電気工業株式会社 電子装置及びその製造方法
TWI562295B (en) * 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9159670B2 (en) * 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US10037941B2 (en) * 2014-12-12 2018-07-31 Qualcomm Incorporated Integrated device package comprising photo sensitive fill between a substrate and a die

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10888001B2 (en) 2018-06-08 2021-01-05 Unimicron Technology Corp. Circuit carrier board structure and manufacturing method thereof
US10999939B2 (en) 2018-06-08 2021-05-04 Unimicron Technology Corp. Circuit carrier board and manufacturing method thereof
US11032917B2 (en) 2018-06-08 2021-06-08 Unimicron Technology Corp. Circuit carrier board and manufacturing method thereof
TWI701981B (zh) * 2019-05-07 2020-08-11 欣興電子股份有限公司 線路載板及其製作方法

Also Published As

Publication number Publication date
EP3154084A3 (en) 2017-04-26
CN106910732A (zh) 2017-06-30
TW201719834A (zh) 2017-06-01
EP3154084A2 (en) 2017-04-12

Similar Documents

Publication Publication Date Title
TWI599008B (zh) 半導體封裝
US10672647B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US7242081B1 (en) Stacked package structure
US9502335B2 (en) Package structure and method for fabricating the same
US10424563B2 (en) Semiconductor package assembly and method for forming the same
US9040359B2 (en) Molded interposer package and method for fabricating the same
EP2936558B1 (en) Method for fabricating base for semiconductor package
US10573615B2 (en) Semiconductor package and method for fabricating base for semiconductor package
US20210202425A1 (en) Semiconductor package using flip-chip technology
TW201813018A (zh) 扇出晶圓級封裝型半導體封裝以及包含其的疊層封裝型半導體封裝
WO2015175559A1 (en) Circuit assemblies with multiple interposer substrates, and methods of fabrication
TWI754839B (zh) 封裝結構及其形成方法
US10325880B2 (en) Hybrid 3D/2.5D interposer
US20230245923A1 (en) Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
US11854961B2 (en) Package substrate and method of fabricating the same and chip package structure
TWI543311B (zh) 半導體封裝基座的製造方法
TW202137350A (zh) 半導體裝置及其製造方法
CN116646330A (zh) 电子封装件及其制法