CN101840912B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101840912B
CN101840912B CN2010101302157A CN201010130215A CN101840912B CN 101840912 B CN101840912 B CN 101840912B CN 2010101302157 A CN2010101302157 A CN 2010101302157A CN 201010130215 A CN201010130215 A CN 201010130215A CN 101840912 B CN101840912 B CN 101840912B
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substrate
layer
dielectric layer
conductive
guide hole
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CN101840912A (zh
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罗明健
吴国雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种半导体装置及其制造方法，用以制造具有穿硅导孔(TSV)的半导体芯片连接。该半导体装置包括：一第一基板；一第一多层介电层；一第一导孔延伸穿越该第一基板及一层或多层该第一多层介电层；以及一第二导孔延伸穿越该第一基板及一层或多层该第一多层介电层，该第二导孔所穿越该第一多层介电层的层数多于该第一导孔所穿越该第一多层介电层的层数。本发明的半导体芯片制作有先导孔工艺的穿硅导孔及后导孔工艺的穿硅导孔，为了建立一低电阻的路径，供相邻芯片之间的芯片连接，以及提供一低电阻的路径供多重芯片之间的馈孔(feedthrough)通道。通过精确地视实际TSV的使用而提供不同的穿硅导孔(TSV)，能降低整体的连线电阻。

Description

半导体装置及其制造方法
技术领域
本发明有关于一种系统及方法以连接半导体装置，特别有关于一种系统及方法通过使用先导孔工艺的穿硅导孔(via-first TSV)及后导孔工艺的穿硅导孔(via-last TSV)已连接芯片于系统级封装(System-in-Package，简称SiP)构造中。
背景技术
大体上，穿硅导孔(through-silicon via，简称TSV)已用于形成电性连接于系统级封装(SiP)构造中，以连接多重半导体芯片穿透半导体芯片基板。一种形成所述穿硅导孔(TSV)的方法被称为先导孔(via-first)工艺，在形成半导体芯片的金属化层之前，先形成穿硅导孔(TSV)穿透该基板，并且该穿硅导孔电性连接至靠近该基板的一金属化层。然而，为维持一低电阻的路径至该基板上的有源元件，此一连接事实上却增加任何馈孔(feedthrough)连接(即提供电力至另一芯片)，其必须也包括上述多个金属化层的电阻，通过这些金属化层电力必须传至该芯片的另一面。
为了降低此馈孔(feedthrough)电阻，可使用另一方法被称为后导孔(via-last)工艺。在此方法中，上述多个金属化层先形成于该基板之上，然后形成穿硅导孔(TSV)延伸穿透该基板和上述多个金属化层。此方法能允许一直线路径穿透该芯片，从上述多个金属化层而并无增加额外的电阻。然而，为降低电阻从芯片的一面至另一面(以及至另一裸片)，此一穿硅导孔(TSV)也增加至有源元件位于该芯片上的电阻，由于任一电力信号必须沿着此后导孔(via-last)工艺的TSV传递穿越该半导体芯片，并且接着传递回来穿越上述多个金属化层已抵达该有源元件。
有鉴于此，业界亟需一种系统及方法，能降低馈孔(feedthrough)电阻而不会增加连接至有源元件的连线电阻。
发明内容
上述所揭示及其他的问题可通过本发明实施例而获得解决及避免，并且能达成技术上的优点，本发明实施例提供于系统级封装中具有穿硅导孔(TSV)的一混成结构。
根据本发明的一实施例，一种半导体装置包括一基板具有一第一面和对向于第一面的一第二面以及一第一导电区域位于该基板的第一面上。一第一导电孔自该基板的第二面延伸至该第一导电区域，而未延伸穿越该第一导电区域；以及一第二导电孔自该基板的第二面延伸穿越该导电区域。
根据本发明另一实施例，一种半导体装置包括一第一半导体芯片包括一第一基板以及一第一金属化区域，该第一基板包括一第一面和一第二面。一第一导电孔自该第一基板的第二面延伸至该第一基板的第一面并且终止于该第一金属化区域。一第二导电孔延伸穿越该第一半导体芯片。
根据本发明又一实施例，一种半导体装置的制造方法包括提供一第一基板及形成一第一导电孔穿越该第一基板。一第一导电区域形成于该第一基板之上，以及形成一第二导电孔延伸穿越该第一基板与该第一导电区域。
本发明所述实施例的优点为，其提供一低电阻路径通过一先导孔工艺的穿硅导孔(via-first TSV)以供相邻芯片连线，而也提供一馈孔(feedthrough)通道，通过一后导孔工艺的穿硅导孔(via-last TSV)以供多重芯片之间的连线。通过提供不同的穿硅导孔(TSV)精确地视实际TSV的使用而定，能降低整体的连线电阻。
为使本发明能更明显易懂，下文特举实施例，并配合附图，作详细说明如下：
附图说明
图1显示根据本发明的实施例于形成先导孔工艺的穿硅导孔(via-firstTSV)的初始步骤的剖面示意图。
图2显示根据本发明的实施例在形成金属化层于该层间介电层、该基板和先导孔工艺的穿硅导孔(via-first TSV)的剖面示意图。
图3显示根据本发明的实施例在形成后导孔工艺的穿硅导孔(via-lastTSV)的剖面示意图。
图4显示根据本发明的实施例将该基板薄化以露出该先导孔工艺的穿硅导孔(via-first TSV)103和后导孔工艺的穿硅导孔(via-last TSV)301，而形成via-first TSV 401和via-last TSV 403的剖面示意图。
图5显示根据本发明的一实施例，通过使用上述对应图1～图4的工艺所形成的第一芯片501，与一封装基板503、一第二芯片505和第三芯片507集成化至系统级封装(SiP)构造的剖面示意图。
【主要附图标记说明】
101～基板；
102～有源元件；
103～先导孔工艺的穿硅导孔(via-first TSV)；
104～层间介电层；
105～基板的第一面；
107～基板的第二面；
201～金属化层；
203～接触垫；
301～后导孔工艺的穿硅导孔(via-last TSV)；
401～先导孔工艺的(via-first TSV)；
403～先导孔工艺的(via-last TSV)；
405～导电层；
407～ENIG层；
501～第一芯片；
503～封装基板；
505～第二芯片；
507～第三芯片；
509～接触凸块；
511、513、515、517～圈出区域。
具体实施方式
以下以各实施例详细说明并伴随着附图说明的范例，做为本发明的参考依据。在附图或说明书描述中，相似或相同的部分皆使用相同的附图标记。且在附图中，实施例的形状或是厚度可扩大，并以简化或是方便标示。再者，图式中各元件的部分将以分别描述说明之，值得注意的是，图中未示出或描述的元件，为所属技术领域普通技术人员所知的形式，另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
本发明的实施例以特定的内容所揭示，即以三维系统级封装(SiP)构造为例，其具有先导孔工艺的穿硅导孔(via-first TSV)及后导孔工艺的穿硅导孔(via-last TSV)的混成结构。然而，本发明也可应用于其他形式的电性连接。
请参阅图1，其显示一基板101具有有源元件102和一层间介电层(interlayer dielectric，简称ILD)104。该基板具有一第一面105和对向于第一面105的一第二面107以及一先导孔工艺的穿硅导孔(via-first TSV)103形成于其中。该基板可包括硅块材、掺杂或未掺杂、或一有源层于绝缘层上有硅(silicon-on-insulator，简称SOI)基板。一般而言，一SOI基板包括一半导体材料层，例如硅、锗、硅锗、SOI、绝缘层上有硅锗(SGOI)、或上述材料的组合。可使用的其他基板包括多层基板、渐层基板、或混合位向基板。
在图1中所显示的有源元件102为两个晶体管。然而，本发明所属技术领域普通技术人员应可理解广泛的各种类型的元件例如电容、电阻、电感、high-k金属栅极元件、以及其他等同类型的元件，可用以产生所欲的结构上及功能上的设计需求。所述有源元件102可利用适当的方法形成于该基板101的表面上或形成于该基板101中。
该层间介电层104形成于基板101和有源元件102上，通过化学气相沉积法、溅镀法、或其他任何已知及已使用于本技术领域中用以形成ILD 104的方法。典型的层间介电层104具有一平坦化的表面，以及可包括氧化硅，然而也可选用其他材料，例如high-k或low-k材料。该层间介电层104可选择地形成以致施予一应变于有源元件102内的基板101，如同本技术领域所周知，此将可增加有源元件102的整体性能。
可形成一先导孔工艺的穿硅导孔(via-first TSV)103，通过先将一适合的光致抗蚀剂(未显示)进行涂布并显影步骤，接着蚀刻该层间介电层104与基板101以形成一开口。在此阶段所形成的开口需延伸进入该基板101，至少甚于该有源元件102，并且抵达一深度至少大于最终所欲完成的基板101的厚度。而此深度为依赖该基板101的整体设计而定，因此，此深度可自该基板101的表面深入大约1微米(μm)至大约700微米之间，例如大约50微米。所形成的该开口具有一直径大约介于1微米至100微米之间，例如大约6微米。
一旦已形成此开口，可将该开口填入一阻障层及一导电材料以形成先导孔工艺的穿硅导孔(via-first TSV)103。该阻障层可包括一导电材料，例如氮化钛，虽然也可替换使用其他材料，例如氮化钽、钛、介电材料、或类似材料。该阻障层可通过使用一化学气相沉积法(CVD)形成，例如等离子体辅助化学气相沉积法(PECVD)。然而，也可选择使用其他可替代的方法，例如溅镀法或有机金属化学气相沉积法(MOCVD)。该阻障层可形成以顺应下方的开口的形状，该开口用于先导孔工艺的穿硅导孔(via-first TSV)103。
该导电材料可包括铜，虽然也可替代其他适合的材料，例如铝、合金、掺杂多晶硅、上述材料的组合、或其他类似的材料。形成该导电材料可通过先沉积一晶种层，接着电镀铜于该晶种层上，填入且溢满该开口，其用于先导孔工艺的穿硅导孔(via-first TSV)103。一旦导电材料已填入用于先导孔工艺的穿硅导孔(via-first TSV)103的开口中，在用于先导孔工艺的穿硅导孔(via-first TSV)103的开口外部多余的阻障层和多余的导电层，通过一研磨工艺被移除，例如化学机械研磨法(CMP)，虽然也可使用其他适合的移除工艺。
图2显示形成金属化层201于该层间介电层104、该基板101和先导孔工艺的穿硅导孔(via-first TSV)103的剖面示意图。上述多个金属化层201形成于该基板101、有源元件102、层间介电层104、和先导孔工艺的穿硅导孔103之上，并且设计以连接各种不同的有源元件102以形成功能性电路。形成上述多个金属化层201是以介电材料和导电材料的交错叠层形式，并且可利用任何适当的工艺(例如沉积、镶嵌、双镶嵌等)。在一实施例中，至少有四层金属化层分别由ILD层104与基板101隔离，然而，金属化层201确实数目至少部分依据该半导体芯片的整体设计而定。
将接触垫203形成于上述多个金属化层201的最上层中，以提供自电路(包括有源元件102和金属化层201)至其他装置(例如其他半导体芯片，如以下图5所述)的连接。上述多个接触垫203可包括铝，并且可通过顺应性地沉积一铝层，以致接触从上述多个金属化层201的低层的一连线。
图3显示根据本发明实施例的形成后导孔工艺的穿硅导孔(via-last TSV)的剖面示意图。该后导孔工艺的穿硅导孔(via-last TSV)301可通过涂布及显影一适合的光致抗蚀剂(未示出)，接着蚀刻上述多个金属化层201、上述多个ILD层104和至少一部分的基板101而形成。该后导孔工艺的穿硅导孔(via-last TSV)301的形成步骤，相似于先导孔工艺的穿硅导孔(via-first TSV)103的形成步骤，使导孔延伸进入该基板101中至少超过该有源元件102，以至一深度大于所欲的该基板的最终高度。有鉴于此，而此深度为依赖该基板101的整体设计而定，因此，此深度可自该基板101的表面深入大约1微米(μm)至大约700微米之间，例如大约50微米。所形成的该开口具有一直径大约介于1微米至100微米之间，例如大约6微米。
可选择地，也可形成后导孔工艺的接触垫(未示出)于该后导孔工艺的穿硅导孔(via-last TSV)301上，以提供一外部连接至其他装置。上述多个后导孔工艺的接触垫可通过与接触垫203相类似的形式和相似的材料形成，如以上图2中所描述。然而，其他任何适当的材料及方法以可用以替换形成上述多个后导孔工艺的接触垫。
图4显示将该基板101薄化以露出该先导孔工艺的穿硅导孔(via-firstTSV)103和后导孔工艺的穿硅导孔(via-last TSV)301，而形成via-first TSV401和via-last TSV 403。为了薄化该基板101，将该基板101的第二面107的部分移除，以露出位于先导孔工艺的穿硅导孔103和后导孔工艺的穿硅导孔301内的导电材料。此移除步骤可通过一研磨工艺实施，例如一化学机械研磨(CMP)，虽然，也可选择使用其他适合的替代方法，例如蚀刻法。
然而，作为本发明所属技术领域普通技术人员应可了解的是，上述形成via-first TSV 401和via-last TSV 403的方法仅仅是用以说明的实施例，并非限定于这些实施例。也可选择使用其他适合的替代方法。例如，用于先导孔工艺的穿硅导孔(via-first TSV)103和后导孔工艺的穿硅导孔(via-last TSV)301可填入介电材料，直至该基板101的第二面107薄化完成后，在此阶段可将介电材料移除并且取代以导电材料。此实施例以及其他适合的实施例可替代以用于形成via-first TSV 401和via-last TSV 403。
在移除部分的该基板101的第二面107之后，可实施一清洗蚀刻步骤。此清洗蚀刻步骤意欲清洗并抛光于CMP步骤之后的该基板101。此外，此清洗蚀刻步骤也可帮助应力释放，此应力是在CMP工艺时研磨基板101生成。此清洗蚀刻步骤可使用HNO3，然而也可选择使用其他适合的替代蚀刻液。
再者，在清洗步骤以移除任何残留的研磨残留物，例如氧化铜之后，可形成一导电层405于该基板101的第二面107上形成一电性连接至该via-firstTSV 401和via-last TSV 403。该导电层405可包括铝，并且可通过一溅镀沉积工艺形成。然而，也可替代使用其他材料，例如镍和铜，以及其他形成方法，例如电镀法或无电镀法。所形成的该导电层405的厚度范围可介于大约1微米(μm)至大约3微米之间，例如大约2微米。
在形成导电层405之后可接续一无电镀镍金(Electroless Nickel Gold，简称ENIG)工艺以形成一无电镀镍金层407，从该基板101相对于该导电层405。该ENIG工艺提供一均匀的金属表面，供形成接触从该基板101至其他装置(详细描述于以下图5中)。该ENIG工艺可包括清洁该导电层405，浸润该基板101于一锌酸盐活化溶液中，无电镀一镍层于该导电层405上，无电镀一金层于该镍层上。所形成的该ENIG层407的厚度范围可介于大约2微米至大约4微米之间，例如大约3微米。一旦形成，可将该导电层405和该ENIG层407图案化，通过一适当的黄光光刻工艺，并且移除不想要的材料通过适当的蚀刻步骤如图4所示。
应注意的是，上述导电层405和ENIG层407仅仅是一具潜力的工艺，可用于薄化的该基板101的第二面107。另择一地，可将该基板101的第二面107形成一凹入，使得该via-first TSV 401和via-last TSV 403自该基板101的第二面107的表面延伸远离。另外，可形成一保护层以保护该via-first TSV401和via-last TSV 403，或者形成重置层或者其他形式的适当的连线，替代地形成于该基板101的第二面107上。
图5显示本发明的一实施例，通过使用上述对应图1～图4的工艺所形成的第一芯片501，与一封装基板503、一第二芯片505和第三芯片507集成化至一SiP构造中。该封装基板503提供一输出/输入(简称I/O)、电力及通过接触凸块509将该via-first TSV 401和via-last TSV 403连接接地。该封装基板503可以是印刷电路板(简称PCB)、IC封装、或者其他基板，其可用于封装具传输信号、电力及将该第一芯片501、第二芯片505和第三芯片507接地。
所述接触凸块509可包括一材料，例如锡，或其他适合的材料例如银、无铅锡、或铜。在一实施例中，该接触凸块509为焊锡凸块。该接触凸块509的形成方式最初是以形成一锡层，通过常用的方法例如蒸镀法、电镀法、印刷法、焊锡转移法、锡球置入法(ball placement)等，直至一厚度大约100微米。一旦一锡层已形成于所述结构上，施以一回焊步骤以将该材料定型成为所欲的凸块形状。
该第二芯片505和第三芯片507以可通过相似于第一芯片501的方法形成，如上述对应图1～图4所述。例如，在此实施例中该第二芯片505和第三芯片507皆包括via-first TSV 401、via-last TSV 403和接触垫203。再者，该via-first TSV 401和via-last TSV 403的确切数目、设置及位置必须至少部分地依据该SiP的整体设计而定，将该via-first TSV 401设置以提供连接至一接触垫203(如第一圈区域511所图示)或者一邻近芯片的via-last TSV 403(如第二圈区域513所图示)。另外，将该via-last TSV 403设置以提供连接至一接触垫203(如第三圈区域515所图示)或者一邻近芯片的via-last TSV 403(如第四圈区域517所图示)。
然而，如本发明所属技术领域的普通技术人员应可了解的是，仍有许多结合可用于连线任意数目适合的芯片，并且上述实施例并非意欲限定本发明。也可使用任何适当的芯片的结合(具有任意数目的via-first TSV 401和via-last TSV 403提供电力和信号路径，此数目也包括零)，仍不脱离本发明的精神和范围，以及所有的这些结合完全涵括于本发明的范围内。此外，可形成或设置重置层(redistribution layer)和插入件(interposer，未示出)，以确保该第一芯片501、第二芯片505和第三芯片507之间的连接(例如导电层405和ENIG层407)具适当的对准。
通过使用via-first TSV 401和via-last TSV 403的结合，可兼具有via-firstTSV 401和via-last TSV 403的优点，以提供一低电阻路径供相邻芯片连接通过一via-first TSV 401，而也提供一馈孔(feedthrough)通道，通过一via-lastTSV 403以供多重芯片之间的连线。通过提供不同的穿硅导孔(TSV)精确地视实际TSV的使用而定，能降低整体的连线电阻。
例如，在一系统级封装(SiP)的第三芯片507内，如图5中所示包括via-firstTSV 401和via-last TSV 403二者，自该封装基板503至上述多个有源元件102的一的连线路径的电阻，可通过以下公式1计算得：
连线电阻＝R’+(n-1)R”(式1)
其中：
n为芯片的数目；
R为各芯片中金属化层的电阻；
R’为各芯片中via-first TSV的电阻；
R”为各芯片中via-last TSV的电阻。
换言之，在第三芯片507上的有源元件102之一的电阻路径为第三芯片507内的via-first TSV 401的电阻及两个via-last TSV 403的电阻总和，此via-last TSV 403为延伸穿透第一芯片501和第二芯片505。
相较于标准的先前技术，其仅通过via-first TSV 401或via-last TSV 403之一，提供连线至位于第三芯片507上的上述多个有源元件102之一，上述实施例针对三维系统级封装(3D SiP)构造提供了更有效的成本解决方案。在仅仅具有via-first TSV 401的案例中，为达到位于第三芯片507上的有源元件102，该电阻路径可包括该第一芯片501的via-first TSV 401、该第一芯片501的金属化层201、该第二芯片505的via-first TSV 401、该第二芯片505的金属化层201、和该第三芯片507的via-first TSV 401的电阻，总结于公式2中：
Via-First TSV电阻＝(n+1)R+nR’(式2)
在仅仅具有via-last TSV 403的案例中，为达到位于第三芯片507上的有源元件102之一，该电阻路径可包括通过各个第一芯片501的via-last TSV403的电阻，及该第三芯片507的金属化层201的电阻总和，总结于公式3中：
Via-Last TSV电阻＝R+nR”(式3)
虽然本发明及其优点已于上述实施例中详细公开，应了解的是可进行各种变化、取代或替换而不脱离本发明所主张请求保护专利的精神和范围。例如，各种不同via-first TSV和via-last TSV的结合应可用于将分离的芯片连接在一起。在另一例中，任何数目的方法皆可替换地使用于形成via-first TSV401和via-last TSV。
本发明虽以各种实施例公开如上，然其并非用以限定本发明的范围，任何所属技术领域的普通技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰。本发明的保护范围当视所附的权利要求的范围为准。

Claims (9)

1.一种半导体装置，包括：
一第一基板；
一第一多层介电层，位于所述第一基板的第一侧上；
一第一导孔延伸穿越该第一基板及该第一多层介电层的一层或多层；以及
一层或多层第一导电层，位于所述第一基板的所述第一侧上并且位于第一导孔之上；
一第二导孔延伸穿越该第一基板及该第一多层介电层的两层或多层和所述一层或多层第一导电层，该第二导孔所穿越的该第一多层介电层的介电层数多于该第一导孔所穿越的该第一多层介电层的介电层数；
一第二基板；
一第二多层介电层，位于所述第二基板的第一侧；
一第三导孔延伸穿越该第二基板及该第二多层介电层的一层或多层，其中，该第三导孔电性连接至该第一导孔，此乃通过位于该第一多层介电层中的金属化层连接；
一层或多层第二导电层，位于第三导孔之上；以及
一第四导孔延伸穿越该第二基板及该第二多层介电层的两层或多层和所述一层或多层第二导电层，该第四导孔所穿越的该第二多层介电层的介电层数多于该第三导孔所穿越的该第二多层介电层的介电层数，其中该第四导孔电性连接至该第二导孔。
2.根据权利要求1所述的半导体装置，还包括：
一有源元件位于所述第一基板的所述第一侧上且位于所述第一多层介电层中与所述第一基板最邻近的介电层之下；以及
多个金属化层设置于该有源元件之上，其中最接近该第一基板的一第一金属化层电性连接该第一导孔与该有源元件，所述多个金属化层是由所述一层或多层第一导电层和所述第一多层介电层的部分层以交错叠层形式形成的。
3.根据权利要求2所述的半导体装置，还包括一导电层相对于该有源元件位于该第一基板相对侧，该导电层与该第一导孔电性连接。
4.一种半导体装置，包括：
一第一半导体芯片包括一第一基板、位于该第一基板的第一侧之上的第一介电层以及位于所述第一介电层上的第一金属化层；
一第一导电孔延伸穿越该半导体芯片；以及
一第二导电孔延伸部分地穿越该第一半导体芯片，其中包括延伸穿越所述第一介电层和所述第一基板，
其中，所述第一金属化层位于第二导电孔之上，并且所述第一导电孔延伸穿越该半导体芯片包括所述第一导电孔延伸穿越所述第一金属化层和所述第一介电层和所述第一基板；
一第二半导体芯片包括一第二基板，位于所述第二基板的第一侧上的第二介电层以及位于所述第二介电层上的第二金属化层；
一第三导电孔延伸穿越所述第二半导体芯片；以及
一第四导电孔延伸部分地穿越所述第二半导体芯片，其中，该第四导电孔延伸穿越所述第二基板和所述第二介电层，并且该第四导电孔通过所述第一半导体芯片的第一金属化层电性连接至所述第二导电孔，
其中，所述第二金属化层位于第四导电孔之上，所述第三导电孔延伸穿越所述第二半导体芯片包括所述第三导电孔延伸穿越所述第二金属化层和所述第二基板。
5.根据权利要求4所述的半导体装置，其中，所述第一金属化层以介电材料和导电材料的交错叠层形式形成。
6.根据权利要求4所述的半导体装置，还包括一有源元件位于该第一基板的所述第一侧上且所述介电层下，其中该有源元件通过一金属化层与该第二导电孔电性连接。
7.一种半导体装置的制造方法，包括：
提供一第一基板；
形成一层或多层第一介电层于该第一基板的第一侧之上；
形成一第一导电孔延伸穿越该第一基板及所述一层或多层第一介电层；
形成多层第二介电层以及一层或多层第一导电层于所述一层或多层第一介电层和该第一基板之上；以及
形成一第二导电孔延伸穿越该第一基板、所述一层或多层第一介电层、及该多层第二介电层和该一层或多层第一导电层；
提供一第二基板；
形成多层第三介电层于所述第二基板的第一侧之上；
形成一第三导电孔延伸穿越所述第二基板及所述多层第三介电层的两层或多层，其中，所述第三导电孔电性连接至该第一导电孔，此乃通过位于该第一多层介电层中的金属化层连接；
形成一层或多层第二导电层于所述第三导电孔之上；以及，
形成一第四导电孔延伸穿越该第二基板及所述多层第三介电层的两层或多层和所述一层或多层第二导电层，所述第四导电孔所穿越的第三介电层的介电层数多于所述第三导电孔所穿越的第三介电层的介电层数，其中该第四导电孔电性连接至该第二导电孔。
8.根据权利要求7所述的半导体装置的制造方法，还包括：
形成一有源元件位于该第一基板上且位于第一介电层之下；以及
形成一第一金属化层于该有源元件之上，该第一金属化层电性连接该第一导电孔与该有源元件，其中第一金属化层由第二介电层和导电层以交错叠层形式形成。
9.根据权利要求7所述的半导体装置的制造方法，其中所述形成该第一导电孔的步骤还包括：
形成一开口于该基底的一第一面上；
将一导电材料填入该开口中；以及
薄化该基板的一第二面，相对于该第一面，以露出该导电材料。
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