CN103311202B - 集成电路的引线接合结构 - Google Patents

集成电路的引线接合结构 Download PDF

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Publication number
CN103311202B
CN103311202B CN201210209937.0A CN201210209937A CN103311202B CN 103311202 B CN103311202 B CN 103311202B CN 201210209937 A CN201210209937 A CN 201210209937A CN 103311202 B CN103311202 B CN 103311202B
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bond pad
pad
layer
protective layer
passivation layer
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CN103311202A (zh
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余振华
李明机
李建勋
陈永庆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件包括衬底、衬底上方的焊盘。保护层设置在接合焊盘上方。保护层和接合焊盘包括不同的材料。接合焊球设置在保护层上方。接合引线连接至焊球。本发明还提供了集成电路的引线接合结构。

Description

集成电路的引线接合结构
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件。
背景技术
集成电路(IC)芯片通常通过引线电连接(例如，金线或铜线)至封装组件中的封装衬底以提供外部信号交换。这种引线通常利用热压和/或超声波振动接合于IC芯片上形成的接合焊盘。引线接合工艺施加热和机械应力。应力施加在接合焊盘上，并且传递至位于接合焊盘下方的层和结构。接合焊盘的结构需要能够承受应力以确保引线接合的质量。
目前，许多工艺在金属层间介电(IMD)层中使用低k和超低k介电材料以减少RC延迟和寄生电容。IMD设计的一般趋势是IMD层的介电常数(k值)趋于从低k状态(regime)减小至超低k状态。这意味着形成金属线和通孔的IMD层机械易碎。此外，IMD层在引线接合力施加的应力下可能分层。因此，对接合工艺的成品率产生不利影响。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种器件，包括：衬底；接合焊盘，位于所述衬底上方；保护层，位于所述接合焊盘上方，其中，所述保护层和所述接合焊盘包含不同的材料；接合焊球，设置在所述保护层上方；以及接合引线，连接至所述接合焊球。
在该器件中，所述接合焊盘包括铝和铜，并且所述保护层包括金层以及位于所述金层上方的镍层。
在该器件中，所述接合焊球与所述镍层接触，并且所述金层与所述接合焊盘接触。
该器件还包括：第一钝化层，包括位于所述接合焊盘的一部分下方的部分；以及第二钝化层，位于所述第一钝化层上方，其中，所述第二钝化层覆盖所述接合焊盘的边缘部分。
在该器件中，所述保护层覆盖所述接合焊盘的整体，并且在所述第二钝化层的一部分下方延伸且与该部分对准。
在该器件中，所述保护层进一步在所述接合焊盘的侧壁上延伸。
在该器件中，所述保护层设置在所述第二钝化层的开口中，并且基本上没有位于所述第二钝化层下方的部分。
根据本发明的另一方面，提供了一种器件，包括：半导体衬底；焊盘，包括铝和铜且位于所述半导体衬底上方；第一钝化层，包括位于所述焊盘的边缘部分下方的部分；第二钝化层，包括位于所述焊盘的边缘部分上方的部分；保护层，位于所述焊盘上方并与所述焊盘接触，其中，所述保护层包括金层以及位于所述金层上方的镍层；接合焊球，接合至所述保护层；以及接合引线，连接至所述接合焊球，其中，所述接合引线电连接所述焊盘。
在该器件中，所述保护层还包括位于所述金层和所述镍层之间的钯层。
在该器件中，所述焊盘位于对应管芯的输入/输出区域中。
在该器件中，没有有源电路位于所述焊盘下方并与所述焊盘对准。
该器件还包括位于所述焊盘下方并与所述焊盘对准的双实心焊盘。
在该器件中，所述接合焊球与所述镍层接触。
根据本发明的又一方面，提供了一种器件，包括：半导体衬底；焊盘，包括铝和铜并位于所述半导体衬底上方；第一钝化层，包括位于所述焊盘的边缘部分下方的部分；第二钝化层，包括位于所述焊盘的边缘部分上方的部分；保护层，位于所述焊盘上方，其中，所述保护层的硬度大于所述焊盘的硬度；接合焊球，接合在所述保护层上；以及接合引线，附接至所述接合焊球。
在该器件中，所述保护层包括金层以及位于所述金层上方的镍层。
在该器件中，所述保护层还包括位于所述金层与所述镍层之间的钯层。
在该器件中，所述保护层设置在所述第二钝化层的开口中，并且基本上没有位于所述第二钝化层下方并与所述第二钝化层对准的部分。
该器件还包括位于所述焊盘下方并与所述焊盘连接的双实心金属焊盘。
在该器件中，所述接合焊球包括堆叠凸块。
附图说明
为了更完整地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考：
图1是根据一些示例性实施例的管芯的截面图，其中，管芯包括引线接合结构(其包括接合焊盘和接合焊盘上方的保护层)；以及
图2至图4是根据可选实施例的管芯的截面图。
具体实施方式
下面详细讨论本公开内容的实施例的制造和使用。然而，应该理解，实施例提供许多可以在各种具体环境中实现的具体化的可应用的发明原理。讨论的具体实施例是说明性的，且不限制本公开内容的范围。
根据各个示例性实施例提供了引线接合结构。讨论了实施例的变型例。在全部附图和说明性的实施例中，相同的参考符号用于指定相同的元件。
图1示出了根据一些实施例的管芯100的截面图。管芯100包括衬底20以及在衬底20的顶面处形成的有源电路22。在一些实施例中，衬底20是可以由硅、硅锗等形成的半导体衬底。有源电路22可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器等。所示管芯100的区域24可以是输入/输出(I/O)区域。因此，有源电路22可以是I/O电路。在可选实施例中，在所示区域24中没有形成有源电路。然而，仍然可以在管芯100的其它区域中形成有源电路。
互连结构30形成在区域24中，并且包括位于有源电路22上方并与有源电路22对准的部分。互连结构30包括金属线34和通孔36，用于互连有源电路22的不同部分并将有源电路22连接至上面的接合焊盘50。互连结构30包括在其中形成金属线34和通孔36的介电层32。在通篇描述中，位于相同层的金属线34统称为金属层。在一些实施例中，介电层32是低k介电层，其可以具有大约低于3.0或在大约2.0和2.8之间的介电常数(k值)。金属线34和通孔36可以由铜或铜合金形成。在一些实施例中，金属线34和通孔36具有电连接功能，并且可以使电流/信号流过其中。在可选实施例中，金属线34和通孔36是伪连接件(不用作电连接件)。因此，当管芯100通电时，伪金属线34和伪通孔36中没有流过电流。
互连结构30包括其中形成金属焊盘38和40的顶部介电层，并且顶部介电层可以由未掺杂硅玻璃或低k介电材料形成。在一些实施例中，在称作层Mtop和Mtop-1的互连结构30的2个顶部金属层中，形成双实心焊盘44。双实心焊盘44包括Mtop焊盘40、Mtop-1焊盘38以及连接焊盘40和38的多个通孔42。Mtop焊盘40、Mtop-1焊盘38以及通孔42可以由铜、钨或其它金属形成，并且可以使用双镶嵌工艺或单镶嵌工艺形成。可选地，可以通过沉积金属层并蚀刻金属层来形成Mtop焊盘40和Mtop-1焊盘38。
在一些实施例中，双实心焊盘44与上面的接合焊盘50物理接触。在可选实施例中，双实心焊盘44可以通过通孔(未示出)电连接至接合焊盘50。在又一个可选实施例中，代替形成双实心焊盘44，可以在接合焊盘50下方形成位于Mtop层中的单个焊盘。
在衬底20以及还在互连结构30上方形成钝化层46和48。钝化层46和48在本领域中分别称作钝化-1和钝化-2，并且可以由诸如氧化硅、氮化硅、未掺杂硅玻璃(USG)和/或其多层的材料形成。在一些实施例中，在与钝化层46的一部分相同的层中形成接合焊盘50。接合焊盘50的边缘部分形成在钝化层46的一部分上方并与该部分对准。接合焊盘50可以包括钝化层48中的一部分，并且通过钝化层48中的开口53暴露该接合焊盘。接合焊盘50的一些边缘部分可以被钝化层48的一部分覆盖。接合焊盘50可以由诸如铝、铜、银、金、镍、钨、其合金和/或其多层的金属材料形成。在一些实施例中，接合焊盘50由铝铜形成。在一些示例性实施例中，接合焊盘50中铝和铜的体积百分比可以分别是大约99.5％和大约0.5％。在其它示例性实施例中，接合焊盘50包括铝、硅和铜。含硅的铝铜中的铝、硅和铜的体积百分比分别是大约97.5％、大约2％以及大约0.5％。接合焊盘50可以通过双实心焊盘44或其它互连件电连接至有源电路22。例如，接合焊盘50的厚度可以在大约与大约之间。
保护层52在接合焊盘50的顶面上方形成。保护层52可以是单层，或者可以是包含多层的复合层。在一些实施例中，保护层52包括金层52A和金层52A上方的镍层52B。金层52A可以与接合焊盘50接触。保护层52可以是由浸渍形成的化学镀镍浸金(ENIG)。在可选实施例中，保护层可以包括化学镀镍/钯浸金(ENEPIG)，其包括接合焊盘50上方的金层、金层上方的钯层以及钯层上方的镍层。保护层52的形成方法包括电镀、化学镀、浸渍、物理汽相沉积(PVD)及它们的组合。保护层52的硬度可以大于接合焊盘50的硬度。
在管芯100的引线接合工艺期间，进行引线接合以将管芯100电连接至另一封装部件(未示出)，例如，封装衬底、引线框等。通过引线接合至接合焊盘50进行接合。对应的引线接合包括接合焊球56(本领域还称为凸块柱)和连接引线58，其中接合焊球56的直径大于引线58的直径。接合焊球56和引线58可以由金、铜、铝等形成。通过接合焊球56，接合引线58电连接接合焊盘50，并且进一步电连接至下面的有源电路22。引线接合可以是前向的引线接合、反向的引线接合(reversewirebonding)、堆叠凸块接合(例如，图4)等。引线58的直径可以在大约0.5mil与大约2.0mil之间。
保护层52可以根据各个实施例而具有各种形式。参照图1，保护层52在接合焊盘50的整个顶面上方形成并与接合焊盘50的整个顶面对准。在可选实施例中，如图2所示，保护层52形成在钝化层48的开口53中，并且不在钝化层48的下面延伸。在又一个实施例中，如图3所示，保护层52在接合焊盘50的整个顶面上方形成且与接合焊盘50的整个顶面对准，并且还在接合焊盘50的侧壁上进一步延伸。这些实施例中的保护层52还延伸到钝化层48的部分下方并与钝化层48的部分重叠。
在实施例中，保护层52的硬度可以高于接合焊盘50的硬度，因此可以帮助使接合工艺中产生的应力散布至更大的芯片区域。没有保护层，接合焊盘50将向诸如低k介电层的下层结构传递更大的应力。因此通过使用实施例改善了引线接合工艺的成品率。
根据实施例，一种器件包括衬底、以及衬底上方的焊盘。保护层设置在接合焊盘上方。保护层和接合焊盘包括不同的材料。焊球设置在保护层上。接合引线连接至接合焊球。
根据其它实施例，一种器件包括半导体衬底、半导体衬底上方的铝铜焊盘、以及第一钝化层和第二钝化层。第一钝化层包括铝铜焊盘的边缘部分下方的部分。第二钝化层包括铝铜焊盘的边缘部分上方的部分。保护层设置在铝铜焊盘上方且与铝铜焊盘接触。保护层包括金层、以及金层上方的镍层。接合焊球接合至保护层。接合引线连接至接合焊球，其中，接合引线电连接至铝铜焊盘。
根据又一个实施例，一种器件包括半导体衬底、半导体衬底上方的铝铜焊盘、以及第一钝化层和第二钝化层。第一钝化层包括铝铜焊盘的边缘部分下方的部分。第二钝化层包括铝铜焊盘的边缘部分上方的部分。保护层设置在铝铜焊盘上方。保护层的硬度大于铝铜焊盘硬度。接合焊球接合至保护层上。接合引线附接至接合焊球。
尽管已经详细描述实施例及其优点，但是应该理解，在不背离通过所附权利要求所限定的实施例的精神和范围内本文可以进行各种改变、替换、和改进。此外，本申请的范围不旨在限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应该理解，通过本公开内容，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (17)

1.一种集成电路器件，包括：
衬底；
双实心焊盘，位于所述衬底中；
接合焊盘，位于所述衬底上方，且位于所述双实心焊盘的上方，还与所述双实心焊盘对准；
第一钝化层，包括位于所述接合焊盘的一部分下方的部分，且未完全覆盖所述双实心焊盘；
保护层，位于所述接合焊盘上方，其中，所述保护层和所述接合焊盘包含不同的材料；
接合焊球，设置在所述保护层上方；以及
接合引线，连接至所述接合焊球。
2.根据权利要求1所述的器件，其中，所述接合焊盘包括铝和铜，并且所述保护层包括金层以及位于所述金层上方的镍层。
3.根据权利要求2所述的器件，其中，所述接合焊球与所述镍层接触，并且所述金层与所述接合焊盘接触。
4.根据权利要求1所述的器件，还包括：第一钝化层，包括位于所述接合焊盘的一部分下方的部分；以及
第二钝化层，位于所述第一钝化层上方，其中，所述第二钝化层覆盖所述接合焊盘的边缘部分。
5.根据权利要求4所述的器件，其中，所述保护层覆盖所述接合焊盘的整体，并且在所述第二钝化层的一部分下方延伸且与该部分对准。
6.根据权利要求5所述的器件，其中，所述保护层进一步在所述接合焊盘的侧壁上延伸。
7.根据权利要求4所述的器件，其中，所述保护层设置在所述第二钝化层的开口中，并且没有位于所述第二钝化层下方的部分。
8.一种集成电路器件，包括：
半导体衬底；
双实心焊盘，位于所述衬底中；
接合焊盘，包括铝和铜且位于所述半导体衬底上方，且位于所述双实心焊盘的上方，还与所述双实心焊盘对准；
第一钝化层，包括位于所述接合焊盘的边缘部分下方的部分，且未完全覆盖所述双实心焊盘；
第二钝化层，包括位于所述接合焊盘的边缘部分上方的部分；
保护层，位于所述接合焊盘上方并与所述接合焊盘接触，其中，所述保护层包括金层以及位于所述金层上方的镍层；
接合焊球，接合至所述保护层；以及
接合引线，连接至所述接合焊球，其中，所述接合引线电连接所述接合焊盘。
9.根据权利要求8所述的器件，其中，所述保护层还包括位于所述金层和所述镍层之间的钯层。
10.根据权利要求8所述的器件，其中，所述接合焊盘位于对应管芯的输入/输出区域中。
11.根据权利要求8所述的器件，其中，没有有源电路位于所述接合焊盘下方并与所述接合焊盘对准。
12.根据权利要求8所述的器件，其中，所述接合焊球与所述镍层接触。
13.一种集成电路器件，包括：
半导体衬底；
双实心焊盘，位于所述衬底中；
接合焊盘，包括铝和铜并位于所述半导体衬底上方，且位于所述双实心焊盘的上方，还与所述双实心焊盘对准；
第一钝化层，包括位于所述接合焊盘的边缘部分下方的部分，且未完全覆盖所述双实心焊盘；
第二钝化层，包括位于所述接合焊盘的边缘部分上方的部分；
保护层，位于所述接合焊盘上方，其中，所述保护层的硬度大于所述接合焊盘的硬度；
接合焊球，接合在所述保护层上；以及
接合引线，附接至所述接合焊球。
14.根据权利要求13所述的器件，其中，所述保护层包括金层以及位于所述金层上方的镍层。
15.根据权利要求14所述的器件，其中，所述保护层还包括位于所述金层与所述镍层之间的钯层。
16.根据权利要求13所述的器件，其中，所述保护层设置在所述第二钝化层的开口中，并且没有位于所述第二钝化层下方并与所述第二钝化层对准的部分。
17.根据权利要求13所述的器件，其中，所述接合焊球包括堆叠凸块。
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