CN101207100A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN101207100A CN101207100A CNA2007103081886A CN200710308188A CN101207100A CN 101207100 A CN101207100 A CN 101207100A CN A2007103081886 A CNA2007103081886 A CN A2007103081886A CN 200710308188 A CN200710308188 A CN 200710308188A CN 101207100 A CN101207100 A CN 101207100A
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- electrode pad
- outside terminal
- container
- conducting liquid
- elongated vessel
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Abstract
本发明提供一种半导体器件,该半导体器件包括基板、设置于基板上的电极焊盘、设置于电极焊盘上的外部端子、从电极焊盘延伸入外部端子中的容器以及置于容器内部的导电液体。导电液体当暴露于空气时固化。当外部端子中形成裂纹时,该容器抑制裂纹的传播。而且,如果裂纹使容器破裂,则导电液体将填充裂纹从而最小化裂纹的进一步传播,并恢复在裂纹形成之前的外部端子的电阻特性。本发明还提供一种形成半导体器件的方法,该半导体器件包括具有导电液体的容器。
Description
技术领域
本发明涉及一种半导体芯片封装以及包含该封装的系统。更具体地,本发明涉及一种半导体封装以及包含该封装且该封装通过外部端子电连接和物理连接到电路板的系统。
背景技术
随着微电子工业持续开发越来越复杂的特征尺寸极小的器件,制造可靠的互联系统成为重要的挑战。常规方法用球栅阵列(BGA)结构将芯片封装附着到复合印刷电路板(PCB)上。在这种结构中,焊球提供芯片封装和PCB之间的电连接和物理连接。
将芯片封装耦合到PCB的工艺一般包括一个或多个温度周期,例如焊料回流步骤就是一个例子。同样,可靠性测试可以通过进行极端温度周期模拟所制成的器件的工作环境。在这些温度周期的过程中,芯片封装基板的热膨胀系数(CTE)与PCB的CTE之间的不匹配,导致在焊球的局部产生应力。所产生应力与芯片封装基板和PCB之间的CTE失配以及温度变化都成正比。因此,大的CTE差值以及大的温度变化致使在焊球局部产生大应力。这种局部应力能导致焊球中的裂纹。即使是小裂纹,也可能使焊球连接的电阻增大,这可对所制成的器件的可靠性造成不利影响。具体来说,当焊球中产生裂纹时,有效导电面积减小,因此连接电阻增大。但是,如果例如通过重复温度周期使得裂纹穿过焊球传播,则焊球连接可能完全失效,导致芯片封装与PCB之间的连接开路。
图1示出开裂的焊球3的显微图,其中焊球3位于具有结合焊盘4的半导体封装2和具有接触焊盘8的印刷电路板6之间。如图1所示,焊球连接内最有可能产生裂纹的点是焊球3与结合焊盘4或接触焊盘8耦合的某一拐角处。这在图1中以细节A和B表示。但是,裂纹也可能形成在焊球3的中部。同样在图1示出,在局部C处是沿焊球3的整个宽度方向传播的裂纹。局部A、B和C所示的裂纹可能导致焊球连接退化,焊球连接可靠性降低,和/或焊球连接完全失效,这些情况中的每一个都可能导致器件失效。
授予Oh等人的第6959856号美国专利(“Oh专利”)公开了一种使焊球中裂纹的传播最少化的方法,在Oh专利中,在焊料凸点中嵌入金属突出物。金属突出物用作阻碍裂纹传播的障碍。虽然Oh专利中的结构可减少裂纹传播以防止连接开路,但是它不能修补由于焊料凸点中的裂纹而导致的电阻增加。
因此,仍然需要一种最少化裂纹传播并且最小化由于裂纹导致的对焊球连接的电阻造成的不利影响的方法。
发明内容
本发明实施例提供一种半导体器件,该半导体器件包括基板、设置于基板上的电极焊盘、设置于电极焊盘上的外部端子、从电极焊盘延伸入外部端子中的容器以及设置于容器内部的导电液体。导电液体当暴露于空气时固化。当外部端子内形成裂纹时,该容器抑制裂纹的传播。另外,如果裂纹使容器破裂,则导电液体将填充裂纹,并且如果暴露于空气中,则导电液体将在在裂纹中固化。本发明还提供一种包含具有导电液体的容器的半导体器件的形成方法。
根据本发明的实施例,通过容器抑制外部端子内裂纹的传播。此外,如果裂纹使容器破裂,则来自容器的导电液体将填充裂纹,恢复连接的电阻特性。因此,与常规方法相比,根据本发明实施例的芯片封装与PCB之间的连接使可靠性得到提高。
附图说明
通过参考附图详细阐述本发明示意性实施例,本发明的上述以及其他特点和优点将更加显而易见,其中:
图1示出位于半导体芯片封装和印刷电路板之间开裂的焊球的显微图;
图2为根据本发明某些实施例的外部端子和细长容器的截面图;
图3为根据本发明某些实施例将半导体芯片封装接合到电路板的外部端子和细长容器的截面图;
图4为根据本发明某些实施例接合到电路板的半导体芯片封装的截面图;
图5为根据本发明某些实施例的外部端子和细长容器的截面图;
图6为根据本发明一实施例包含外部端子和多个突出物的半导体芯片封装的截面图;
图7为根据本发明某些实施例具有形成在电极焊盘上的细长容器的半导体芯片封装的截面图;
图8为根据本发明某些实施例具有形成在电极焊盘上且部分被填充的细长容器的半导体芯片封装的截面图;
图9为根据本发明某些实施例具有形成在电极焊盘上的细长容器和焊膏的半导体芯片封装的截面图;
图10为根据本发明某些实施例具有形成在电极焊盘上且插入外部电极中的细长容器的半导体芯片封装的截面图;
图11为根据本发明某些实施例通过含有裂纹的外部端子接合到电路板的半导体芯片封装的截面图。
具体实施方式
下文中将参考附图更全面地描述本发明,其中示出了本发明的多个实施例。但是本发明可以多种不同的形式实施,并且不能将其解释为仅限于这里说阐述的具体实施例。相反,这些实施例提供来使本发明详实和完整,以向所属领域的技术人员传达本发明的范围。在附图中,为清楚起见,层和区域的尺寸和相对尺寸可能被放大。
应理解,当一元件或层被称为在另一元件或层“上面”,“连接至”或“耦合至”另一元件或层时,它可以直接位于该另一元件或层的上面、连接至或耦合至该另一元件或层,或可能存在的中间元件或层。相反,当一元件被称作“直接”在另一元件或层“上面”、“直接连接至”或“直接耦合至”另一元件或层时,则不存在中间元件或层。全文中同样的标号表示同样的元件。如这里使用的术语“和/或”包括一个或多个所列举的相关项的任意组合或所有组合。
除非另外定义,这里使用的所有术语(包括技术术语和科技术语)与本发明所属领域的普通技术人员通常理解的含义相同。而且还应了解,比如通用字典所定义的术语,应将其解释为与它们在相关领域的背景中的含义一致,并且除非在此明确定义,否则不能将其进行理想化或过于正式形式化的解释。
图2为根据本发明某些实施例的外部端子和细长容器的截面图。
参见图2,根据本发明某些实施例的半导体芯片封装100包括半导体基板10、设置于基板10上的电极焊盘12、电极焊盘12上的外部端子20、设置于外部端子20内的细长容器22、以及位于容器22内部的导电液体24。基板10可包括钝化层14和绝缘层16。绝缘层16限定了暴露电极焊盘12的开口。绝缘层16可由诸如聚酰亚胺材料的有机材料或无机材料构成。
半导体芯片封装100可包括设置于电极焊盘12上的凸点下金属(UBM)18。包含UBM 18可改善外部端子20与电极焊盘12之间的润湿性。UBM 18可包含几个薄层,并且可包含Cu、Au、Ni、Cr和其合金中的一个或多个,可用本领域公知的常规方法形成。外部端子20可以是焊球、焊料凸点、导电球、导电凸点或任何用于将结合焊盘连接至接触焊盘的其他装置,如在本领域众所周知的那些。
容器22可以主要由外部端子20支撑,或者它也可以耦合至电极焊盘12、UBM18、和/或接触焊盘52(图3所示)。如下文进一步解释的,容器22的端部可部分地插入电极焊盘12的、接触焊盘52的或者二者的凹槽中。容器22的端部也可以嵌入在UBM 18内(未示出)。例如,如图2所示,容器22的端部可直接接触UBM 18的顶面。容器22可以具有大致为圆柱形的形状。或者,容器22还可以具有能容纳导电液体24的任何细长的形状,这包括但不局限于矩形中空形状和三角形中空形状。
导电液体24的部分24a可在细长容器22的一端或两端暴露于空气形成。导电液体24可包括如金属的导电材料并在暴露于空气时固化。因此,导电液体24的部分24a当暴露于空气时可固化,从而在容器22内密封其余的导电液体24。具体而言,导电液体24的部分24a当暴露于空气时可固化,但是容器22内其余的导电液体24将保持为液态,除非其暴露于空气。导电液体24可以是低粘度、可流动的材料,诸如金属膏、导电油墨、纳米金属溶胶。例如,导电液体24可以是如韩国专利第10-20070043484、10-20060011083以及10-20070043436所描述的导电油墨或纳米油墨材料,在此引用这些专利的内容作为参考。根据某些实施例,导电液体24的粘度可以是约10cps到约5000cps。为了形成具有合适粘度的导电液体,可在导电液体24中添加粘性材料。
图3为根据本发明某些实施例将半导体芯片封装接合到电路板的外部端子和细长容器的截面图。图4为根据本发明某些实施例接合到电路板的半导体芯片封装的截面图。
参照图3和图4,半导体芯片封装100通过外部端子20接合到电路板50。电路板50可以包括耦合至外部端子20的接触焊盘52。接触焊盘52可包含凹槽54,并且当电路板50接合到半导体芯片封装100时,细长容器22可以延伸入凹槽54。凹槽54可完全穿过接触焊盘52,或者它仅部分穿过接触焊盘52。具体来说,凹槽54可进入接触焊盘52中至预定深度。如图5所示,该预定深度可与容器22从外部端子20突出的量相一致。凹槽54可有助于将外部端子20与接触焊盘52对准,并可为容器22提供额外的机械支撑。而且,通过与凹槽54啮合,容器22可提供对剪切应力的抵抗力,这些剪切应力是由半导体芯片封装100和PCB 50施加到外部端子20的。接触焊盘52可由诸如如本领域所公知的金属的导电材料构成。
图5为根据本发明某些实施例的外部端子和细长容器的截面图。
图5的半导体芯片封装105与图2的半导体芯片封装类似,除了半导体芯片封装105的细长容器22包括在外部端子20的顶面上方延伸的部分22a之外。如上文所述,容器22的部分22a可与电路板50内的凹槽54啮合(如图3所示)。这样,容器22的部分22a延伸到外部端子20表面的外部,可起到稳定半导体芯片封装105与PCB 50之间连接的作用。同样,延伸部分22a例如当半导体芯片封装105与PCB接合到一起时有助于将它们对准。容器22的部分22a内的导电液体24的部分24a当暴露于空气时可以固化。
图6为根据本发明一实施例的包括外部端子和多个突出物或细长容器的半导体芯片封装的截面图。
参见图6,半导体芯片封装100包括细长容器22和突出物22b。突出物22b可以是与细长容器22类似的细长容器,并包含有导电液体。突出物22b内部的导电液体可以是与细长容器22内的相同的材料,或者不同的材料。或者,突出物22b可以基本上完全是由导电材料或非导电材料制成的固体。
图7为根据本发明某些实施例的具有形成在电极焊盘上的细长容器的半导体芯片封装的截面图。
参见图7,制造半导体芯片封装的方法可包括在电极焊盘12上提供细长容器22。电极焊盘12可包含UBM 18,则此情形中在UBM 18上提供细长容器22。电极焊盘12和/或UBM 18可包含凹槽,并且细长容器22可延伸入凹槽中以改善其间的粘附性。具体来说,电极焊盘12和UBM 18之一或二者都可包含凹槽(未示出),并且容器22可延伸入凹槽中。在提供到电极焊盘12之前,细长容器22可用导电液体24填充并可以被切割至所需的长度。通过切割细长容器22而暴露的导电液体24当暴露于空气时固化,由此密封容器22的端部。容器22可通过提供铜片、将铜片辊压成圆柱形、将该圆柱形镀镍的方法以及其它方法形成。
图8为根据本发明某些实施例的具有形成在电极焊盘上的部分填充的细长容器的半导体芯片封装的截面图。
参见图8,制造半导体芯片封装的方法可包括在设置于半导体基板10上的电极焊盘12上提供细长容器22。电极焊盘12可包含UBM 18,此情形中在UBM 18上提供细长容器22。电极焊盘12和/或UBM 18可包括凹槽,并且细长容器22可延伸入凹槽以改善其间的粘附性。细长容器22最初可以是中空容器,例如在提供到电极焊盘12上以后,之后填充入导电液体24。可通过向容器22注入导电液体24来使用导电液体24填充细长容器22。导电液体24可利用容器22内部与容器22外部之间的压差注入容器22内。使用这种压差方法可以将容器22内的气泡的出现最小化。填充后暴露于空气的导电液体24可固化。换言之,在填充容器22后暴露于空气的导电液体24可固化,由此密封容器22的端部。
图9为根据本发明某些实施例的具有细长容器和形成于电极焊盘上的焊膏的半导体芯片封装的截面图。
参见图9,可通过在基板10上印刷焊膏20a来形成外部端子20。具体来说,可通过本领域公知的丝网印刷工艺或任何其它常规工艺在基板10上印刷焊膏20a。焊膏20a可以基本上包围细长容器22并接触电极焊盘12和/或UBM 18。焊膏20a可以暴露于加热步骤以形成外部端子20。焊膏20a可包括在本领域公知的常规焊料、无铅焊料或任何其它导电材料。
图10为根据本发明某些实施例的具有插入形成于电极焊盘上的外部端子的细长容器的半导体芯片封装的截面图。
参见图10,根据本发明某些实施例,在基板10上形成焊膏20a和/或外部端子20后,可将细长容器22插入焊膏20a或外部端子20中。具体来说,可于印刷工艺之后,但在加热步骤之前,将容器22插入焊膏20a中,或者可在加热步骤之后,将容器22插入外部端子20中。通过控制外部端子20的热状态,可在不损害容器22并且不改变外部端子20的形状的情形下,将细长容器22插入外部端子20中。导电液体24的部分24a通过在将容器22插入外部端子20之前暴露于空气中而固化。或者,在将容器22插入外部端子20之前,部分24a可以是用来密封容器22中的导电液体24的不同材料。例如,可以对容器22的一端部进行涂敷工艺以密封容器22中的导电液体24。
图11为根据本发明某些实施例的通过含有裂缝或裂纹的外部端子接合到电路板的半导体芯片封装的截面图。
参见图11,当外部端子20暴露于应力时,例如在加热步骤中,外部端子20中将形成裂纹或裂缝28。由于容器22的存在可抑制外部端子20中裂纹28的传播。同样,裂纹28可能使容器22破裂。当裂纹28使容器22破裂时,导电液体24的部分24s脱离容器并至少部分填充裂纹28。导电液体24的部分24s可完全填充裂纹28。脱离容器22的导电液体24的部分24s可暴露于空气中并固化以形成导电材料。因此,导电液体24的部分24s可密封裂纹并恢复外部端子20的机械稳定性。而且,导电液体24的部分24s可将外部端子20的电阻特性恢复到与裂纹28产生前基本相同的水平。
如上文所述,本发明实施例提供了包含填充有导电液体的容器的外部端子。通过此容器抑制在外部端子内的裂纹的传播。而且,如果裂纹使容器破裂,来自容器的导电液体至少部分填充裂纹,改善或恢复连接的电阻特性。因此,根据本发明实施例,与常规方法相比,芯片封装与PCB之间的连接可靠性得到改善。
本说明书通篇提及的“一个实施例”或“一实施例”表示结合该实施例描述的具体特征、结构或特性包含在本发明的至少一个实施例中。因此,本说明书通篇各处出现的所有短语“在一实施例中”或“在一个实施例中”不一定都指代相同的实施例。而且,具体特征、结构或特性可以任何适当的方式包含在一个或多个实施例中。
各种操作将以最有助于理解本发明的形式进行的多个分离步骤来描述。但是,其中所描述的步骤的顺序并不意味着这些操作依赖于该顺序,或者也不意味着必须以描述这些步骤的顺序执行这些步骤的顺序。
而且,为了避免不必要的细节使对本发明的描述含糊不清,没有给出公知的结构和公知的器件。
前面仅仅是在较宽范围内对本发明的示意性说明,不应理解为对其的限定。虽然本发明已经描述了几个示意性实施例,但是本领域技术人员能够想到,在实质上不脱离本发明新的启示和优点情形下,对示意性实施例做各种修改也是可行的。相应地,所有这些修改都将包括在如权利要求限定的本发明范围内。例如,虽然本发明已经用细长容器来描述,但是只要容器与所描述的细长容器具有相同功能,则容器也可以不是细长的,或者可以是与附图所示不同的细长形状。因此,应理解,前面是对本发明的示例,而不应理解为限于所公开的具体实施例,并且对所公开实施例的修改和其它实施例将包含在权利要求的范围内。本发明由权利要求以及其中包含的权利要求的等同特征限定。
Claims (42)
1.一种半导体器件,包括:
半导体基板;
设置于所述半导体基板上的电极焊盘;
设置于所述电极焊盘上的外部端子;
从所述电极焊盘延伸入所述外部端子中的容器;以及
设置于所述容器内部的导电液体。
2.权利要求1的器件,其中所述导电液体当暴露于空气时固化。
3.权利要求1的器件,其中所述导电液体的粘度的范围为约1 0cps至约5000cps。
4.权利要求1的器件,其中所述导电液体包括金属。
5.权利要求1的器件,其中所述导电液体包括金属膏、导电油墨或纳米金属溶胶。
6.权利要求1的器件,还包括位于所述电极焊盘上的凸点下金属,其中所述容器直接与所述凸点下金属的顶面接触,或者所述容器嵌入在所述凸点下金属中。
7.权利要求1的器件,其中所述容器直接接触所述电极焊盘。
8.权利要求1的器件,其中所述电极焊盘包括凹槽,并且所述容器延伸入所述凹槽中。
9.权利要求1的器件,其中所述容器在所述外部端子的顶面上方延伸。
10.权利要求1的器件,还包括一个或多个设置于所述外部电极中的突出物。
11.权利要求10的器件,其中所述突出物为固体。
12.权利要求10的器件,其中每个所述突出物包括设置于其中的导电液体。
13.权利要求1的器件,还包括:
电路板;以及
与所述电极焊盘的位置相对应的、设置于所述电路板和所述外部端子之间的接触焊盘。
14.权利要求13的器件,其中所述接触焊盘包括形成在其中的凹槽,以及其中所述容器从所述电极焊盘延伸,穿过所述外部端子,进入所述接触焊盘的凹槽中。
15.权利要求13的器件,其中所述接触焊盘包括穿过其形成的通孔,以及其中所述容器延伸穿过所述通孔。
16.一种半导体器件,包括:
半导体基板;
设置于所述半导体基板上的电极焊盘;
设置于所述电极焊盘上的外部端子;
设置来从所述电极焊盘延伸入所述外部端子中的细长容器;
电路板;
设置在所述电路板和所述外部端子之间的接触焊盘;
所述外部端子内部的裂纹,所述裂纹从所述细长容器的外壁延伸到所述细长容器;以及
设置于所述细长容器和所述裂纹内部的导电材料。
17.权利要求16的器件,其中所述导电材料为之前是液体的固体。
18.一种半导体器件,包括:
半导体基板;
设置于所述半导体基板上的电极焊盘;
设置于所述电极焊盘上的外部端子;以及
在所述外部端子内部延伸的裂纹,
其中所述裂纹至少部分填充有从所述导电液体固化的导电材料。
19.一种制造半导体器件的方法,该方法包括:
在半导体基板上形成电极焊盘;
在所述电极焊盘上形成容器,使得所述容器从所述电极焊盘延伸,其中所述容器包含有导电液体;以及
在所述电极焊盘上和所述容器周围形成外部端子。
20.权利要求19的方法,其中形成容器包括:
在所述电极焊盘上形成中空容器;以及
用导电液体填充所述中空容器。
21.权利要求19的方法,其中所述导电液体当暴露于空气时固化。
22.权利要求19的方法,其中所述导电液体具有的粘度的范围为约10cps至约5000cps。
23.权利要求19的方法,其中所述导电液体包括金属。
24.权利要求19的方法,其中所述导电液体包括金属膏、导电油墨或纳米金属溶胶。
25.权利要求19的方法,还包括将所述容器切割到所需长度。
26.权利要求25的方法,其中通过切割所述容器而暴露的部分导电液体由于暴露于空气而固化以密封所述容器。
27.权利要求19的方法,其中形成外部端子包括:
将焊膏印刷到所述半导体基板上,所述焊膏在所述容器周围;以及
加热所述焊膏以形成焊球。
28.权利要求19的方法,还包括在所述电极焊盘中形成凹槽,其中所述容器插入所述凹槽中。
29.权利要求19的方法,还包括在所述电极焊盘上形成一个或多个突出物。
30.一种制造半导体器件的方法,该方法包括:
在半导体基板上形成电极焊盘;
在所述电极焊盘上形成外部端子;以及
将细长容器插入所述外部端子中,所述细长容器容纳有导电液体。
31.权利要求30的方法,还包括在所述电极焊盘上形成凸点下金属,以及其中所述容器直接接触所述凸点下金属的顶面,或者所述容器嵌入所述凸点下金属中。
32.一种制造半导体器件的方法,该方法包括:
在半导体基板上形成电极焊盘;
在所述电极焊盘上形成外部端子,所述外部端子包括容纳有导电液体的细长容器;
在所述外部端子中产生应力以在所述外部端子内部形成裂纹;以及
用来自所述细长容器的导电液体至少部分填充所述裂纹。
33.权利要求32的方法,其中产生所述应力包括进行热处理。
34.权利要求32的方法,其中形成所述外部端子包括将所述细长容器插入所述外部端子中。
35.权利要求34的方法,其中形成所述外部端子包括印刷焊膏,还包括在插入所述细长容器后加热所述焊膏以形成焊球。
36.权利要求32的方法,其中形成所述外部端子包括:
在所述电极焊盘上形成所述细长容器,以使所述细长容器从所述电极焊盘延伸;以及
在所述电极焊盘上和所述容器周围形成所述外部端子。
37.权利要求36的方法,其中形成所述外部端子还包括用所述导电液体填充所述细长容器。
38.权利要求32的方法,其中所述导电液体当暴露于空气时固化。
39.权利要求32的方法,其中形成所述电极焊盘包括在所述电极焊盘中形成凹槽,其中所述细长容器延伸入所述凹槽中。
40.一种半导体器件,包括:
半导体基板;
设置于所述半导体基板上的电极焊盘;以及
设置于所述电极焊盘上的外部端子,其中所述外部端子包括导电液体。
41.权利要求40的器件,还包括设置在所述外部端子内的细长容器,其中所述导电液体设置在所述细长容器内。
42.权利要求40的器件,其中配置所述导电液体使其在暴露于空气时固化。
Applications Claiming Priority (4)
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KR121657/06 | 2006-12-04 | ||
US11/858,078 | 2007-09-19 |
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US (1) | US7675171B2 (zh) |
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TW (1) | TW200818360A (zh) |
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KR20080030897A (ko) | 2008-04-07 |
KR101328551B1 (ko) | 2013-11-13 |
US7675171B2 (en) | 2010-03-09 |
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