CN102136453A - 空腔互连技术中的焊料 - Google Patents
空腔互连技术中的焊料 Download PDFInfo
- Publication number
- CN102136453A CN102136453A CN2010106210128A CN201010621012A CN102136453A CN 102136453 A CN102136453 A CN 102136453A CN 2010106210128 A CN2010106210128 A CN 2010106210128A CN 201010621012 A CN201010621012 A CN 201010621012A CN 102136453 A CN102136453 A CN 102136453A
- Authority
- CN
- China
- Prior art keywords
- soldered ball
- solder
- cavity
- wall
- projection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0018—Brazing of turbine parts
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
- B23K1/203—Fluxing, i.e. applying flux onto surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/06—Solder feeding devices; Solder melting pans
- B23K3/0607—Solder feeding devices
- B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/046—Surface mounting
- H05K13/0465—Surface mounting by soldering
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10135—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1143—Manufacturing methods by blanket deposition of the material of the bump connector in solid form
- H01L2224/11442—Manufacturing methods by blanket deposition of the material of the bump connector in solid form using a powder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11474—Multilayer masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12222—Shaped configuration for melting [e.g., package, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mechanical Engineering (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本发明涉及空腔互连技术中的焊料。互连技术可使用模制焊料来限定焊球。掩模层可被图案化,以便形成空腔和淀积在空腔中的焊膏。在加热时,形成焊球。空腔由间隔开的壁来限定,以便阻止焊球在接合过程中桥接。在一些实施例中,连接到焊球的焊料凸块可具有比焊球的相对面更大的相对面。
Description
技术领域
一般来说,本发明涉及集成电路互连技术。
背景技术
集成电路互连技术将两个电子组件进行机械和电连接。例如,焊球可用于将集成电路连接到印刷电路板、如主板。集成电路设置在主板之上,而焊球介于其间。在称作回流的过程中,当加热时,焊料被软化,并且在器件之间形成焊点。
虽然这种类型的表面安装或C4连接一直极为成功,但是不断地希望增加可形成的互连的密度。可形成的每个单位面积的互连越多,则所得到的器件可以越小。一般来说,器件越小,则其成本越低,并且其性能越高。
此外,现有器件可容易出现许多故障,包括焊球与其它组件之间的应力或疲劳相关故障,例如焊点下面的低介电常数的电介质的脱层。其它故障包括桥接故障,其中来自一个连接的焊料桥接到相邻连接上。
发明内容
按照本发明的一个方面,提供一种方法,包括:
形成电气组件,其中焊料凸块固定到焊球,使得所述焊球的相对面小于或等于所述焊料凸块的相对面。
按照本发明的另一方面,提供一种方法,包括:
将第一组件与第二组件对齐,所述第一组件具有在相邻壁之间限定的空腔之内的焊球,所述第二组件包括焊接区,以便连接到所述焊球;
将压力施加到所述组件之一;以及
使所述焊球的焊料回流到所述焊接区。
按照本发明的又一方面,提供一种设备,包括:
平坦的表面;
多个壁,所述多个壁从所述表面向外延伸并且限定所述壁之间的空腔;
在所述空腔的每一个中形成的焊料凸块;以及
在所述焊料凸块上的焊球,所述焊球的相对面小于或等于所述焊料凸块的相对面。
附图说明
图1是在早期阶段的一个实施例的放大截面图;
图2是根据一个实施例在后续阶段的放大截面图,其中涂层已经被涂敷并且图案化;
图3是根据一个实施例、在涉及焊膏印刷的后续阶段的放大截面图;
图4是根据一个实施例、在涉及回流焊的后续阶段的放大截面图;
图5是根据一个实施例、在后续阶段的放大截面图,其中示出两个组件之间的互连;
图6是另一个实施例的放大截面图;
图7是又一个实施例的放大截面图;
图8是根据一个实施例的焊球和焊接区的放大图示;
图9是示出施加焊膏的一个实施例的放大截面图;
图10是空腔间壁的一个实施例的放大截面图;以及
图11是再一个实施例的放大截面图。
具体实施方式
根据一些实施例,互连技术可使用介于焊料凸块之间的空腔间壁来保持所焊接的互连之间的分隔。在一些情况下,这些壁可减少焊接连接的桥接或断裂故障。另外,在一些情况下,连接的可靠性可得到提高。
在一些实施例中,代替淀积焊球,可将焊料模制在待接合到另一个组件的组件上的空腔中的适当位置。然后,焊球可在空腔内的适当位置形成。因此,在一些实施例中,空腔间壁可提供相邻焊点之间的分隔,减少桥接,并且在一些实施例中允许更小的互连间距。另外,居间的壁可用于加强或支承焊点,特别是响应横向负荷。
根据一个实施例,如图1所示,在衬底10上可形成多个金属焊接区或凸块12。衬底10可以是适合接合集成组件的任何组件,所述集成组件包括集成电路晶圆、管芯、印刷电路板或者甚至已封装集成电路。在一些实施例中,凸块12可由铜形成。
在一些情况下,凸块12可大于常规凸块。更大的凸块可用于减小凸块中对于焊球连接的应力。在一些情况下,凸块大于焊球是有利的,但是通常焊球大于其下面的凸块。
应力通过较小面积耦合,在本发明的一些实施例中,通过较大的凸块,减小在一些情况中在凸块之下的应力。因此,有利的是,在一些实施例中,使凸块大于所得焊球的相对面(facing surface)。
参照图2,可涂敷如光致抗蚀剂之类的掩模层14并且对其图案化。作为图案化的结果,空腔16在凸块12中的每一个之上形成。另外,在空腔16之间形成居间的空腔间壁17。壁17相当于被蚀刻的掩模层14的残留剩余部分。注意,在一些实施例中,壁17可以为T形的,具有在相邻凸块12之间延伸的部分15以及在其上在相邻空腔16之间延伸的部分。因此,壁17的部分19实际上覆盖在凸块12的端部上面。
然后,如图3所示,包括其空腔16的图2的结构充当用于印刷焊膏18的有效模具。焊膏18淀积在空腔16之内。
在一些实施例中,焊料是具有助熔剂基体(flux matrix)中的焊锡粉的较小尺寸微球的焊膏。在一些实施例中,焊锡粉的直径为最小特征尺寸的1/7或更小,这通常是空腔16的厚度或深度。
然后参照图4,焊料回流,使印刷的焊料18呈现曲面结构或者焊球的形状,具有与凸块12邻接的展平表面。还应当观测到,焊球20的体积比所淀积的焊膏18要小。这样的一个原因是助焊剂基体的挥发。焊球20的曲面形状是层14上的焊接材料的表面能或者润湿角的作用。
来看图5,图4所示的衬底10则可啮合结构22。结构22可以是集成电路芯片、集成电路晶圆、衬底或者印刷电路板,这里只是列举几个例子。结构22可具有直立焊接区24,每个的尺寸确定在空腔16以内并且啮合其中的焊球20。
在一些实施例中,直立焊接区24啮合并且穿透焊球20,从而形成强连接。实际上,连接是三维的。与常规焊球连接技术相比,互连表面面积比常规表面安装的面积要大,从而在一些实施例中产生强得多的连接。在一些实施例中,施加超过衬底10的重量的压力P,以便产生焊接区24对焊球20的这种相互啮合和穿透。
根据另一个实施例,壁17可用图6所示的由层叠部分26和28所组成的二层壁17a代替。内部部分26可由一种材料形成,外部部分28可由不同的材料形成,使得可去除材料28,而留下材料26。例如,在一些实施例中,材料28可通过不会实质影响材料26的蚀刻剂去除。
由于在需要时去除层28,完全在空腔16内形成的焊球20a可从仅由内层26所限定的减小的空腔中伸出。焊球20a的伸出在一些实施例中可能是有利的。在一个实施例中,结构22a可具有可能没有图5的焊接区24高的焊接区24a。
参照图7,根据又一个实施例,空腔16a和16b可具有不同尺寸。因此,焊球20b和20c可具有不同尺寸。这种焊球尺寸差异在对不规则成形的组件进行电和机械连接时可能是有利的。实际上,空腔可被确定尺寸以创建具有与另一个结构的配置匹配的共同配置的焊球。在一些实施例中,可在壁17b、17c与居间的焊球20c或20b之间保持间隙G。在一些实施例中,间隙G可以是壁17与焊球之间的20微米间隙。
另外,可淀积层30,以便限定禁入区,从而将焊球限制到凸块12b或12c之上的特定中心区域。层30可以是不易于被流体焊料润湿的材料。
接下来参照图8,在一些实施例中,有利的是,凸块12的长度L2实质上大于焊球20的相对面的长度L1。下面给出更具体的示例,在一些实施例中,具有200微米的常规互连间距可能是有利的。但是对于这种间距,与按常规具有100微米尺寸的常规凸块(对于200微米间距)相比,凸块具有比常规凸块大得多的尺寸、例如大约180微米是有利的。同时,焊球20可具有160微米尺寸L1,它小于凸块尺寸L2。相比之下,这类技术中的常规焊球会大于凸块,并且可以是大约130至140微米。
因此,在一些实施例中,对于相同间距,凸块和焊球更大。在一些实施例中,更大的焊料凸块尺寸产生更可靠的连接。具体来说,在一些实施例中,焊球尺寸至少为间距的75%。在一些实施例中,凸块尺寸至少为间距的70%,并且凸块大于焊料。在一些实施例中,由于限制并且分离焊料的壁17所提供的相邻连接之间的物理屏障,有利的配置是可能的。
参照图9,一种用于将焊膏32淀积在空腔16中的技术采用使用橡皮辊S的橡皮辊印刷。橡皮辊印刷通过在橡皮辊前面使焊膏34的一部分移过空腔16,将焊料整洁地淀积到空腔16中。但是,其它技术也可用于将焊膏印刷或淀积到空腔16中。
参照图10,在一些实施例中,壁17与凸块12重叠由“O/L”所示的距离。在一些实施例中,使壁与凸块边缘重叠阻止焊料尺寸变得与凸块一样大,并且减小应力。在一些实施例中,由于可靠性原因并且特别是为了应力减小,焊料没有润湿到凸块的边缘可能是有利的。因此,在一些实施例中,使用材料来形成粘附于通常为铜的用于凸块12的材料的层14,也是有利的。更大的凸块厚度也是更好的,因为它散布来自集成电路的热量。
在一些实施例中,壁17比最终凸块尺寸要高得多。例如,在一些情况下,壁17可比凸块高50至100微米。这种高度差可采用200至250微米的空腔16深度或厚度来实现。
根据一些实施例,不是使用常规光致抗蚀剂,而是可使用干膜来限定空腔。在一些情况下,干膜空腔可比焊球要宽。
在一些实施例中,焊料凸块可以相对拉长或者更椭圆而不是圆。换言之,凸块的纵横比可比所示的要大得多。另外,凸块可由两种不同焊料的复合材料来制成。在一些实施例中,结构22上的焊接区可比衬底10上的凸块小得多。因此,在接合时,焊料可呈现截头锥体(frustroconical)形状而不是所示的更圆的形状。在一些情况下,底层填料可施加在截头锥体焊接接缝之间。
在一些实施例中,焊球可延伸到超出壁,在其它实施例中,它们可延伸到壁高度,而在又一些实施例中,焊球的高度可小于壁的高度。例如,焊球的不同高度可通过结构22上的焊接区的不同高度来适应。
参照图11,根据又一个实施例,衬底10c可固定到具有突出体24b的结构22b。衬底10c可具有在经由电镀、焊膏印刷或其它方法形成所述焊料凸块12d之前形成的壁17d。焊球20d使用相同壁17d来形成,并且因而具有实质上等于焊料凸块12d的直径的直径。例如,焊料凸块12d可以是具有柱形或球形的铜或焊接材料。
在一些情况下,图11的实施例可采用焊料来形成,所述焊料使用用于电镀凸块12d的相同光致抗蚀剂来焊膏印刷。籽层(未示出)可在焊料回流之后剥去。
本说明书全文中提到“一个实施例”或“实施例”表示结合该实施例所述的具体特征、结构或特性包含在本发明内所涵盖的至少一个实现中。因此,短语“一个实施例”或“在一个实施例中”的出现不一定都指的是同一个实施例。此外,具体特征、结构或特性可通过与所示具体实施例不同的其它适当形式来创立,并且所有这类形式都可涵盖在本申请的权利要求中。
虽然针对有限数量的实施例描述了本发明,但是本领域的技术人员将会从其中知道大量修改和变化。所附权利要求意在涵盖落入本发明的真实精神和范围之内的所有这类修改和变化。
Claims (30)
1.一种方法,包括:
形成电气组件,其中焊料凸块固定到焊球,使得所述焊球的相对面小于或等于所述焊料凸块的相对面。
2.如权利要求1所述的方法,包括:通过将焊膏模制在空腔中来制作所述焊球。
3.如权利要求2所述的方法,包括:从向外延伸的壁形成所述空腔,并且保持所述壁,以便保护所述壁的两个相邻部分之间的所述焊球。
4.如权利要求3所述的方法,包括:由图案化的淀积层形成所述壁。
5.如权利要求4所述的方法,包括:由光致抗蚀剂形成所述层。
6.如权利要求4所述的方法,包括:由干膜形成所述层。
7.如权利要求2所述的方法,包括:由直径小于或等于所述空腔的深度的1/7的粉末形成所述焊膏。
8.如权利要求1所述的方法,包括:形成尺寸至少为互连间距的75%的所述焊球。
9.如权利要求1所述的方法,包括:形成至少为互连间距的70%的所述焊料凸块。
10.如权利要求1所述的方法,包括:在两个相邻焊球之间形成壁,所述壁延伸到超出所述凸块。
11.如权利要求10所述的方法,包括:形成所述壁,从而与两个相邻焊料凸块的边缘部分重叠。
12.如权利要求2所述的方法,包括:形成不同尺寸的空腔。
13.如权利要求1所述的方法,包括:在管芯上形成所述凸块。
14.如权利要求1所述的方法,包括:在衬底上形成所述凸块。
15.如权利要求3所述的方法,包括:将焊球连接到具有穿入所述空腔的突出体的另一个器件。
16.如权利要求3所述的方法,包括:由至少两层形成所述壁。
17.如权利要求16所述的方法,包括:由层叠的外层和内层形成所述壁,使得可去除所述外层,而不去除所述内层。
18.如权利要求17所述的方法,包括:形成高于所述内层的所述焊球。
19.如权利要求2所述的方法,包括:将焊膏用橡皮辊印刷到所述空腔中。
20.如权利要求19所述的方法,包括:使所述焊膏回流,从而形成润湿所述焊料凸块的焊球。
21.如权利要求1所述的方法,包括:在所述焊料凸块上形成材料,从而限制焊料的润湿。
22.一种方法,包括:
将第一组件与第二组件对齐,所述第一组件具有在相邻壁之间限定的空腔之内的焊球,所述第二组件包括焊接区,以便连接到所述焊球;
将压力施加到所述组件之一;以及
使所述焊球的焊料回流到所述焊接区。
23.如权利要求22所述的方法,包括:施加压力,使得所述焊接区穿入所述焊球。
24.如权利要求22所述的方法,包括:使所述焊接区延伸到所述空腔中。
25.一种设备,包括:
平坦的表面;
多个壁,所述多个壁从所述表面向外延伸并且限定所述壁之间的空腔;
在所述空腔的每一个中形成的焊料凸块;以及
在所述焊料凸块上的焊球,所述焊球的相对面小于或等于所述焊料凸块的相对面。
26.如权利要求25所述的设备,其中,所述壁包括光致抗蚀剂。
27.如权利要求25所述的设备,其中,所述焊球的尺寸至少为互连间距的75%。
28.如权利要求25所述的设备,其中,所述焊料凸块至少为互连间距的70%。
29.如权利要求25所述的设备,所述壁从所述表面向外延伸到超出所述凸块。
30.如权利要求29所述的设备,其中,所述壁与两个相邻焊料凸块的边缘部分重叠。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610354839.4A CN106024743A (zh) | 2009-12-21 | 2010-12-21 | 空腔互连技术中的焊料 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/643084 | 2009-12-21 | ||
US12/643,084 US8424748B2 (en) | 2009-12-21 | 2009-12-21 | Solder in cavity interconnection technology |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610354839.4A Division CN106024743A (zh) | 2009-12-21 | 2010-12-21 | 空腔互连技术中的焊料 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN102136453A true CN102136453A (zh) | 2011-07-27 |
Family
ID=44149661
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610354839.4A Pending CN106024743A (zh) | 2009-12-21 | 2010-12-21 | 空腔互连技术中的焊料 |
CN2010106210128A Pending CN102136453A (zh) | 2009-12-21 | 2010-12-21 | 空腔互连技术中的焊料 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610354839.4A Pending CN106024743A (zh) | 2009-12-21 | 2010-12-21 | 空腔互连技术中的焊料 |
Country Status (5)
Country | Link |
---|---|
US (3) | US8424748B2 (zh) |
KR (1) | KR20110073314A (zh) |
CN (2) | CN106024743A (zh) |
SG (1) | SG172531A1 (zh) |
TW (2) | TWI546145B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103943515A (zh) * | 2013-01-21 | 2014-07-23 | 国际商业机器公司 | 具有电绝缘壁的芯片堆叠及其形成方法 |
CN104425287A (zh) * | 2013-08-19 | 2015-03-18 | 讯芯电子科技(中山)有限公司 | 封装结构及制造方法 |
CN111354705A (zh) * | 2020-03-20 | 2020-06-30 | 维沃移动通信(重庆)有限公司 | 电路板装置及其制备方法、电子设备 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8424748B2 (en) | 2009-12-21 | 2013-04-23 | Intel Corporation | Solder in cavity interconnection technology |
US8936967B2 (en) | 2011-03-23 | 2015-01-20 | Intel Corporation | Solder in cavity interconnection structures |
US20150027756A1 (en) * | 2013-07-23 | 2015-01-29 | Kinsus Interconnect Technology Corp. | Circuit board structure for high frequency signals |
US20160021153A1 (en) * | 2014-07-16 | 2016-01-21 | Highway Hottie, LLC | System and computer program for social media utilizing navigation |
CN106816417B (zh) * | 2017-01-13 | 2019-02-12 | 南京大学 | 一种高密度封装及其制造方法 |
CN107564923B (zh) * | 2017-10-13 | 2020-03-31 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、柔性显示装置 |
US10483221B2 (en) * | 2017-10-30 | 2019-11-19 | Micron Technology, Inc. | 3DI solder cup |
US20190157222A1 (en) * | 2017-11-20 | 2019-05-23 | Nxp Usa, Inc. | Package with isolation structure |
TWI690947B (zh) * | 2018-11-30 | 2020-04-11 | 台灣愛司帝科技股份有限公司 | 導電物質的布局方法、布局結構及包含其之led顯示器 |
JP7525878B2 (ja) * | 2020-06-17 | 2024-07-31 | 東北マイクロテック株式会社 | 積層型半導体装置及びこれに用いる搭載部品、基体及びバンプ接続体 |
US11875988B2 (en) | 2021-04-29 | 2024-01-16 | Nxp Usa, Inc. | Substrate pad and die pillar design modifications to enable extreme fine pitch flip chip (FC) joints |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146674A (en) * | 1991-07-01 | 1992-09-15 | International Business Machines Corporation | Manufacturing process of a high density substrate design |
US5313021A (en) * | 1992-09-18 | 1994-05-17 | Aptix Corporation | Circuit board for high pin count surface mount pin grid arrays |
US20030009878A1 (en) * | 2001-07-12 | 2003-01-16 | John Gregory | Method for attaching an electronic component to a substrate |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
WO1993019487A1 (en) * | 1992-03-24 | 1993-09-30 | Unisys Corporation | Integrated circuit module having microscopic self-alignment features |
JP2800691B2 (ja) | 1994-07-07 | 1998-09-21 | 株式会社デンソー | 回路基板の接続構造 |
US5539153A (en) * | 1994-08-08 | 1996-07-23 | Hewlett-Packard Company | Method of bumping substrates by contained paste deposition |
CA2135508C (en) * | 1994-11-09 | 1998-11-03 | Robert J. Lyn | Method for forming solder balls on a semiconductor substrate |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
US5929521A (en) * | 1997-03-26 | 1999-07-27 | Micron Technology, Inc. | Projected contact structure for bumped semiconductor device and resulting articles and assemblies |
JP2907188B2 (ja) * | 1997-05-30 | 1999-06-21 | 日本電気株式会社 | 半導体装置、半導体装置の実装方法、および半導体装置の製造方法 |
US5977632A (en) | 1998-02-02 | 1999-11-02 | Motorola, Inc. | Flip chip bump structure and method of making |
US6268114B1 (en) * | 1998-09-18 | 2001-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for forming fine-pitched solder bumps |
US6190940B1 (en) | 1999-01-21 | 2001-02-20 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
TW460991B (en) | 1999-02-04 | 2001-10-21 | United Microelectronics Corp | Structure of plug that connects the bonding pad |
CN1383197A (zh) * | 2001-04-25 | 2002-12-04 | 松下电器产业株式会社 | 半导体装置的制造方法及半导体装置 |
US6622907B2 (en) * | 2002-02-19 | 2003-09-23 | International Business Machines Corporation | Sacrificial seed layer process for forming C4 solder bumps |
US6583517B1 (en) * | 2002-04-09 | 2003-06-24 | International Business Machines Corporation | Method and structure for joining two substrates with a low melt solder joint |
US6921860B2 (en) * | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
JP4094982B2 (ja) * | 2003-04-15 | 2008-06-04 | ハリマ化成株式会社 | はんだ析出方法およびはんだバンプ形成方法 |
JP4389471B2 (ja) * | 2003-05-19 | 2009-12-24 | パナソニック株式会社 | 電子回路の接続構造とその接続方法 |
TWI241001B (en) * | 2004-03-26 | 2005-10-01 | Advanced Semiconductor Eng | Method of improving adhesive characteristic between photoresist layer and substrate, and bumping process |
US7459386B2 (en) * | 2004-11-16 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming solder bumps of increased height |
US20070269973A1 (en) * | 2006-05-19 | 2007-11-22 | Nalla Ravi K | Method of providing solder bumps using reflow in a forming gas atmosphere |
JP5017930B2 (ja) * | 2006-06-01 | 2012-09-05 | 富士通株式会社 | 半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法 |
US7485563B2 (en) * | 2006-06-29 | 2009-02-03 | Intel Corporation | Method of providing solder bumps of mixed sizes on a substrate using a sorting mask and bumped substrate formed according to the method |
US7652374B2 (en) | 2006-07-31 | 2010-01-26 | Chi Wah Kok | Substrate and process for semiconductor flip chip package |
US20080157353A1 (en) | 2006-12-29 | 2008-07-03 | Texas Instruments Incorporated | Control of Standoff Height Between Packages with a Solder-Embedded Tape |
US20090127703A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Low-Profile Semiconductor Assembly |
US7749887B2 (en) * | 2007-12-18 | 2010-07-06 | Micron Technology, Inc. | Methods of fluxless micro-piercing of solder balls, and resulting devices |
JP5076922B2 (ja) * | 2008-01-25 | 2012-11-21 | 株式会社日立プラントテクノロジー | ハンダボール印刷装置 |
US20090218688A1 (en) | 2008-02-28 | 2009-09-03 | International Business Machines Corporation | Optimized passivation slope for solder connections |
US7780063B2 (en) * | 2008-05-15 | 2010-08-24 | International Business Machines Corporation | Techniques for arranging solder balls and forming bumps |
TWI473553B (zh) * | 2008-07-03 | 2015-02-11 | Advanced Semiconductor Eng | 晶片封裝結構 |
US8424748B2 (en) | 2009-12-21 | 2013-04-23 | Intel Corporation | Solder in cavity interconnection technology |
US8936967B2 (en) | 2011-03-23 | 2015-01-20 | Intel Corporation | Solder in cavity interconnection structures |
-
2009
- 2009-12-21 US US12/643,084 patent/US8424748B2/en active Active
-
2010
- 2010-10-29 SG SG2010080067A patent/SG172531A1/en unknown
- 2010-11-03 TW TW099137763A patent/TWI546145B/zh active
- 2010-11-03 TW TW105117034A patent/TWI623365B/zh active
- 2010-12-20 KR KR1020100130907A patent/KR20110073314A/ko not_active Application Discontinuation
- 2010-12-21 CN CN201610354839.4A patent/CN106024743A/zh active Pending
- 2010-12-21 CN CN2010106210128A patent/CN102136453A/zh active Pending
-
2013
- 2013-03-26 US US13/850,581 patent/US20130206820A1/en not_active Abandoned
-
2014
- 2014-05-05 US US14/269,571 patent/US9848490B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5146674A (en) * | 1991-07-01 | 1992-09-15 | International Business Machines Corporation | Manufacturing process of a high density substrate design |
US5313021A (en) * | 1992-09-18 | 1994-05-17 | Aptix Corporation | Circuit board for high pin count surface mount pin grid arrays |
US20030009878A1 (en) * | 2001-07-12 | 2003-01-16 | John Gregory | Method for attaching an electronic component to a substrate |
Non-Patent Citations (1)
Title |
---|
TOBIAS BAUMGARTNER ET AL.: "《Printing Solder Paste in Dry Film - A Low Cost Fine-Pitch Bumping Technique》", 《2007 9TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE》 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103943515A (zh) * | 2013-01-21 | 2014-07-23 | 国际商业机器公司 | 具有电绝缘壁的芯片堆叠及其形成方法 |
CN103943515B (zh) * | 2013-01-21 | 2017-03-01 | 国际商业机器公司 | 具有电绝缘壁的芯片堆叠及其形成方法 |
CN104425287A (zh) * | 2013-08-19 | 2015-03-18 | 讯芯电子科技(中山)有限公司 | 封装结构及制造方法 |
CN111354705A (zh) * | 2020-03-20 | 2020-06-30 | 维沃移动通信(重庆)有限公司 | 电路板装置及其制备方法、电子设备 |
CN111354705B (zh) * | 2020-03-20 | 2022-05-20 | 维沃移动通信(重庆)有限公司 | 电路板装置及其制备方法、电子设备 |
Also Published As
Publication number | Publication date |
---|---|
TWI623365B (zh) | 2018-05-11 |
US20110147440A1 (en) | 2011-06-23 |
US20140240943A1 (en) | 2014-08-28 |
TW201716166A (zh) | 2017-05-16 |
US20130206820A1 (en) | 2013-08-15 |
KR20110073314A (ko) | 2011-06-29 |
US8424748B2 (en) | 2013-04-23 |
CN106024743A (zh) | 2016-10-12 |
TW201134588A (en) | 2011-10-16 |
US9848490B2 (en) | 2017-12-19 |
TWI546145B (zh) | 2016-08-21 |
SG172531A1 (en) | 2011-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102136453A (zh) | 空腔互连技术中的焊料 | |
KR101572600B1 (ko) | 다층 배선 요소와 마이크로전자 요소가 실장된 어셈블리 | |
JP5012514B2 (ja) | 多層配線板の製造法 | |
JP2009158593A (ja) | バンプ構造およびその製造方法 | |
TWI345939B (en) | Method of manufacturing a multilayer wiring board | |
EP0997942A2 (en) | Chip Size Semiconductor Package and process for producing it | |
US9698094B2 (en) | Wiring board and electronic component device | |
US8302297B2 (en) | Method of fabricating a circuit board structure | |
CN103229605A (zh) | 布线基板 | |
TWI463931B (zh) | 電路板及其製作方法 | |
JP6510897B2 (ja) | 配線基板及びその製造方法と電子部品装置 | |
JP4597631B2 (ja) | 部品内蔵配線板、部品内蔵配線板の製造方法 | |
CN103945657A (zh) | 一种在印制电路板上制作铜柱的方法 | |
KR20090121676A (ko) | 회로 기판의 제조 방법 및 그 방법으로 제조된 회로 기판 | |
US20010044198A1 (en) | Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same | |
JP2010141049A (ja) | 配線構造体 | |
JP5014673B2 (ja) | 多層配線基板及びその製造方法 | |
CN105097558A (zh) | 芯片封装结构、制作方法及芯片封装基板 | |
JP2006303338A (ja) | 多層回路基板とその製造方法 | |
CN102123578B (zh) | 表面安装集成电路组件 | |
JP2011238843A (ja) | 突起電極付き配線基板及び突起電極付き配線基板の製造方法 | |
JP5750896B2 (ja) | 回路基板及びその製造方法、並びに電子装置 | |
US7939940B2 (en) | Multilayer chip scale package | |
JP2007081437A (ja) | 印刷配線板の製造方法 | |
JP2002043745A (ja) | 配線基板及びそれを用いた半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110727 |