CN104425287A - 封装结构及制造方法 - Google Patents

封装结构及制造方法 Download PDF

Info

Publication number
CN104425287A
CN104425287A CN201310362550.3A CN201310362550A CN104425287A CN 104425287 A CN104425287 A CN 104425287A CN 201310362550 A CN201310362550 A CN 201310362550A CN 104425287 A CN104425287 A CN 104425287A
Authority
CN
China
Prior art keywords
encapsulating structure
substrate
insulated column
weld pad
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310362550.3A
Other languages
English (en)
Inventor
王月荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
- Core Of Electronic Science And Technology (zhongshan) Co Ltd
Original Assignee
- Core Of Electronic Science And Technology (zhongshan) Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by - Core Of Electronic Science And Technology (zhongshan) Co Ltd filed Critical - Core Of Electronic Science And Technology (zhongshan) Co Ltd
Priority to CN201310362550.3A priority Critical patent/CN104425287A/zh
Priority to TW102130971A priority patent/TW201515161A/zh
Priority to US14/059,455 priority patent/US20150048504A1/en
Publication of CN104425287A publication Critical patent/CN104425287A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

一种封装结构，包括基板、设于基板上的芯片、多个锡球、多个焊垫、封胶体及与焊垫一一对应的隔离柱。芯片通过锡球与焊垫电性连接，封胶体包覆于芯片。隔离柱自相应的焊垫的边缘朝向远离焊垫的方向延伸形成，锡球收容于隔离柱内，隔离柱用于防止相邻的两个锡球之间发生短路。本发明还揭示了一种封装结构制造方法。本发明提供的封装结构及制造方法，通过在焊垫周边设置隔离柱，将锡球收容于隔离柱内，解决了锡桥问题，缩小了产品尺寸。

Description

封装结构及制造方法
技术领域
本发明涉及一种封装结构及制造方法，尤其涉及一种倒装芯片的封装结构及制造方法。
背景技术
现有技术中，倒装芯片的封装结构是通过在基板上设计阻隔层来防止相邻的锡球之间发生锡桥现象。由于需要在基板上镀大量的阻隔层以及需要预焊，从而使得相邻焊垫之间的中心距离必须大于100um以使相邻焊垫之间预留相应的空间来设置阻隔层。因此，采用此种结构会增大基板的尺寸，制造成本高，且不利于封装结构的小型化的发展趋势。
发明内容
有鉴于此，需提供一种封装结构及制造方法，不但可以有效解决锡球与锡球之间的锡桥问题，而且可缩小封装产品的尺寸。
本发明提供的封装结构，包括基板、设于基板上的多个焊垫、多个锡球、芯片及封胶体。所述芯片通过所述锡球与所述焊垫电性连接，所述封胶体包覆所述芯片，所述封装结构还包括与所述焊垫一一对应的隔离柱，所述隔离柱自相应的焊垫的边缘朝向远离所述焊垫的方向延伸形成，所述锡球收容于所述隔离柱内，所述隔离柱用于防止相邻的所述两个锡球之间发生短路。
优选地，所述隔离柱的材质为铜。
优选地，每两个相邻的所述隔离柱之间部分重合。
优选地，每两个相邻的所述隔离柱之重合部分的厚度为40um。
优选地，所述隔离柱的厚度为40um。
优选地，每两个相邻的隔离柱之间的距离为40um。
本发明提供的封装结构制造方法，用于将倒装芯片封装于基板上，所述封装结构制造方法包括：
制作所述基板外层线路，所述外层线路包括多个焊垫，所述基板分为第一区域及与所述焊垫一一对应的第二区域，所述第二区域围绕所述焊垫设置；
在所述第一区域上覆盖干膜；
在所述第二区域上制作隔离柱，所述隔离柱自所述焊垫的边缘朝向远离所述焊垫的方向延伸；
移除所述干膜；
蚀刻掉所述基板上多余的电镀线；
将锡球收容于所述隔离柱内并与所述基板电性连接，将所述倒装芯片置放于所述锡球上；
采用封胶体包覆所述倒装芯片，使所述倒装芯片定位于所述基板上。
优选地，所述隔离柱采用电镀的方式形成。
优选地，在将锡球收容于所述隔离柱内并与所述基板电性连接的步骤之间还包括在所述基板表面设置保护膜。
优选地，所述保护膜通过电镀镍金的方式或采用有机保护膜的方式形成。
相较于现有技术，本发明的封装结构通过触刻或电镀的方式设置隔离柱，用以取代阻焊层的设计，且无需在基板上进行预焊锡，有效的缩短了焊垫与焊垫之间的距离，从而缩小了产品的尺寸。同时，锡球与锡球之间通过隔离柱隔开，可有效防止锡桥的现象发生。
附图说明
图1所示为本发明实施方式中封装结构截面示意图。
图2所示为本发明封装结构的制造方法的流程图。
图3所示为制造基板外层线路的示意图。
图4所示为在第一区域覆盖干膜的示意图。
图5所示为电镀隔离柱的示意图。
图6所示为在基板上电镀保护膜的示意图。
图7所示为放置倒装芯片的示意图。
图8所示为基板封装成型的示意图。
图9所示为本发明另一种实施方式中封装结构截面示意图。
主要元件符号说明
封装结构                  100
基板           10
外层线路                  11
干膜                      12
隔离柱                    20
保护膜                    21
锡球                      30
芯片                      40
焊垫                      50
封胶体                    60
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参照图1，本发明提供的封装结构100，包括基板10、设于基板10上的多个焊垫50、多个锡球30、芯片40及封胶体60。所述芯片40通过所述锡球30与所述焊垫50电性连接，所述封胶体60包覆所述芯片40。所述封装结构100还包括与所述焊垫一一对应的隔离柱20，所述隔离柱20自相应的焊垫50的边缘朝向远离所述焊垫50的方向延伸形成。所述锡球30收容于所述隔离柱20内，所述隔离柱20用于防止相邻的所述两个锡球30之间发生短路。
由此可见，本发明提供的封装结构100，通过在焊垫50之周边设置隔离柱20，将锡球30收容于隔离柱20内使相邻的锡球之间被隔离，从而能够有效防止基板在封装过程中发生锡桥的现象，缩小了封装产品的尺寸。
进一步的，在本实施方式中，所述隔离柱20的材质为铜。由于铜具有良好的导电性和热传导性，通过在基板上增加隔离柱，可以提高封装产品的散热性能。在本发明的其他实施方式中，隔离柱20也可以为其他金属材质，例如铝。
本实施方式中，每两个相邻的隔离柱20之间是相互分离的，每两个相邻的所述隔离柱20之间的距离为40um。由此可见，相较于先前技术，基板上焊垫与焊垫之间的距离大大缩小，从而有效缩小了封装结构的尺寸，符合产品小型化的发展趋势。
在本发明的其他实施方式（请参照图9）中，每两个相邻的所述隔离柱20之间部分重合，每两个相邻的所述隔离柱20之重合部分的厚度为40um。由于每两个相邻的所述隔离柱20之间可以实现重叠，大大缩小了焊垫与焊垫之间的距离，从而减小了产品的尺寸。
本发明之封装结构制造方法用于将所述倒装芯片40封装于基板10上。所述封装结构制造方法包括如下步骤。
请同时参照图2及图3，在步骤S100，将所述基板10分为第一区域及与所述焊垫一一对应的第二区域，所述第二区域围绕所述焊垫50设置，在所述基板10的第二区域制作外层线路11，需要保留电镀线。
请同时参照图2及图4，在步骤S200，在第一区域上覆盖干膜12，以防止基板表面氧化。
请同时参照图2及图5，在步骤S300，在所述第二区域上制作隔离柱20，所述隔离柱20自所述焊垫50的边缘朝向远离所述焊垫50的方向延伸。本实施方式中，所述隔离柱20的材质为铜，所述隔离柱20的厚度为40um，所述隔离柱20采用电镀的方式形成。在本发明的其他实施方式中，隔离柱20也可以为其他金属材质，例如铝。
请参照图2，在步骤S400，移除所述干膜12，本实施方式中，所述干膜12采用化学药液蚀刻的方式移除。
请参照图2，在步骤S500，蚀刻掉多余的电镀线。
请同时参照图2及图6，在步骤S600，在所述隔离柱20及焊垫50表面设置保护膜21，以对基板10的表面进行保护。所述保护膜21通过电镀镍金的方式或采用有机保护膜的方式形成，所述有机保护膜经过高温后会熔化，保证了焊垫50的导电性。
请同时参照图2及图7，在步骤S700，将锡球30收容于所述隔离柱20与所述焊垫50形成的凹槽内并通过所述焊垫50与电路板电性连接，将所述倒装芯片40置放于所述锡球30上。
请同时参照图2及图8，在步骤S800，采用封胶体60包覆所述倒装芯片40，使所述倒装芯片40定位于所述基板10上。
本实施方式中，采用注胶成型的技术将封胶体60包覆所述倒装芯片40，使所述倒装芯片40定位于所述基板10上。
本发明提供的封装结构制造方法利用倒装芯片的技术将倒装芯片40内埋于封胶体60内，通过采用电镀的方式设置隔离柱20，将锡球置放于隔离柱内以防止锡桥的现象发生，且相邻隔离柱之间的尺寸可根据需要进行相应调整，将隔离柱重叠可以缩短焊垫之间的距离，缩小封装产品的尺寸，适用于高密度倒装芯片的封装。

Claims (10)

1.一种封装结构，包括基板、设于基板上的多个焊垫、多个锡球、芯片及封胶体，所述芯片通过所述锡球与所述焊垫电性连接，所述封胶体包覆所述芯片，其特征在于，所述封装结构还包括与所述焊垫一一对应的隔离柱，所述隔离柱自相应的焊垫的边缘朝向远离所述焊垫的方向延伸形成，所述锡球收容于所述隔离柱内，所述隔离柱用于防止相邻的所述两个锡球之间发生短路。
2.如权利要求1所述的封装结构，其特征在于，所述隔离柱的材质为铜。
3.如权利要求1所述的封装结构，其特征在于，每两个相邻的所述隔离柱之间部分重合。
4.如权利要求3所述的封装结构，其特征在于，每两个相邻的所述隔离柱之重合部分的厚度为40um。
5.如权利要求1所述的封装结构，其特征在于，每一个隔离柱的厚度为40um。
6.如权利要求1所述的封装结构，其特征在于，每两个相邻的所述隔离柱之间的距离为40um。
7.一种封装结构制造方法，用于将倒装芯片封装于基板上，其特征在于，所述封装结构制造方法包括：
制作所述基板外层线路，所述外层线路包括多个焊垫，所述基板分为第一区域及与所述焊垫一一对应的第二区域，所述第二区域围绕所述焊垫设置；
在所述第一区域上覆盖干膜；
在所述第二区域上制作隔离柱，所述隔离柱自所述焊垫的边缘朝向远离所述焊垫的方向延伸；
移除所述干膜；
蚀刻所述基板上多余的电镀线；
将锡球收容于所述隔离柱内并与所述基板电性连接，将所述倒装芯片置放于所述锡球上；
采用封胶体包覆所述倒装芯片，使所述倒装芯片定位于所述基板上。
8.如权利要求7所述的封装结构制造方法，其特征在于，所述隔离柱采用电镀的方式形成。
9.如权利要求7所述的封装结构制造方法，其特征在于，在将锡球收容于所述隔离柱内并与所述基板电性连接的步骤之间还包括在所述基板表面设置保护膜。
10.如权利要求9所述的封装结构制造方法，其特征在于，所述保护膜通过电镀镍金的方式或采用有机保护膜的方式形成。
CN201310362550.3A 2013-08-19 2013-08-19 封装结构及制造方法 Pending CN104425287A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310362550.3A CN104425287A (zh) 2013-08-19 2013-08-19 封装结构及制造方法
TW102130971A TW201515161A (zh) 2013-08-19 2013-08-29 封裝結構及製造方法
US14/059,455 US20150048504A1 (en) 2013-08-19 2013-10-22 Package assembly for chip and method of manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310362550.3A CN104425287A (zh) 2013-08-19 2013-08-19 封装结构及制造方法

Publications (1)

Publication Number Publication Date
CN104425287A true CN104425287A (zh) 2015-03-18

Family

ID=52466264

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310362550.3A Pending CN104425287A (zh) 2013-08-19 2013-08-19 封装结构及制造方法

Country Status (3)

Country Link
US (1) US20150048504A1 (zh)
CN (1) CN104425287A (zh)
TW (1) TW201515161A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355573B (zh) * 2015-11-04 2017-11-21 苏州启微芯电子科技有限公司 Ccga自动植柱机
US10186478B2 (en) * 2016-12-30 2019-01-22 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface
US11437333B2 (en) * 2016-12-30 2022-09-06 Texas Instruments Incorporated Packaged semiconductor device with a reflow wall
FR3119048A1 (fr) * 2021-01-21 2022-07-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Interconnexion avec ame

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090068858A1 (en) * 2007-08-17 2009-03-12 Centipede Systems, Inc. Miniature electrical ball and tube socket assembly with self-capturing multiple-contact-point coupling
CN101496168A (zh) * 2006-07-31 2009-07-29 智识投资基金27有限责任公司 用于半导体倒装芯片封装的衬底和过程
CN102136453A (zh) * 2009-12-21 2011-07-27 英特尔公司 空腔互连技术中的焊料
CN102637649A (zh) * 2012-04-28 2012-08-15 日月光半导体制造股份有限公司 半导体结构的制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
KR0157284B1 (ko) * 1995-05-31 1999-02-18 김광호 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지
US5611884A (en) * 1995-12-11 1997-03-18 Dow Corning Corporation Flip chip silicone pressure sensitive conductive adhesive
JPH11274237A (ja) * 1998-03-23 1999-10-08 Casio Electronics Co Ltd ボールグリッドアレイ実装方法
US6750551B1 (en) * 1999-12-28 2004-06-15 Intel Corporation Direct BGA attachment without solder reflow
US7557452B1 (en) * 2000-06-08 2009-07-07 Micron Technology, Inc. Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same
JP3440243B2 (ja) * 2000-09-26 2003-08-25 株式会社アドバンストシステムズジャパン スパイラルコンタクタ
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
TWI236109B (en) * 2004-02-26 2005-07-11 Advanced Semiconductor Eng Chip package
US7445141B2 (en) * 2004-09-22 2008-11-04 International Business Machines Corporation Solder interconnection array with optimal mechanical integrity
US7749806B2 (en) * 2005-09-22 2010-07-06 Chipmos Technologies Inc. Fabricating process of a chip package structure
US7847414B2 (en) * 2005-09-22 2010-12-07 Chipmos Technologies Inc. Chip package structure
US8487428B2 (en) * 2007-11-20 2013-07-16 Fujitsu Limited Method and system for providing a reliable semiconductor assembly
FR2936359B1 (fr) * 2008-09-25 2010-10-22 Commissariat Energie Atomique Connexion par emboitement de deux inserts soudes.
CN101872727A (zh) * 2009-04-24 2010-10-27 国碁电子(中山)有限公司 一种芯片焊接方法及结构
US20110210443A1 (en) * 2010-02-26 2011-09-01 Xilinx, Inc. Semiconductor device having bucket-shaped under-bump metallization and method of forming same
DE102010040065B4 (de) * 2010-08-31 2015-07-23 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verspannungsreduktion in einem Chipgehäuse unter Anwendung eines Chip-Gehäuse-Verbindungsschemas bei geringer Temperatur
JP5645592B2 (ja) * 2010-10-21 2014-12-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8410604B2 (en) * 2010-10-26 2013-04-02 Xilinx, Inc. Lead-free structures in a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101496168A (zh) * 2006-07-31 2009-07-29 智识投资基金27有限责任公司 用于半导体倒装芯片封装的衬底和过程
US20090068858A1 (en) * 2007-08-17 2009-03-12 Centipede Systems, Inc. Miniature electrical ball and tube socket assembly with self-capturing multiple-contact-point coupling
CN102136453A (zh) * 2009-12-21 2011-07-27 英特尔公司 空腔互连技术中的焊料
CN102637649A (zh) * 2012-04-28 2012-08-15 日月光半导体制造股份有限公司 半导体结构的制造方法

Also Published As

Publication number Publication date
TW201515161A (zh) 2015-04-16
US20150048504A1 (en) 2015-02-19

Similar Documents

Publication Publication Date Title
JP5032623B2 (ja) 半導体記憶装置
CN105489591A (zh) 半导体封装及其制造方法
CN103579128B (zh) 芯片封装基板、芯片封装结构及其制作方法
TWI523158B (zh) 雙面封裝結構及應用其之無線通訊系統
JP2015176906A (ja) 半導体装置および半導体装置の製造方法
JP5400094B2 (ja) 半導体パッケージ及びその実装方法
US9173298B2 (en) Packaging substrate, method for manufacturing same, and chip packaging structure having same
TWI468086B (zh) 電子裝置、系統級封裝模組及系統級封裝模組的製造方法
TWI724744B (zh) 半導體裝置及半導體裝置之製造方法
JP2012015185A (ja) 半導体記憶装置
CN111627871A (zh) 半导体封装件
JP2009016843A (ja) リードフレーム構造体及びそれを備えた半導体パッケージ
KR20150130660A (ko) 반도체 패키지 및 그의 제조 방법
JP2014045051A (ja) 電子部品内蔵基板及びその製造方法
US20170117251A1 (en) Fan-out 3D IC Integration Structure without Substrate and Method of Making the Same
CN104425287A (zh) 封装结构及制造方法
CN105489565A (zh) 嵌埋元件的封装结构及其制法
CN103151274A (zh) 半导体元件及其制造方法
US10916520B2 (en) Semiconductor device, and method of manufacturing the same
CN102064162B (zh) 堆叠式封装结构、其封装结构及封装结构的制造方法
CN202940236U (zh) 封装基板构造
CN102751203A (zh) 半导体封装结构及其制作方法
TWI501370B (zh) 半導體封裝件及其製法
JP2011003818A (ja) モールドパッケージ
CN105990155A (zh) 芯片封装基板、芯片封装结构及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150318

WD01 Invention patent application deemed withdrawn after publication