CN102130094B - 集成电路芯片 - Google Patents

集成电路芯片 Download PDF

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CN102130094B
CN102130094B CN201010597866.7A CN201010597866A CN102130094B CN 102130094 B CN102130094 B CN 102130094B CN 201010597866 A CN201010597866 A CN 201010597866A CN 102130094 B CN102130094 B CN 102130094B
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layer
pad
integrated circuit
bond pad
chip
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CN102130094A (zh
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黄裕华
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MediaTek Inc
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Abstract

本发明提供一种集成电路芯片。所述集成电路芯片包含衬底、顶层金属层及焊盘。顶层金属层位于衬底上方；焊盘位于顶层金属层中；多个金属间绝缘层，位于衬底上方；其中焊盘的厚度比顶层金属层的厚度小，且所有金属间绝缘层均在顶层金属层下方。本发明的集成电路芯片的结构可避免焊盘变形或开裂。

Description

集成电路芯片
技术领域
本发明有关于集成电路芯片的焊盘(pad)结构，且特别有关于改进的线接合(wire-bonding)焊盘结构及具有该线接合焊盘结构的集成电路芯片，该集成电路芯片可在线接合期间避免焊盘变形(pad deformation)或开裂。
背景技术
目前，业界存在对于具有多功能及高性能的小型且较廉价电子产品的迫切需求。电路设计的主流趋势是将尽可能多的电路组件整合至集成电路中，从而降低每片晶片的成本。
集成电路是通过在硅晶片的表面形成半导体器件而制造的。器件之间形成多层互连(multi-level interconnection)，用来与各主动器件接触并将各器件线连接在一起以创建所需电路。导线层(wiring layer)是在器件上沉积绝缘层(dielectric layer)，在该层内成型(patterning)并刻蚀(etching)接触窗开口(contactopening)，随后在开口内沉积导体材料(conductive material)而形成的。导体层(conductive layer)应用于绝缘层之上并被图型化(patterned)，以在器件接触点之间形成导线互连(wiring interconnection)，从而创建基本电路(basic circuitry)的首层。所述电路随后通过利用额外的导线层而进一步互连，而所述额外的导线层位于具有导电通孔(conductive via)的额外的绝缘层上。根据整体集成电路的复杂度，可使用数层导线互连。在顶层，导线终止于金属焊盘，而芯片的外部导线连接则接合至所述金属焊盘。
在某些情况下，具有导线的顶层可为厚铝层。金属焊盘(例如线接合(wire-bonding))及RF器件(例如集成电感器(integrated inductor)、金属-氧化物-金属电容器、电阻器或重新分布层(redistribution layer，简称为RDL))可同时在厚铝层中形成。然而，由于线接合期间施加于其上的压力，厚铝层可导致焊盘变形。变形的接合焊盘也可能在覆盖接合焊盘外缘的钝化层(passivationlayer)内造成破裂缺陷(fracture defect)，以及潜在的焊盘至焊盘的桥接(pad-to-pad bridging)。通常，上述问题可采用增大每一焊盘、焊盘开口及/或两焊盘之间的空间尺寸来处理。然而，增大每一焊盘、焊盘开口及焊盘间距(pad pitch)的尺寸将导致芯片尺寸及成本的增加。
发明内容
有鉴于此，特提供以下技术方案：
本发明实施例提供一种集成电路芯片的实施例，集成电路芯片包含衬底、顶层金属层及焊盘。顶层金属层位于衬底上方；焊盘位于顶层金属层中；多个金属间绝缘层，位于衬底上方；其中焊盘的厚度比顶层金属层的厚度小，且所有金属间绝缘层均在顶层金属层下方。
以上所述的集成电路芯片提供了一种新型接合垫结构，从而避免了接合焊盘变形或开裂。
附图说明
图1是依据本发明实施例的集成电路芯片的一部分的横截面示意图。
图2是依据本发明另一实施例的集成电路芯片的一部分的横截面的示意图。
图3是依据本发明又一实施例的集成电路芯片的一部分的横截面的示意图。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来指称特定的组件。所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语，故应解释成“包含但不限定于”。另外，“耦接”一词在此包含任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表第一装置可直接电气连接于第二装置，或透过其它装置或连接手段间接地电气连接至第二装置。
以下将结合附图来说明本发明的实施例。在说明书以及附图中，符号“Mn”代表制作于集成电路芯片中的顶层(topmost level)金属层，例如铝重新分布层，而“Mn-1”代表比顶层金属层低一层的金属层，并依此类推，其中，优选地，n介于2到10之间(n＝2-10)，但并非仅限于此。符号“V，9代表连接两邻近金属层的通孔(via plug)。举例而言，V5代表将M5互连至M6的通孔。
请参考图1，图1是根据本发明一个实施例的集成电路芯片1的一部分的横截面的示意图。应可理解，图1中的层或者元件并非依据实际尺寸画出，且被修改以使其更清楚。集成电路芯片1可包含用于合并RF器件的顶层金属层Mn的RF集成电路，例如电感器或者适合于RF电路的任何其他器件。用于RF器件的顶层金属层Mn可为铝层、铜层(copper layer)或者铜合金层(copper alloy layer)，其中铝层为优选方案。
顶层金属层可降低寄生损耗(parasitic loss)，从而改善RF集成电路的品质因数(quality factor)Q。在本实施例中，顶层金属层的厚度不小于0.5微米(micrometer)。在某些实施例中，顶层金属层可具有不小于1.0微米的厚度。在另一些实施例中，顶层金属层可具有不小于3.0微米的厚度。
如图1所示，集成电路芯片1包含衬底10，例如硅衬底。衬底10可为任何适合的半导体衬底，例如硅锗(SiGe)衬底或者硅晶绝缘体(Silicon onInsulator，SOI)衬底。基本层12形成于衬底10上，且包含但不限于器件层，例如金氧半(MOS)或者双极型器件，以及至少一层间绝缘(inter-layerdielectric，ILD)层。为简洁起见，基本层12内包含导线及接触/通孔的互连未画出。多个金属间绝缘(inter-metal dielectric，IMD)层14、16、18及20被提供于基本层12之上。多个IMD层14、16、18及20中的每一个可包含但不限于氧化硅(silicon oxide)、氮化硅(silicon nitride)、碳化硅(silicon carbide)、氮氧化硅(silicon oxy-nitride)、低介电常数或者超低介电常数(ultra low-k，ULK)材料(例如有机(例如，芳香族碳氢化合物(SiLK))或者无机(例如，含氢的硅酸盐(HSQ))材料)，或者上述材料的任意组合。钝化层22位于IMD层20的至少一部分之上。钝化层22可为氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺(polyimide)或者上述材料的任意组合或者类似物质。根据本实施例，钝化层22具有0.5至6.0微米的厚度，但并不仅限于此。
金属互连40，例如Mn-2、Vn-2及Mn-1，可被分别制造于对应的IMD层14、16及18内。RF器件，例如可包含第一绕组(winding)24及邻近于第一绕组24的第二绕组26的电感器200，被制造于位于集成电路芯片1的电感器形成区101内的顶层金属层Mn内。根据本发明的实施例，顶层金属层Mn具有不小于0.5微米的厚度h。在某些实施例中，顶层金属层具有不小于1.0微米的厚度。在另一些实施例中，顶层金属层具有不小于3.0微米的厚度。电感器200的第一绕组24与第二绕组26的侧壁(sidewall)与顶面(top surface)可被钝化层22覆盖。尽管本实施例以电感器为例，但本发明并不仅限于此。应可理解，其他RF器件，例如MOM电容器或者电阻器可于顶层金属层Mn形成。进一步，顶层金属层Mn可用于形成重新分布层。
根据本发明的实施例，金属层Mn-1可由铝制成，其中至少一接合焊盘118形成于金属层Mn-1内，而金属层Mn-2可由传统的铜镶嵌(damascene)方式形成，例如单镶嵌(single damascene)方式或者双镶嵌(dual damascene)方式。例如，金属层Mn-2可由单镶嵌方式形成，而金属层Mn-1及积分通孔层(integral viaplug layer)Vn-2可由传统的铝工艺形成。此外，Mn-2可由铝形成。如本领域中技术人员所了解，铜镶嵌方式提供一种不需要干法刻蚀(dry etch)铜而形成耦接至积分通孔的导线的解决方案。单镶嵌或者双镶嵌结构可用于连接器件及/或集成电路的导线。
集成电路芯片1包含接合焊盘形成区102。至少一接合焊盘118形成于接合焊盘形成区102之内的金属层Mn-1中。金属层Mn-1可比顶层金属层Mn薄。例如，金属层Mn-1可具有约0.2-1微米的厚度。开口202形成于钝化层22及IMD层20中以暴露出接合焊盘118的上表面(top surface)的至少一部分，使得接合线30可在封装组装阶段(package assembly stage)附着至接合焊盘118。开口202可具有约0.8-6.0微米的深度d。根据本发明的实施例，接合焊盘118优选地为铝焊盘，但并不限于此。
可选地，支撑结构114及116可被形成于接合焊盘118之下。支撑结构114及116可为任何合适的形状及组态(configuration)，以在导线接合期间为接合焊盘118提供足够的机械支撑。例如，支撑结构114可为制造于金属层Mn-2内的仿真金属板(dummy metal plate)，而支撑结构116可为多个通孔，用于连接支撑结构114与接合焊盘118。此外，接合焊盘118下的区域112之内可形成主动电路(active circuit)、电路元件或互连(未画出)。
图2是依据本发明另一实施例的集成电路芯片1a的一部分的横截面的示意图，其中相似的标号表示相似的层、区域或者元件。应可理解，图2的层或者元件并非依据实际尺寸画出，且被修改以使其更清楚。如图2所示，类似地，集成电路芯片1a包含衬底10。基本层12以及多个IMD层14、16、18及20，被提供于衬底10之上。多个IMD层14、16、18及20中的每一个可包含(但不限于)氧化硅、氮化硅、碳化硅、氮氧化硅、低介电常数或者超低介电常数材料(例如有机(例如，SiLK)或者无机(例如，HSQ)材料)，或者上述材料的任意组合。钝化层22位于IMD层20的至少一部分之上。钝化层22可为氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺或者上述材料的任意组合或者类似物质。根据本实施例，钝化层22具有0.5至6.0微米的厚度，但并不限于此。
金属互连40，例如Mn-2、Vn-2及Mn-1，可被分别制造于对应的IMD层14、16及18内。RF器件，例如可包含第一绕组24及邻近于第一绕组24的第二绕组26的电感器200，被制造于位于集成电路芯片1a的电感器形成区101内的顶层金属层Mn内。根据本发明的实施例，顶层金属层Mn具有不小于0.5微米的厚度h。在某些实施例中，顶层金属层Mn具有不小于1.0微米的厚度。在另一些实施例中，顶层金属层可具有不小于3.0微米的厚度。电感器200的第一绕组24与第二绕组26的侧壁与顶面可被钝化层22覆盖。
集成电路芯片1a更包含接合焊盘形成区102。至少一接合焊盘214可形成于低于顶层金属层Mn的任何金属层之内，例如接合焊盘形成区102之内的金属层Mn-2。开口302形成于钝化层22及IMD层16、18及20中以暴露出接合焊盘214的上表面的至少一部分，使得接合线30可在封装组装阶段附着至接合焊盘214。开口302可具有约1.0-8.0微米的深度。请注意，如图2所示，接合焊盘214下的支撑结构可被省略。
图3是依据本发明又一实施例的集成电路芯片1b的一部分的横截面的示意图，其中相似的标号表示相似的层、区域或者元件。如图3所示，集成电路芯片1b包含衬底10。基本层12以及多个IMD层14、16、18及20被提供于衬底10之上。多个IMD层14、16、18及20中的每一个可包含(但不限于)氧化硅、氮化硅、碳化硅、氮氧化硅、低介电常数或者超低介电常数材料(例如有机(例如，SiLK)或者无机(例如，HSQ)材料)，或者上述材料的任意组合。钝化层22可位于IMD层20的至少一部分之上。钝化层22可为氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺或者上述材料的任意组合或者类似物质。根据本实施例，钝化层22具有大约0.5至6.0微米的厚度，但并不限于此。
金属互连40，例如Mn-2、Vn-2、Mn-1及Vn-1，可被分别制造于IMD层14、16、18及20内。在本实施例中，RF器件，例如可包含第一绕组24及邻近于第一绕组24的第二绕组26的电感器200，可被制造于位于集成电路芯片1a的电感器形成区101内的顶层金属层Mn内。在某些实施例中，RDL可形成于顶层金属层Mn内。根据本发明的实施例，顶层金属层Mn可具有不小于1.0微米的厚度h。电感器200的第一绕组24与第二绕组26的侧壁与顶面可被钝化层22覆盖。
集成电路芯片1b更包含接合焊盘形成区102。至少一接合焊盘128可形成于接合焊盘形成区102内的顶层金属层Mn之内。接合焊盘128可用于线接合。依据本发明的实施例，接合焊盘128及电感器200形成于同一金属层内，即，顶层金属层Mn之内。在某些情形中，RDL导线(未画出)也可形成于顶层金属层Mn之内。开口402形成于钝化层22中以暴露出接合焊盘128的上表面的至少一部分，使得接合线30可在封装组装阶段附着至接合焊盘128。依据本发明的实施例，接合焊盘128是铝焊盘，但不限于此。顶层金属层Mn可为铝层，但不限于此。在集成电路芯片1b通过铜工艺制造并且接合焊盘128是铝焊盘的情形下，金属层Mn-1可成为顶层铜导线层或最终的铜导线层。然而，应可理解，本实施例也可适用于铝集成电路芯片，其中金属互连通过铝工艺制造，从而金属层Mn和Mn-1均为铝层。
依据本发明的实施例，接合焊盘128可为具有较薄中心部分128a及环绕较薄中心部分128a的较厚外缘部分128b的碗状(bowl-shaped)接合焊盘。接合线30的头部可处于由较厚外缘部分128b环绕的凹腔128c中。开口402形成之后，可进行额外的刻蚀处理或过度刻蚀(over-etching)步骤以刻蚀暴露出的接合焊盘128的一部分，从而形成凹腔128c。在某些情况下，开口402的侧壁可基本上与较厚外缘部分128b的内侧壁对齐。在某些情况下，开口402的侧壁可比较厚外缘部分128b的内侧壁更向外延伸。此外，上述工艺中可不需要额外的光掩模(photo mask)。应可理解，凹腔128c及接合焊盘128的碗状结构可通过干法刻蚀、湿法刻蚀(wet etching)或其他适合的方式形成。
依据本发明的实施例，较厚外缘部分128b具有不超过或大体上等于顶层金属层Mn、电感器200或RDL导线(未画出)厚度的厚度。顶层金属层Mn、电感器200或RDL导线(未画出)的厚度可为，例如，不少于1.0微米。依据本发明的实施例，较薄中心部分128a具有不超过2微米的厚度t。依据本发明的实施例，较厚外缘部分128b的宽度w可大于0.5微米，例如，大约0.5-10微米。钝化层22可覆盖较厚外缘部分128b的上表面。由于接合焊盘128具有减少的厚度并进而具有减少的体积，线接合期间的焊盘变形或开裂可被避免。此外，较厚外缘部分128b可作为坝(dam)，以抵消施加于较薄中心部分128a上的压力。
可选地，支撑结构114、116、124及126可被形成于接合焊盘128之下。支撑结构114、116、124及126可为任何适合的形状及组态，以在导线接合期间为接合焊盘128提供足够的机械支撑。例如，支撑结构114可为制造于金属层Mn-2内的仿真金属板，而支撑结构116可为多个通孔，用于连接支撑结构114与支撑结构124，支撑结构126则可为多个通孔，用于连接支撑结构124与接合焊盘128。此外，接合焊盘128下的区域112之内可形成主动电路、电路元件或互连(未画出)。在铝工艺中，支撑结构126可为多个钨通孔。在铜工艺中，接合焊盘128可为铝焊盘，而支撑结构126可为与接合焊盘128整体形成的多个铝通孔。
应可理解，尽管本发明的实施例利用线接合焊盘作为范例，但本发明也适用于其他类性的焊盘，例如凸点(bump)焊盘、焊锡(solder)焊盘或RDL焊盘。所述RDL焊盘可为RDL倒装芯片(flip-chip)焊盘。本发明并不限于线接合焊盘及利用线接合焊盘的集成电路芯片。此外，在集成电路上也存在RDL焊盘的情况下，接合焊盘128的较薄中心部分128a的厚度t可不等于RDL焊盘的最薄部分的厚度。
以上所述仅为本发明的较佳实施例，本领域相关的技术人员依据本发明的精神所做的等效变化与修改，都应当涵盖在权利要求书内。

Claims (5)

1.一种集成电路芯片，包含：
衬底；
顶层金属层，位于该衬底上方；
焊盘，位于该顶层金属层中；以及
多个金属间绝缘层，位于该衬底上方；
其中该焊盘的厚度比该顶层金属层的厚度小，且所有金属间绝缘层均在该顶层金属层下方。
2.根据权利要求1所述的集成电路芯片，更包含钝化层，覆盖该焊盘的外缘部分，该钝化层包含开口，该开口暴露出该焊盘的中心部分，并且该焊盘的该中心部分比该顶层金属层薄。
3.根据权利要求1所述的集成电路芯片，更包含钝化层，覆盖该焊盘的外缘部分，该钝化层包含开口，该开口暴露出该焊盘的中心部分，并且该焊盘的该中心部分具有不超过2微米的厚度。
4.根据权利要求1所述的集成电路芯片，其特征在于，该焊盘是铝焊盘。
5.根据权利要求1所述的集成电路芯片，其特征在于，该顶层金属层具有不少于1微米的厚度。
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