TWI423406B - 積體電路晶片 - Google Patents

積體電路晶片 Download PDF

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TWI423406B
TWI423406B TW099142059A TW99142059A TWI423406B TW I423406 B TWI423406 B TW I423406B TW 099142059 A TW099142059 A TW 099142059A TW 99142059 A TW99142059 A TW 99142059A TW I423406 B TWI423406 B TW I423406B
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pad
integrated circuit
metal layer
top metal
layer
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TW099142059A
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TW201133738A (en
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yu hua Huang
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Mediatek Inc
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Description

積體電路晶片
本發明有關於積體電路晶片之焊墊架構。更具體而言，本發明有關於改良之線接合(wire-bonding)焊墊架構及具有該線接合焊墊架構之積體電路晶片，該積體電路晶片可於線接合期間避免焊墊變形(pad deformation)或開裂。
目前，業界存在對於具有多功能及高性能之小型且較廉價電子產品之迫切需求。電路設計之主流趨勢係將盡可能多的電路組件整合入積體電路中，從而降低每片晶圓之成本。
積體電路係藉由在矽晶圓之表面形成半導體器件而製造。器件之間形成多層內連接(multi-level interconnection)，與各主動器件接觸並將各器件線連接在一起以創建所需電路。導線層(wiring layer)係在器件上沉積介電層(dielectric layer)，在該層內成型(patterning)並蝕刻(etching)接觸窗開口(contact opening)，隨後在開口內沉積導體材料(conductive material)而形成。導體層(conductive layer)應用於介電層之上並被圖型化(patterned)，以在器件接觸點之間形成導線內連接(wiring interconnection)，從而創建基本電路(basic circuitry)之首層。電路隨後藉由利用額外之導線層而進一步內連接，所述額外之導線層位於具有導體介層窗(conductive via)之額外之介電層上。根據整體積體電路之複雜度，可使用數層導線內連接。在頂層，導線終止於金屬焊墊，而晶片之外部導線連接則接合至所述金屬焊墊。
於某些狀況下，具有導線之頂層可係為厚鋁層。金屬焊墊(例如線接合(wire-bonding))及RF器件(例如整合電感器(integrated inductor)、MOM電容器、電阻器或重分佈層(redistribution layer，簡稱為RDL))可同時在厚鋁層中形成。然而，由於線接合期間施加於其上之壓力，厚鋁層可造成焊墊變形。變形之接合焊墊亦可在覆蓋接合焊墊外緣之鈍化層(passivation layer)內造成破裂缺陷(fracture defect)，以及潛在的焊墊至焊墊橋接(pad-to-pad bridging)。通常採用增大每一焊墊、焊墊開口及/或兩焊墊之間之空間之尺寸來處理上述問題。然而，增大每一焊墊、焊墊開口及焊墊間距(pad pitch)尺寸將導致晶片尺寸及成本的增加。
有鑑於此，特提供以下技術方案：本發明實施例提供一種積體電路晶片之實施例，積體電路晶片包含基底、頂層金屬層及焊墊。頂層金屬層位於基底上方；焊墊位於頂層金屬層中；其中焊墊之厚度較頂層金屬層之厚度小。
本發明實施例另提供一種積體電路晶片之實施例，積體電路晶片包含基底、至少一金屬間介電層、頂層金屬層、焊墊及鈍化層。至少一金屬間介電層位於基底上方；頂層金屬層位於金屬間介電層上方；焊墊位於頂層金屬層中，包含較薄中心部分及環繞較薄中心部分之較厚外緣部分；鈍化層覆蓋較厚外緣部分。
本發明實施例另提供一種積體電路晶片之實施例，積體電路晶片包含基底、頂層金屬層及至少一碗狀焊墊。頂層金屬層位於基底上方；至少一碗狀焊墊位於頂層金屬層中。
本發明之積體電路晶片之結構提供一種新型接合墊結構，可避免接合焊墊變形或開裂。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的基準。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表第一裝置可直接電氣連接於第二裝置，或透過其他裝置或連接手段間接地電氣連接至第二裝置。
以下將接合附圖來說明本發明之實施例。於說明書以及附圖中，符號“Mn ”意指製作於積體電路晶片中之頂層(topmost level)金屬層，例如鋁重分佈層，而“Mn-1 ”意指較頂層金屬層低一層之金屬層，並以此類推，其中，優選地，n介於2到10之間(n=2-10)，但並非僅限於此。符號“V”意指連接兩鄰近金屬層之介層窗(via plug)。舉例而言，V5 代表將M5 內連接至M6 之介層窗。
請參考第1圖，第1圖係根據本發明一實施例之積體電路晶片1之一部分之橫截面之示意圖。應可理解，第1圖之層或者元件並非依據實際尺寸畫出，且被修飾以使之更清楚。積體電路晶片1可包含用於合併RF器件之頂層金屬層Mn 之RF積體電路，例如電感器或者適合於RF電路之任一其他器件。用於RF器件之頂層金屬層Mn 可為鋁層、銅層(copper layer)或者銅合金層(copper alloy layer)，其中鋁層為優選方案。
頂層金屬層可降低寄生損耗(parasitic loss)，從而改善RF積體電路之品質因數(quality factor)Q。於本實施例中，頂層金屬層之厚度不小於0.5微米(micrometer)。於某些實施例中，頂層金屬層可具有不小於1.0微米之厚度。於另一些實施例中，頂層金屬層可具有不小於3.0微米之厚度。
如第1圖所示，積體電路晶片1包含基底10，例如矽基底。基底10可係為任一適合的半導體基底，例如矽鍺(SiGe)基底或者介電層上覆矽(Silicon on Insulator，SOI)基底。基本層12形成於基底10上，且包含但不限於器件層，例如金氧半(MOS)或者雙極型器件，以及至少一層間介電(inter-layer dielectric，ILD)層。為簡潔起見，基本層12內包含導線及接觸/介層窗之內連接未繪示。多個金屬間介電(inter-metal dielectric，IMD)層14、16、18及20，被提供於基本層12之上。多個IMD層14、16、18及20之每一者可包含但不限於氧化矽(silicon oxide)、氮化矽(silicon nitride)、碳化矽(silicon carbide)、氮氧化矽(silicon oxy-nitride)、低介電常數或者超低介電常數(ultra low-k，ULK)材料(例如有機(例如，芳香族碳氫化合物(SiLK))或者無機(例如，含氫的矽酸鹽(HSQ))材料)，或者上述材料之任一組合。鈍化層22位於IMD層20之至少一部分之上。鈍化層22可係為氧化矽、氮化矽、碳化矽、氮氧化矽、聚醯亞胺(polyimide)或者上述材料之任一組合或者類似物質。根據本實施例，鈍化層22具有0.5至6.0微米之厚度，但並不僅限於此。
金屬內連接40，例如Mn-2 、Vn-2 及Mn-1 ，可被分別製造於對應之IMD層14、16及18內。RF器件，例如可包含第一繞組(winding)24及鄰近於第一繞組24之第二繞組26之電感器200，被製造於位於積體電路晶片1之電感器形成區101內之頂層金屬層Mn 內。根據本發明之實施例，頂層金屬層Mn 具有不小於0.5微米之厚度h。於某些實施例中，頂層金屬層具有不小於1.0微米之厚度。於另一些實施例中，頂層金屬層具有不小於3.0微米之厚度。電感器200之第一繞組24與第二繞組26之側壁(sidewall)與頂面(top surface)可被鈍化層22覆蓋。儘管本實施例以電感器為例，本發明並不僅限於此。應可理解，其他RF器件，例如MOM電容器或者電阻器可自頂層金屬層Mn 形成。進一步，頂層金屬層Mn 可用於形成重分佈層。
根據本發明之實施例，金屬層Mn-1 可由鋁製成，其中至少一接合焊墊118形成於金屬層Mn-1 內，而金屬層Mn-2 可由傳統的銅鑲嵌(damascene)方式形成，例如單鑲嵌(single damascene)方式或者雙鑲嵌(dual damascene)方式。例如，金屬層Mn-2 可由單鑲嵌方式形成，而金屬層Mn-1 及積分介層窗層(integral via plug layer)Vn-2 可由傳統的鋁製程形成。此外，Mn-2 可由鋁形成。如本技術領域中具有通常知識者所知悉，銅鑲嵌方式提供一種不需要乾式蝕刻(dry etch)銅而形成耦接至積分介層窗之導線之解決方案。單鑲嵌或者雙鑲嵌結構可用於連接器件及/或積體電路之導線。
積體電路晶片1包含接合焊墊形成區102。至少一接合焊墊118形成於接合焊墊形成區102之內之金屬層Mn-1 中。金屬層Mn-1可薄於頂層金屬層Mn 。例如，金屬層Mn-1 可具有約0.2-1微米之厚度。開口202形成於鈍化層22及IMD層20中以暴露出接合焊墊118之上表面(top surface)之至少一部分，使得接合線30可於封裝組裝階段(package assembly stage)附著至接合焊墊118。開口202可具有約0.8-6.0微米之深度d。根據本發明之實施例，接合焊墊118優選地為鋁銲墊，但並不限於此。
可選地，支撐結構114及116可被形成於接合焊墊118之下。支撐結構114及116可係任一合適之形狀及組態(configuration)，以於導線接合製程期間為接合焊墊118提供足夠的機械支撐。例如，支撐結構114可為製造於金屬層Mn-2 內之仿真金屬板(dummy metal plate)，而支撐結構116可為多個介層窗，用於連接支撐結構114與接合焊墊118。此外，接合焊墊118下之區域112之內可形成主動電路(active circuit)、電路元件或內連接(未繪示)。
第2圖係依據本發明另一實施例之積體電路晶片1a之一部分之橫截面之示意圖，其中相似之標號表示相似之層、區域或者元件。應可理解，第2圖之層或者元件並非依據尺寸畫出，且被修飾以使之更清楚。如第2圖所示，類似地，積體電路晶片1a包含基底10。基本層12以及多個IMD層14、16、18及20，被提供於基底10之上。多個IMD層14、16、18及20之每一者可包含(但不限於)氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數或者超低介電常數材料(例如有機(例如，SiLK)或者無機(例如，HSQ)材料)，或者上述材料之任一組合。鈍化層22位於IMD層20之至少一部分之上。鈍化層22可為氧化矽、氮化矽、碳化矽、氮氧化矽、聚醯亞胺或者上述材料之任一組合或者類似物質。根據本實施例，鈍化層22具有0.5至6.0微米之厚度，但並不限於此。
金屬內連接40，例如Mn-2 、Vn-2 及Mn-1 ，可被分別製造於對應之IMD層14、16及18內。RF器件，例如可包含第一繞組24及鄰近於第一繞組24之第二繞組26之電感器200，被製造於位於積體電路晶片1a之電感器形成區101內之頂層金屬層Mn 內。根據本發明之實施例，頂層金屬層Mn 具有不小於0.5微米之厚度h。於某些實施例中，頂層金屬層Mn 具有不小於1.0微米之厚度。於另一些實施例中，頂層金屬層可具有不小於3.0微米之厚度。電感器200之第一繞組24與第二繞組26之側壁與頂面可被鈍化層22覆蓋。
積體電路晶片1a更包含接合焊墊形成區102。至少一接合焊墊214可形成於低於頂層金屬層Mn 之任一金屬層之內，例如接合焊墊形成區102之內之金屬層Mn-2 。開口302形成於鈍化層22及IMD層16、18及20中以暴露出接合焊墊214之上表面之至少一部分，使得接合線30可於封裝組裝階段附著至接合焊墊214。開口302可具有約1.0-8.0微米之深度。請注意，如第2圖所示，接合焊墊214下之支撐結構可被省略。
第3圖係依據本發明另一實施例之積體電路晶片1b之一部分之橫截面之示意圖，其中相似之標號表示相似之層、區域或者元件。如第3圖所示，積體電路晶片1b包含基底10。基本層12以及多個IMD層14、16、18及20，被提供於基底10之上。多個IMD層14、16、18及20之每一者可包含(但不限於)氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數或者超低介電常數材料(例如有機(例如，SiLK)或者無機(例如，HSQ)材料)，或者上述材料之任一組合。鈍化層22可位於IMD層20之至少一部分之上。鈍化層22可為氧化矽、氮化矽、碳化矽、氮氧化矽、聚醯亞胺或者上述材料之任一組合或者類似物質。根據本實施例，鈍化層22具有大約0.5至6.0微米之厚度，但並不限於此。
金屬內連接40，例如Mn-2 、Vn-2 、Mn-1 及Vn-1 ，可被分別製造於IMD層14、16、18及20內。於本實施例中，RF器件，例如可包含第一繞組24及鄰近於第一繞組24之第二繞組26之電感器200，可被製造於位於積體電路晶片1a之電感器形成區101內之頂層金屬層Mn 內。於某些實施例中，RDL可形成於頂層金屬層Mn 內。根據本發明之實施例，頂層金屬層Mn 可具有不小於1.0微米之厚度h。電感器200之第一繞組24與第二繞組26之側壁與頂面可被鈍化層22覆蓋。
積體電路晶片1b更包含接合焊墊形成區102。至少一接合焊墊128可形成於接合焊墊形成區102內之頂層金屬層Mn 之內。接合焊墊128可用於線接合。依據本發明之實施例，接合焊墊128及電感器200形成於同一金屬層內，亦即，頂層金屬層Mn 之內。於某些情形中，RDL導線(未繪示)亦可形成於頂層金屬層Mn 之內。開口402形成於鈍化層22中以暴露出接合焊墊128之上表面之至少一部分，使得接合線30可於封裝組裝階段附著至接合焊墊128。依據本發明之實施例，接合焊墊128係鋁焊墊，但不限於此。頂層金屬層Mn 可係鋁層，但不限於此。於積體電路晶片1b藉由銅製程製造並且接合焊墊128係鋁焊墊之情形下，金屬層Mn-1 可成為頂層銅導線層或最終之銅導線層。然而，應可理解，本實施例亦可適用於鋁積體電路晶片，其中金屬內連接係藉由鋁製程製造，從而金屬層Mn 和Mn-1 均為鋁層。
依據本發明之實施例，接合焊墊128可係為具有較薄中心部分128a及環繞較薄中心部分128a之較厚外緣部分128b之碗狀(bowl-shaped)接合焊墊。接合線30之頭部可處於由較厚外緣部分128b環繞之凹腔128c中。開口402形成之後，可進行額外之蝕刻處理或過度蝕刻(over-etching)步驟以蝕刻暴露出之接合焊墊128之一部分，從而形成凹腔128c。於某些情況下，開口402之側壁可基本上與較厚外緣部分128b之內側壁對齊。於某些情況下，開口402之側壁可較較厚外緣部分128b之內側壁更向外延伸。此外，上述製程中可不需要額外之光罩(photo mask)。應可理解，凹腔128c及接合焊墊128之碗狀結構可藉由乾式蝕刻、濕式蝕刻(wet etching)或其他適合方式形成。
依據本發明之實施例，較厚外緣部分128b具有不超過或大體上等於頂層金屬層Mn 、電感器200或RDL導線(未繪示)厚度之厚度。頂層金屬層Mn 、電感器200或RDL導線(未繪示)之厚度可係為，例如，不少於1.0微米。依據本發明之實施例，較薄中心部分128a具有不超過2微米之厚度t。依據本發明之實施例，較厚外緣部分128b之寬度w可大於0.5微米，例如，大約0.5-10微米。鈍化層22可覆蓋較厚外緣部分128b之上表面。由於接合焊墊128具有減少之厚度並進而具有減少之體積，線接合期間之焊墊變形或開裂可被避免。此外，較厚外緣部分128b可作為坝，可抵消施加於較薄中心部分128a上之壓力。
可選地，支撐結構114、116、124及126可被形成於接合焊墊128之下。支撐結構114、116、124及126可係為任一合適之形狀及組態，以於導線接合製程期間為接合焊墊128提供足夠的機械支撐。例如，支撐結構114可為製造於金屬層Mn-2 內之仿真金屬板，而支撐結構116可為多個介層窗，用於連接支撐結構114與支撐結構124，支撐結構126則可為多個介層窗，用於連接支撐結構124與接合焊墊128。此外，接合焊墊128下之區域112之內可形成主動電路、電路元件或內連接(未繪示)。於鋁製程中，支撐結構126可為多個鎢介層窗。於銅製程中，接合焊墊128可為鋁焊墊，而支撐結構126可為與接合焊墊128整體形成之多個鋁介層窗。
應可理解，儘管本發明之實施例利用線接合焊墊作為範例，本發明亦適用於其他類性之焊墊，例如凸塊(bump)焊墊、焊錫(solder)焊墊或RDL焊墊。前述RDL焊墊可為RDL覆晶(flip-chip)焊墊。本發明並不限於線接合焊墊及利用線接合焊墊之積體電路晶片。此外，於積體電路上亦存在RDL焊墊之情況下，接合焊墊128之較薄中心部分128a之厚度t可不等於RDL焊墊之最薄部分之厚度。
以上所述僅為本發明之較佳實施例，舉凡熟悉本案之人士援依本發明之精神所做之等效變化與修飾，皆應涵蓋於後附之申請專利範圍內。
1、1a、1b．．．積體電路晶片
10．．．基底
12．．．基本層
14、16、18、20．．．IMD層
22．．．鈍化層
24．．．第一繞組
26．．．第二繞組
30．．．接合線
40．．．金屬內連接
101．．．電感器形成區
102．．．接合焊墊形成區
112．．．接合焊墊下之區域
114、116、124、126．．．支撐結構
118、128、214．．．接合焊墊
200．．．電感器
202、302、402．．．開口
128a．．．較薄中心部分
128b．．．較厚外緣部分
128c．．．凹腔
d．．．開口之深度
h．．．頂層金屬層之厚度
t．．．較薄中心部分之厚度
Mn 、Mn-1 、Mn-2 ．．．金屬層
Vn-1 、Vn-2 ．．．介層窗
w．．．較厚外緣部分之寬度
第1圖係根據本發明一實施例之積體電路晶片1之一部分之橫截面示意圖。
第2圖係依據本發明另一實施例之積體電路晶片1a之一部分之橫截面之示意圖。
第3圖係依據本發明另一實施例之積體電路晶片1b之一部分之橫截面之示意圖。
1．．．積體電路晶片
10．．．基底
12．．．基本層
14、16、18、20．．．IMD層
22．．．鈍化層
24．．．第一繞組
26．．．第二繞組
30．．．接合線
40．．．金屬內連接
101．．．電感器形成區
102．．．接合焊墊形成區
112．．．接合焊墊下之區域
114、116．．．支撐結構
118．．．接合焊墊
200．．．電感器
202．．．開口
d．．．開口之深度
h．．．頂層金屬層之厚度
Mn 、Mn-1 、Mn-2 ．．．金屬層
Vn-2 ．．．介層窗

Claims (17)

  1. 一種積體電路晶片，包含：一基底；一頂層金屬層，位於該基底上方；以及一焊墊，位於該頂層金屬層中；其中該焊墊之一厚度較該頂層金屬層之一厚度小。
  2. 如申請專利範圍第1項所述之積體電路晶片，更包含一鈍化層，該鈍化層覆蓋該焊墊之一外緣部分，並且該鈍化層包含一開口，該開口暴露出該焊墊之一中心部分，其中該焊墊之該中心部分較該頂層金屬層薄。
  3. 如申請專利範圍第1項所述之積體電路晶片，更包含一鈍化層，該鈍化層覆蓋該焊墊之一外緣部分，並且該鈍化層包含一開口，該開口暴露出該焊墊之一中心部分，其中該焊墊之該中心部分具有不超過2微米之一厚度。
  4. 如申請專利範圍第1項所述之積體電路晶片，其中該焊墊係一鋁焊墊。
  5. 如申請專利範圍第1項所述之積體電路晶片，其中該頂層金屬層具有不少於1微米之一厚度。
  6. 一種積體電路晶片，包含：一基底；至少一金屬間介電層，位於該基底上方；一頂層金屬層，位於該金屬間介電層上方；一焊墊，位於該頂層金屬層中，該焊墊包含一較薄中心部分及環繞該較薄中心部分之一較厚外緣部分；以及一鈍化層，覆蓋該較厚外緣部分。
  7. 如申請專利範圍第6項所述之積體電路晶片，其中該鈍化層包含一開口，該開口暴露出該較薄中心部分。
  8. 如申請專利範圍第6項所述之積體電路晶片，其中該焊墊係一鋁焊墊。
  9. 如申請專利範圍第6項所述之積體電路晶片，其中該頂層金屬層係一重分佈層。
  10. 如申請專利範圍第6項所述之積體電路晶片，其中該頂層金屬層具有不少於1微米之一厚度，且該焊墊之該較厚外緣部分之一厚度不超過該頂層金屬層之一厚度。
  11. 如申請專利範圍第6項所述之積體電路晶片，其中該焊墊之該較薄中心部分具有不超過2微米之一厚度。
  12. 一種積體電路晶片，包含：一基底；一頂層金屬層，位於該基底上方；以及至少一碗狀焊墊，位於該頂層金屬層中。
  13. 如申請專利範圍第12項所述之積體電路晶片，其中該碗狀焊墊包含一較薄中心部分及環繞該較薄中心部分之一較厚外緣部分。
  14. 如申請專利範圍第13項所述之積體電路晶片，其中該較厚外緣部分之一厚度大體上與該頂層金屬層之一厚度相同。
  15. 如申請專利範圍第12項所述之積體電路晶片，其中該碗狀焊墊係一鋁焊墊。
  16. 如申請專利範圍第12項所述之積體電路晶片，其中該頂層金屬層係一重分佈層。
  17. 如申請專利範圍第12項所述之積體電路晶片，其中該頂層金屬層具有不少於1微米之一厚度。
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