JP2006005202A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】 外部接続端子を構成するボンディングパッド24と、ボンディングパッド24の下面に、少なくとも二層の銅膜44,16と、前記隣接する銅膜44,16同士を接続するように設けられる接続ビア18から形成されるボンディングパッド下部領域48と、ボンディングパッド下部領域48を取り囲むように銅膜および隣接する銅膜同士を接続する環状導体より構成されるシールリング42と、シールリング42の外側においてボンディングパッド24に接続される配線26と、を含む。
【選択図】 図1
Description
あるいは、ボンディングパッド下部領域の前記隣接する銅膜の各々が平面的に設けられており、銅膜がパッシベーション膜の開口領域よりも大きくなるようにしてもよい。
なお、図面の説明においては、同一要素には同一符号を付し、重複する説明を省略する。
図1は、本発明の第一の実施形態に係る半導体装置の要部を示す図であり、図2(a)は本実施形態における層間絶縁膜28の上面図であり、図2(b)は本実施形態における層間絶縁膜32の上面図であり、図2(c)は本実施形態における層間絶縁膜34の上面図である。
図3および図4は、本実施形態に係る半導体装置の製造工程を示す図である。
絶縁膜12(図3(a))上に、CVD(chemical vapor deposition)法により全面に膜厚が10〜50nmのシリコン窒化膜、300〜2000nmのSiOCなどの低誘電率膜からなる層間絶縁膜34を形成した後、フォトリソグラフィ技術を使用したプラズマエッチング法により、第2銅膜を形成するための溝を形成する。次に、スパッタ法により全面に膜厚が10〜50nmのタンタル膜とタンタル窒化膜との積層膜からなるバリアメタル膜を形成した後、続けて50〜300nmの銅シード膜を形成し、めっき法により銅膜を形成して、溝内に完全に銅膜を埋め込むようにする。続いて、CMP法により不要なバリアメタル膜および銅膜を除去して、バリアメタル膜74および第2銅膜16が形成される(図3(b))。
図5は、本発明の第二の実施形態に係る半導体装置の要部を示す図である。
本実施形態に係る半導体装置10は、図1の第一の実施形態において層間絶縁膜28に設けた第1銅膜44およびシールリング銅膜46を連続して形成して、一つの第1銅膜22とした以外は、第一の実施形態に係る半導体装置40と同様の構成を有する。
図6は、本発明の第三の実施形態に係る半導体装置の要部を示す図である。
本実施形態に係る半導体装置90は、第一の実施形態に係る半導体装置40の下側に積層配線80が設けられ、さらに最下層の層間絶縁膜82に接するように半導体基板としてのシリコン基板86が設けられている。このシリコン基板86においては、外部接続端子となる半導体装置40の開口部の直下に電子素子であるMOS(metal oxide semiconductor)84を配置することができる。
16 第2銅膜
18 接続ビア
20 シールリング
22 第1銅膜
24 ボンディングパッド
26 配線
30 パッシベーション膜
34 ボンディングパッド下部領域
40 半導体装置
42 シールリング
44 第1銅膜
46 シールリング銅膜
48 ボンディングパッド下部領域
Claims (9)
- 半導体基板上に外部接続端子を有する半導体装置において、
前記外部接続端子を構成するボンディングパッドと、
前記ボンディングパッドの下面に、少なくとも二層の銅膜と、前記隣接する銅膜同士を接続するように設けられる接続ビアから形成されるボンディングパッド下部領域と、
前記ボンディングパッド下部領域を取り囲むように前記銅膜および前記隣接する銅膜同士を接続する環状導体より構成されるシールリングと、
前記シールリングの外側において前記ボンディングパッドに接続される引き出し配線と、
を含む半導体装置。 - 請求項1に記載の半導体装置において、
前記シールリングが占める領域よりも内側の領域に開口領域を有するパッシベーション膜をさらに含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ボンディングパッド下部領域の前記隣接する銅膜の各々が平面的に設けられていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記ボンディングパッド下部領域の前記隣接する銅膜の各々が平面的に設けられており、
前記銅膜が上記パッシベーション膜の開口領域よりも大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記銅膜の最下層が前記ボンディングパッド下部領域と前記シールリングとを含み、当該シールリングで囲まれた領域をカバーするように形成されることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記引き出し配線が、前記シールリングの外側において前記ボンディングパッドの前記ボンディングパッド下部領域に直接接する平坦領域の端部に直接接続されることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ボンディングパッド下部領域の銅膜のうち、ボンディングパッドに直接接する銅膜が、前記接続ビアに接続される部分と、前記シールリングに接続される部分とで不連続に形成されることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記ボンディングパッド下部領域における銅膜および接続ビアは、シングルダマシン法またはデュアルダマシン法により形成されることを特徴とする半導体装置。 - 請求項1〜8のいずれかに記載の半導体装置と、
半導体基板と、
前記ボンディングパッド下部領域と、前記半導体基板との間に設けられる電子素子と、
を含む半導体装置。
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US11/153,619 US7301244B2 (en) | 2004-06-18 | 2005-06-16 | Semiconductor device |
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Cited By (9)
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JP2006332533A (ja) * | 2005-05-30 | 2006-12-07 | Fujitsu Ltd | 半導体素子及びその製造方法 |
JP2007299900A (ja) * | 2006-04-28 | 2007-11-15 | Kawasaki Microelectronics Kk | 半導体装置と半導体装置の絶縁破壊防止方法 |
US7696081B2 (en) | 2007-01-31 | 2010-04-13 | Renesas Technology Corp. | Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns |
WO2010041365A1 (ja) * | 2008-10-10 | 2010-04-15 | パナソニック株式会社 | 半導体装置 |
JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
JP2011222963A (ja) * | 2010-01-15 | 2011-11-04 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US9093432B2 (en) | 2011-09-23 | 2015-07-28 | Sanken Electric Co., Ltd. | Semiconductor device |
JP2017011110A (ja) * | 2015-06-23 | 2017-01-12 | ローム株式会社 | 半導体集積回路および選択検出回路 |
WO2018070111A1 (ja) * | 2016-10-14 | 2018-04-19 | 株式会社デンソー | 半導体装置 |
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DE10337569B4 (de) * | 2003-08-14 | 2008-12-11 | Infineon Technologies Ag | Integrierte Anschlussanordnung und Herstellungsverfahren |
CN100413066C (zh) * | 2005-11-30 | 2008-08-20 | 中芯国际集成电路制造(上海)有限公司 | 低k介电材料的接合焊盘和用于制造半导体器件的方法 |
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CN103779234A (zh) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件封装结构以及制备方法 |
TWI570822B (zh) * | 2014-01-24 | 2017-02-11 | 矽品精密工業股份有限公司 | 基板結構及其製法 |
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JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001015516A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001298029A (ja) * | 1999-12-16 | 2001-10-26 | Lucent Technol Inc | ストレスを減少してパッドの下に回路を入れることができるようにするためのデュアル食刻ボンドパッド構造およびそれを形成するための方法 |
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JP2001267323A (ja) | 2000-03-21 | 2001-09-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4555540B2 (ja) * | 2002-07-08 | 2010-10-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001015516A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001298029A (ja) * | 1999-12-16 | 2001-10-26 | Lucent Technol Inc | ストレスを減少してパッドの下に回路を入れることができるようにするためのデュアル食刻ボンドパッド構造およびそれを形成するための方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006332533A (ja) * | 2005-05-30 | 2006-12-07 | Fujitsu Ltd | 半導体素子及びその製造方法 |
JP2007299900A (ja) * | 2006-04-28 | 2007-11-15 | Kawasaki Microelectronics Kk | 半導体装置と半導体装置の絶縁破壊防止方法 |
US7696081B2 (en) | 2007-01-31 | 2010-04-13 | Renesas Technology Corp. | Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns |
US8084279B2 (en) | 2007-01-31 | 2011-12-27 | Renesas Electronics Corporation | Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns |
WO2010041365A1 (ja) * | 2008-10-10 | 2010-04-15 | パナソニック株式会社 | 半導体装置 |
JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
JP2011222963A (ja) * | 2010-01-15 | 2011-11-04 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US9093432B2 (en) | 2011-09-23 | 2015-07-28 | Sanken Electric Co., Ltd. | Semiconductor device |
JP2017011110A (ja) * | 2015-06-23 | 2017-01-12 | ローム株式会社 | 半導体集積回路および選択検出回路 |
WO2018070111A1 (ja) * | 2016-10-14 | 2018-04-19 | 株式会社デンソー | 半導体装置 |
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US7301244B2 (en) | 2007-11-27 |
JP4528035B2 (ja) | 2010-08-18 |
US20050280149A1 (en) | 2005-12-22 |
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