CN113517209A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN113517209A
CN113517209A CN202010279542.2A CN202010279542A CN113517209A CN 113517209 A CN113517209 A CN 113517209A CN 202010279542 A CN202010279542 A CN 202010279542A CN 113517209 A CN113517209 A CN 113517209A
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Prior art keywords
conductive structure
substrate
semiconductor
chip
conductive
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CN202010279542.2A
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Inventor
吕开敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202010279542.2A priority Critical patent/CN113517209A/zh
Priority to US17/432,191 priority patent/US12033933B2/en
Priority to EP21773255.1A priority patent/EP3933898A4/en
Priority to PCT/CN2021/079980 priority patent/WO2021203900A1/zh
Publication of CN113517209A publication Critical patent/CN113517209A/zh
Pending legal-status Critical Current

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Abstract

该发明涉及半导体封装技术领域，公开了一种半导体结构及其形成方法。该方法包括：提供芯片，所述芯片表面具有互连结构，所述互连结构顶端具有暴露的可熔部分；提供基板，所述基板表面形成有导电结构；图形化所述导电结构，使所述导电结构的边缘具有凸起部；将所述芯片与所述基板组合，使得所述可熔部分和所述导电结构初步机械结合，然后将所述可熔部分加热到所述可熔部分的回流温度，将所述可熔部分与所述导电结构热压结合。本发明主要针对基板的导电结构进行改进，新的结构设计对金属焊料可以引流，避免芯片与半导体基板在后续的塑封阶段出现产品失效的问题，同时加强导电结构与基板之间焊接金属结合力。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体封装技术领域，具体涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器是一种广泛应用的半导体存储器。随着半导体集成电路器件特征尺寸的不断缩小，对半导体制造技术的要求也在不断提高。现有的半导体封装技术存在一定的局限，就需要我们去研发先进的工艺，提升公司竞争力。
在现有的半导体封装技术中，导电凸块与半导体基板间隔是使用塑封料填充，由于塑封料的填充性或致密性的材料属性，以及芯片与基板的金属互连结构使用焊料的润湿性问题，导致焊接作用较差，进而导致在后续的塑封阶段出现产品失效。
因此，如何在特征尺寸缩小的半导体的封装工艺中，避免芯片与半导体基板在后续的塑封阶段出现产品失效的问题，同时加强导电结构与基板之间焊接金属结合力，是我们目前亟待解决的技术问题。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，能够避免芯片与半导体基板在后续的塑封阶段出现产品失效的问题，同时加强导电结构与基板之间焊接金属结合力。
为解决上述技术问题，本发明中提供了一种半导体结构的形成方法，其特征在于：
提供芯片，所述芯片表面具有互连结构，所述互连结构顶端具有暴露的可熔部分；
提供基板，所述基板表面形成有导电结构；
图形化所述导电结构，使所述导电结构的边缘具有凸起部；
将所述芯片与所述基板组合，使得所述可熔部分和所述导电结构初步机械结合，然后将所述可熔部分加热到所述可熔部分的回流温度，将所述可熔部分与所述导电结构热压结合。
可选的，所述图形化所述导电结构的步骤包括：在所述导电结构上方形成第一掩膜材料层，所述第一掩膜材料层暴露出所述导电结构的边缘；在所述第一掩膜材料层中沉积阻挡材料层；去除所述第一掩膜材料层，于所述导电结构的边缘形成所述凸起部。
可选的，所述图形化所述导电结构的步骤包括：在所述导电结构上方形成第二掩膜材料层，所述第二掩膜材料层至少覆盖所述导电结构的边缘部分；沿所述第二掩膜材料层刻蚀所述导电结构，于所述导电结构的边缘形成所述凸起部。
可选的，所述阻挡材料层与所述导电结构的材质相同或不同。
本发明的的技术方案还提供一种半导体结构，包括：
基板，所述基板表面形成有导电结构，所述导电结构的边缘具有凸起部；
芯片，所述芯片表面具有互连结构；所述互连结构与所述导电结构相向嵌合。
可选的，所述导电结构的中心部分具有弧形曲面凹槽，所述互连结构的顶表面至少部分与所述弧形曲面凹槽嵌合。
可选的，所述导电结构的边缘具有凸起部，所述凸起部的形状为矩形、三角形或弧形中一种。
可选的，还包括：所述互连结构顶端具有可熔部分；所述可熔部分与所述导电结构相向嵌合。
可选的，所述导电结构的材质与所述可熔部分的材质不同。
可选的，所述凸起部的高度至少大于或等于所述可熔部分的三分之一。
可选的，所述导电结构的边缘具有两个或两个以上的所述凸起部，各所述凸起部之间存在间隔。
本发明的优点在于，相较于现有的半导体封装工艺，本发明主要针对基板的导电结构进行改进，新的结构设计对金属焊料可以引流，避免后续封装技术中金属焊料沿着图案方向扩散，避免导电结构与半导体基板间隔出现漏电流、接触不良短路、产品失效等问题，同时金属焊料与导电结构有三个面进行焊接，进一步加强焊接金属间的结合力，从而提高半导体封装工艺的良品率。
附图说明
图1至图4为本发明的一种具体实施方式中的半导体结构示意图；
图5为现有技术中的半导体结构示意图；
图6A、图6B、图6C为本发明的一种具体实施方式中的半导体结构截面示意图。
附图标记：
100：半导体基板；200：导电结构；300：第一掩膜材料层；400：可熔部分；201：互连结构；110：芯片；500：塑封料。
具体实施方式
以下结合附图和具体实施方式对本发明提出的半导体结构及其形成方法作进一步详细说明。
请参阅图1为本发明的一种具体实施方式中的半导体结构示意图。
具体地说，提供一基板100，基板100表面形成有间隔排列的导电结构200。
在半导体封装技术中，半导体基板100的材料多为印刷电路板。比如，可以采用氮化铝基板、铝碳化硅基板等。基板100表面形成有间隔排列的导电结构200。在本实施方式中，导电结构200可以是焊盘，也可以是迹线。在半导体封装技术中，导电结构200的材料包括：铜、镍、金、钽、钴、铟、钒、氮化钛等中至少一种。
本技术领域人员可以理解，现有的半导体封装技术中，导电结构200与半导体基板100间隔是使用的塑封料500，塑封料500是焊接后在注入的，也是说如果之前的焊接不够牢固，在后期注入塑封料500塑封时会导致焊接点出现接触不良，或者塑封的高温导致焊料融化，相邻的结构间耦合，出现短路。
可以参阅对比图4与图5，图4为本实施方式，图5为现有技术方案。金属焊料一般为锡合金。其中，金属焊接材料即为图4、图5中标号：可熔部分400。可熔部分400位于芯片110上互连结构201顶端，用于将可熔部分400与导电结构200热压结合，以形成芯片110与基板100封装组合。进一步的，由于导电结构200在可熔部分400的热熔温度下相对不熔，因此，可熔部分400与导电结构200的材质不相同。
图形化导电结构200的具体步骤包括如下：
请参阅图2为先在导电结构200的表面沉积第一掩膜材料层300，进行刻蚀处理。进一步的，请参阅图3为对导电结构200进行图形化刻蚀，使导电结构200的边缘具有凸起部。
在导电结构200上方形成第一掩膜材料层300，第一掩膜材料层300暴露出导电结构的边缘。在第一掩膜材料层300中沉积阻挡材料层(未示出)；去除第一掩膜材料层300，于导电结构的边缘形成凸起部。其中，阻挡材料层(未示出)与导电结构200的材质可以相同也可以不同。阻挡材料层的材质可以是镍、金、钽、钴、铟、氮化钛、钒等金属中至少一种，也可以是与导电结构200润湿性比较好的介电材料。
进一步的，在导电结构200上方形成第二掩膜材料层(未示出)，第二掩膜材料层至少覆盖导电结构200的边缘部分；沿第二掩膜材料层刻蚀导电结构200，于导电结构200的边缘形成凸起部。
具体地说，在本实施方式中，具体沉积掩膜层的方式多种多样，比如可以使用：化学气相沉积，将一种或数种物质的气体，以某种方式激活后，在衬底表面发生化学反应，并沉积出所需固体薄膜的生长技术。物理气相沉积，利用某种物理过程实现物质的转移，即将原子或分子转移到硅衬底表面，并沉积成薄膜的技术。还有旋涂法、电镀法等。例如，本实施方式中，掩膜层采用化学气相沉积的方式，在导电结构200的表面，沉积预设厚度分布的掩膜层。可以单独运用控制导入气流的流速、控制导入气流的流量、控制沉积时长或控制沉积温度的控制手段，通过提高对气流和温度的控制精度，可以确保所有原子沉积时排列整齐，形成单晶层，最终在导电结构200的表面得到一层厚度均匀的掩膜层。
上述多层掩膜层的沉积与刻蚀，可以使导电结构200能够刻蚀出更好的效果。同时，设置图案于掩膜层，根据图案对导电结构200进行图形化刻蚀。根据实际工艺中的需求，比方，请参阅图6A-6C中刻蚀后导电结构200的结构截面示意图，导电结构200的中心部分形成弧形曲面凹槽，于导电结构200的边缘形成凸起部。其中，刻蚀后导电结构200的两侧边缘具有凸起部，凸起部的形状为矩形、三角形或弧形中一种。因此，可以将掩膜层的图案设置为矩形，圆形等。
根据上述步骤中设置于第一掩膜材料层300的图案，对导电结构200进行图形化刻蚀，使导电结构200的边缘具有凸起部。在半导体制造中有两种基本的刻蚀工艺：干法刻蚀和湿法刻蚀。干法刻蚀是利用气态中产生的等离子体，通过光刻而开出的掩蔽层窗口，与暴露于等离子体中的硅片进行物理和化学反应，刻蚀掉硅片上暴露的表面材料的一种工艺技术方法。干法刻蚀被用于先进电路的小特征尺寸精细刻蚀中。干法刻蚀是指以气体为主要媒体的刻蚀技术，半导体材料不需要液体化学品或冲洗，半导体材料在干燥的状态下进出系统。干法刻蚀相对于湿法刻蚀，在刻蚀特性上既表现出化学的等方性(指纵横两个方向上均存在刻蚀)，又表现出物理的异方性(指单一纵向的刻蚀)。
在本实施方式中，可以采用干法刻蚀工艺将导电结构200进行刻蚀。具体的步骤包括：将上述半导体结构送至反应室，并由真空系统将内部压力降低。在真空建立起来后，将反应室内充入反应气体。对于钨、铜等相关集成电路导电材料的刻蚀，反应气体一般使用氟化氮和氧气的混合剂。或者也可以采用其他含氟气体作为刻蚀气体，比如四氟化碳，六氟化硫，三氟化氮等。电源通过在反应室中的电极创造了一个射频电场。能量场将混合气体激发成等离子体态。在激发状态，反应氟进行刻蚀，并将其转化为挥发性成分由真空系统排出。
在半导体封装技术中，根据实际工艺中的需求，导电结构200的中心部具有弧形曲面凹槽，互连结构201的顶表面至少部分与弧形曲面凹槽嵌合。其中，刻蚀后导电结构200的两侧边缘具有凸起部，凸起部的形状为矩形、三角形或弧形中一种。请参阅图6A-6C中刻蚀后导电结构200的结构截面示意图，比如：图6A为刻蚀后导电结构200的两侧边缘凸起的形状为矩形；图6B为刻蚀后导电结构200的两侧边缘凸起的形状为三角形；图6C为刻蚀后导电结构200的两侧边缘凸起的形状为弧形。因此，根据设置于掩膜层的图案刻蚀出相应的效果。进一步的，在实践中，一般第一掩膜材料层300形成凸起部是图6A的形状。至于其他结构(如：凸起部为图6B或6C的形状)是需要改变掩膜形状或者在形成图6A的形状进一步采用例如倾斜离子注入工艺处理后再刻蚀等方式才能获得的。同时，上述多层掩膜层的沉积与刻蚀，可以使导电结构200能够刻蚀出更好的效果。
进一步的，凸起部的高度至少大于或者等于可熔部分400高度的三分之一。导电结构200的边缘具有两个或两个以上的凸起部，各所述凸起部之间存在间隔。因此，可以确保有足够的结合力和引流能力。
因此，本实施方式，相较于现有的半导体封装工艺，主要针对基板的导电结构进行改进新的结构设计相当于将导电结构重新刻蚀，通过刻蚀导电结构中心部分，使边缘与中心出现高度差，新的结构设计对金属焊料进行引流，可以避免后续封装技术中金属焊料沿着耦合方向扩散，可以避免金属焊料与旁边材料进行接触，也可以避免后续高温加热情况下金属焊料的融化流向周围，从而避免相邻导电结构之间出现短路；基板与芯片之间出现漏电流、接触不良；造成产品失效等问题。同时金属焊料与导电结构有三个面进行焊接，进一步加强焊接金属间的结合力，从而提高半导体封装工艺的良品率。
请参阅图4为提供芯片110，芯片110表面具有互连结构201。将芯片100与基板100组合，基板100表面具有刻蚀后的导电结构200，进而将刻蚀后的导电结构200与互连结构201、芯片110进行封装工艺。
具体地说，芯片110表面具有互连结构201，互连结构201顶端具有暴露的可熔部分400。在本实施方式中，定义可熔部分400是为了区别于导电结构200。可熔部分400为金属焊料，一般为锡合金等。由于导电结构200在可熔部分400的热熔温度下相对不熔，因此，可熔部分400与导电结构200的材质不相同。
将可熔部分400和导电结构200初步机械结合，然后将可熔部分400加热到可熔部分400的回流温度，将可熔部分400与导电结构200热压结合。
可以对比图4与图5，图4为本实施方式，图5为现有技术方案。本技术领域人员可以理解，现有的半导体封装技术中，导电结构200与半导体基板100间隔是使用的塑封料500，由于材料的填充性或致密性等材料属性，当导电结构200与芯片110上互连结构201焊接时，导致相邻的金属焊接材料之间出现漏电流、接触不良短路、产品失效等问题。
因此，本实施方式，相较于现有的半导体封装工艺，主要针对基板的导电结构进行改进，新的结构设计相当于将导电结构重新刻蚀，通过刻蚀导电结构中心部分，使边缘与中心出现高度差，新的结构设计对金属焊料进行引流，可以避免后续封装技术中金属焊料无序扩散，从而避免相邻导电结构之间短路；。同时金属焊料与导电结构有三个面进行焊接，进一步加强焊接金属间的结合力，避免基板与芯片之间出现漏电流、接触不良等问题，从而提高半导体封装工艺的良品率。
本发明的具体实施方式还提供一种半导体结构。
请参阅图4为本发明的一种具体实施方式中的半导体结构示意图。
半导体结构具体包括：基板100，导电结构200。
基板100表面形成有间隔排列的导电结构200；导电结构200位于基板100表面；进一步的，导电结构200经刻蚀后，为表面中心向下凹陷、两侧边缘凸起的导电结构200。进一步的，凸起部的高度至少大于或者等于可熔部分400高度的三分之一。导电结构200的边缘具有两个或两个以上的凸起部，各所述凸起部之间存在间隔。因此，可以确保有足够的结合力和引流能力。
具体地说，在半导体封装技术中，半导体基板100的材料多为印刷电路板。比如，可以采用氮化铝基板、铝碳化硅基板等。基板100表面形成有间隔排列的导电结构200。在本实施方式中，导电结构200可以是焊盘，也可以是迹线。在半导体封装技术中，导电结构200的材料包括：铜、镍、金、钽、钴、铟、钒、氮化钛等中至少一种。
根据实际工艺中的需求，请参阅图6A-C中刻蚀后导电结构200的结构示意图，比如：刻蚀后导电结构200的两侧边缘凸起的形状包括：矩形、三角形、弧形。图6A为刻蚀后导电结构200的两侧边缘凸起的形状为矩形；图6B为刻蚀后导电结构200的两侧边缘凸起的形状为三角形；图6C为刻蚀后导电结构200的两侧边缘凸起的形状为弧形。因此，根据设置于掩膜层的图案刻蚀出相应的效果。进一步的，在实践中，一般第一掩膜材料层300形成凸起部是图6A的形状。至于其他结构(如：凸起部为图6B或6C的形状)是需要改变掩膜形状或者在形成图6A的形状进一步采用例如倾斜离子注入工艺处理后再刻蚀等方式才能获得的。
提供芯片110，芯片110表面具有互连结构201。将芯片100与基板100组合，基板100表面具有刻蚀后的导电结构200，进而将刻蚀后的导电结构200与互连结构201、芯片110进行封装工艺。
具体地说，芯片110表面具有互连结构201，互连结构201顶端具有暴露的可熔部分400。在本实施方式中，定义可熔部分400是为了区别于导电结构200。可熔部分400为金属焊料，一般为锡合金。由于导电结构200在可熔部分400的热熔温度下相对不熔，因此，可熔部分400与导电结构200的材质不相同。
将可熔部分400和导电结构200初步机械结合，然后将可熔部分400加热到可熔部分400的回流温度，将可熔部分400与导电结构200热压结合。
可以对比图4与图5，图4为本实施方式，图5为现有技术方案。
本技术领域人员可以理解，现有的半导体封装技术中，导电结构200与半导体基板100间隔是使用的塑封料500，塑封料500是焊接后在注入的，也是说如果之前的焊接不够牢固，在后期注入塑封料500塑封时会导致焊接点出现接触不良，或者塑封的高温导致焊料融化，相邻的结构间耦合，出现短路。因此，由于材料的填充性或致密性等材料属性，相邻的金属焊接材料之间可能会出现漏电流、接触不良、短路等问题，造成产品失效。
因此，本实施方式，相较于现有的半导体封装工艺，主要针对基板的导电结构进行改进，新的结构设计相当于将导电结构重新刻蚀，通过刻蚀导电结构中心部分，使边缘与中心出现高度差，对金属焊料进行引流，可以避免后续封装技术中金属焊料无序扩散，避免相邻导电结构之间出现短路；同时金属焊料与导电结构有三个面进行焊接，进一步加强焊接金属间的结合力，防止基板与芯片之间出现漏电流、接触不良等问题，从而提高半导体封装工艺的良品率。
以上仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种半导体结构的形成方法，其特征在于，包括：
提供芯片，所述芯片表面具有互连结构，所述互连结构顶端具有暴露的可熔部分；
提供基板，所述基板表面形成有导电结构；
图形化所述导电结构，使所述导电结构的边缘具有凸起部；
将所述芯片与所述基板组合，使得所述可熔部分和所述导电结构初步机械结合，然后将所述可熔部分加热到所述可熔部分的回流温度，将所述可熔部分与所述导电结构热压结合。
2.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述图形化所述导电结构的步骤包括：在所述导电结构上方形成第一掩膜材料层，所述第一掩膜材料层暴露出所述导电结构的边缘；
在所述第一掩膜材料层中沉积阻挡材料层；
去除所述第一掩膜材料层，于所述导电结构的边缘形成所述凸起部。
3.根据权利要求1所述的半导体结构的形成方法，其特征在于，所述图形化所述导电结构的步骤包括：在所述导电结构上方形成第二掩膜材料层，所述第二掩膜材料层至少覆盖所述导电结构的边缘部分；
沿所述第二掩膜材料层刻蚀所述导电结构，于所述导电结构的边缘形成所述凸起部。
4.根据权利要求2所述的半导体结构的形成方法，其特征在于，所述阻挡材料层与所述导电结构的材质相同或不同。
5.一种半导体结构，其特征在于，包括：
基板，所述基板表面形成有导电结构，所述导电结构的边缘具有凸起部；
芯片，所述芯片表面具有互连结构；所述互连结构与所述导电结构相向嵌合。
6.根据权利要求5所述的半导体结构，其特征在于，所述导电结构的中心部具有弧形曲面凹槽，所述互连结构的顶表面至少部分与所述弧形曲面凹槽嵌合。
7.根据权利要求5所述的半导体结构，其特征在于，所述凸起部的形状为矩形、三角形或弧形中一种。
8.根据权利要求5所述的半导体结构，其特征在于，所述互连结构顶端具有可熔部分；所述可熔部分与所述导电结构相向嵌合。
9.根据权利要求8所述的半导体结构，其特征在于，所述凸起部的高度至少大于或等于所述可熔部分的三分之一。
10.根据权利要求5所述的半导体结构，其特征在于，所述导电结构的边缘具有两个或两个以上的所述凸起部，各所述凸起部之间存在间隔。
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