US20050142835A1 - Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed - Google Patents

Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed Download PDF

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US20050142835A1
US20050142835A1 US11068676 US6867605A US2005142835A1 US 20050142835 A1 US20050142835 A1 US 20050142835A1 US 11068676 US11068676 US 11068676 US 6867605 A US6867605 A US 6867605A US 2005142835 A1 US2005142835 A1 US 2005142835A1
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solder
mask
conductive
material
contact
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US11068676
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Michael Ball
Chad Cobbley
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Ball Michael B.
Cobbley Chad A.
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    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/11472Profile of the lift-off mask
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
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    • H01L2924/01006Carbon [C]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033Arsenic [As]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01078Platinum [Pt]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0125Shrinkable, e.g. heat-shrinkable polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0041Etching of the substrate by chemical or physical means by plasma etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions ; Methods of application thereof

Abstract

A method of forming conductive structures on the contact pads of a substrate, such as a semiconductor die or a printed circuit board. A solder mask is secured to an active surface of the substrate. Apertures through the solder mask are aligned with contact pads on the substrate. The apertures may be preformed or formed after a layer of the material of which the solder mask is comprised has been disposed on the substrate. Conductive material is disposed in and shaped by the apertures of the solder mask to form conductive structures in communication with the contact pads exposed to the apertures. Sides of the conductive structures are exposed through the solder mask, either by removing the solder mask from the substrate or by reducing the thickness of the solder mask. The present invention also includes semiconductor devices formed during different stages of the method of the present invention.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation of application Ser. No. 09/736,795, filed Dec. 14, 2000, now U.S. Pat. No. 6,861,345, issued Mar. 1, 2005, which is a divisional of application Ser. No. 09/385,584, filed Aug. 27, 1999, pending.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to methods of disposing conductive structures, such as solder bumps, onto the surfaces of semiconductor devices. In particular, the present invention relates to methods of employing solder masks made of dielectric materials to substantially simultaneously dispose a plurality of solder bumps onto a semiconductor device. More specifically, the present invention relates to conductive structure disposition methods wherein the dielectric solder mask is removable from the semiconductor device or may otherwise be altered during or subsequent to forming the conductive structures to expose the sides, or peripheries, of the conductive structures.
  • [0004]
    2. Background of Related Art
  • [0005]
    Conventionally, metal masks were used to selectively control the application of solder balls to the contact pads through which a semiconductor device would electrically communicate with other devices external thereto. Metal masks have typically been made from molybdenum, which exhibits long-term dimensional stability at high temperature and may be reused.
  • [0006]
    Dry films have also been used as solder masks. Dry films, which are typically a thin layer of semisolid material that is disposed on a carrier film, may be laminated to the surface of a substrate, such as a printed circuit board (“PCB”), by heat and vacuum lamination processes. The dry film may then be patterned by exposing selected regions to ultraviolet (“UV”) light, which hardens the regions of the dry film that are to remain and be used as the solder mask. The uncured regions are removed from the substrate by use of a suitable solvent, such as 1,1,1,-trichloroethane, and the remaining portions of the dry film cured by heat or high-energy UV irradiation.
  • [0007]
    In addition to metal solder masks and dry films, polymers, such as acrylates and epoxies, have also been used as masks for applying solder to semiconductor device substrates, such as printed circuit boards and bare semiconductor devices. Polymers are typically applied to the surface of the substrate, patterned to expose the contact pads of the substrate through the polymer, and cured. Polymers may be applied to the surface of a substrate by screen printing, which also patterns the polymer, by curtain coating, by roller coating, or by the use of electrostatic spray. The patterning and curing processes employed with polymeric solder masks depend upon the type of polymer used as the solder mask. For example, photoimaging or mask and etch techniques may be employed to pattern the polymer, while the polymer may be cured by heat (for epoxies) or ultraviolet irradiation (for acrylates).
  • [0008]
    Solder may be applied to metal, dry film, or polymeric solder masks by known processes, such as by applying solder balls to the apertures of the solder mask, forcing solder paste into the apertures of the solder mask, by casting, or by ultrasonic dipping, wherein the masked substrate is immersed in molten solder, which then fills the apertures of the solder mask.
  • [0009]
    Following the deposition of solder to contact pads through a metal mask, the apertures of the metal mask must be larger than the cross-section of the solder bumps formed therethrough in order to facilitate removal and reuse of the metal solder mask. While dry film and polymeric solder masks dictate the contact location of a substrate upon which solder bumps are formed or applied, dry film and polymeric solder masks are typically very thin in order to facilitate their retention on or their removal from the substrate. Thus, the apertures of dry film and polymeric solder masks may not define the configuration of solder bumps; rather, dry film and polymeric solder masks are typically used to position spherical solder bumps on the contact pads of a substrate.
  • [0010]
    Spherical solder bumps and other configurations of relatively short, wide solder bumps may stress the adjacent semiconductor device. Such stress may be caused, for example, by the different coefficients of thermal expansion of the solder and the adjacent substrate or by conformational changes as the solder bump solidifies.
  • [0011]
    Thin polymeric films, such as adhesive tapes, have also been applied to printed circuit boards to be used as solder masks. U.S. Pat. No. 5,388,327 (hereinafter “the '327 Patent”), which issued to Trabucco on Feb. 14, 1995, and U.S. Pat. Nos. 5,497,938 (hereinafter “the '938 Patent”) and 5,751,068 (hereinafter “the '068 Patent”), which issued to McMahon et al. on Mar. 12, 1996, and May 12, 1998, respectively, disclose adhesive films that carry preformed conductive bumps. The conductive bumps carried by the film are aligned with corresponding contact pads of a printed circuit board, the film is adhered to the printed circuit board, the conductive bumps are each secured to their corresponding contact pad, and the film is removed from the printed circuit board with a solvent. The use of such a carrier film is, however, somewhat undesirable since, during application of the film to the printed circuit board, air pockets may form between the film and the printed circuit board and a sufficient contact between one or more of the conductive bumps and their corresponding contact pads may not be established. Thus, the conductive bumps may not secure sufficiently to their corresponding contact pads on the printed circuit board to establish an adequate electrical connection with the contact pads. Moreover, the use of such an adhesive film to facilitate the disposal of solder bumps on a bare or minimally packaged semiconductor device is not disclosed in the '327 Patent, the '938 Patent, or the '068 Patent.
  • [0012]
    U.S. Pat. Nos. 5,442,852 (hereinafter “the '852 Patent”), 5,504,277 (hereinafter “the '277 Patent”), and 5,637,832 (hereinafter “the '832 Patent”), which issued to Danner on Aug. 22, 1995, Apr. 2, 1996, and Jun. 10, 1997, respectively, each disclose a solder mask that includes an adhesive film with an array of holes therethrough. In use, the holes through the film are aligned with corresponding contact pads of a printed circuit board. Solder balls are then disposed on the contact pads exposed through the holes of the film. The solder mask, however, has a thickness that is significantly less than the height of the solder balls. Thus, the adhesive film solder mask disclosed in the '852, '277, and '832 Patents may be employed to position the solder balls in desired locations, but does not include apertures that define the shape of the solder. Moreover, the use of such an adhesive film to facilitate the disposal of solder bumps on a bare or minimally packaged semiconductor device is not disclosed in the '852, '277, or '832 Patents.
  • [0013]
    Thus, there is a need for a reliable method of efficiently applying conductive structures, such as solder bumps, of desired configuration to the contact pads of semiconductor device substrates through a solder mask. There is also a need for a solder mask through which conductive structures of desired configuration can be reliably and efficiently applied to the contact pads of semiconductor device substrates, including bare or minimally packaged semiconductor dice.
  • SUMMARY OF THE INVENTION
  • [0014]
    The present invention includes a method of disposing solder bumps on a substrate, such as a bare or minimally packaged semiconductor device or a printed circuit board (e.g., the printed circuit board of a ball grid array (“BGA”) package). The method of the present invention employs a solder mask comprising a dielectric film, such as a polymer, silicon oxide, glass (e.g., borophosphosilicate glass (“BPSG”), phosphosilicate glass (“PSG”), or borosilicate glass (“BSG”)), or silicon nitride, with apertures formed therethrough. The present invention also includes solder masks that may be used in the inventive method, as well as semiconductor devices fabricated in accordance with the method of the present invention. As used herein, the term “solder mask” is expansive and not limiting, including structures for application of materials to substrates to form conductive elements, whether metallic or nonmetallic.
  • [0015]
    The method of the present invention includes aligning a film of dielectric material, such as a polymer, silicon oxide, glass, or silicon nitride, with a substrate, such as a bare or minimally packaged semiconductor device or a printed circuit board. The film may be preformed or formed during disposal thereof onto the substrate. The film has apertures formed therethrough, which are substantially aligned with contact pads of the substrate, such as the bond pads of a bare or minimally packaged semiconductor device or the terminals of a printed circuit board, so as to expose the contact pads through the solder mask. The apertures are configured to impart a solder bump formed therein with a desired configuration. Apertures may be formed in the solder mask prior to, during, or subsequent to disposal of the solder mask on the substrate.
  • [0016]
    Conductive material, such as solder, is applied to the contact pads of the substrate through the apertures of the solder mask. Solder may be applied to the contact pads by known techniques, such as by wave solder techniques, which are also referred to as thermosonic dipping, by evaporation, by plating, by screen printing, or by disposing solder balls in or adjacent the apertures of the solder mask. Other conductive materials, such as conductive elastomers, may alternatively be disposed in the apertures of the solder mask by known processes, such as by screen printing or disposing a quantity of the conductive material in or adjacent each of the apertures of the solder mask. The solder or other conductive material is molten as it is introduced into the apertures or thereafter. As the solder or other conductive material in the apertures of the solder mask becomes molten, conductive structures of the desired shape are substantially simultaneously formed in the apertures and secured to their corresponding contact pads.
  • [0017]
    When the formed conductive structures have adequately solidified, the solder mask may be substantially removed from the substrate. Depending upon the type of material employed as the solder mask, the solder mask may be removed by peeling the film from the substrate (e.g., if a polymer is used as the solder mask) by use of suitable solvents (e.g., if a polymer is used as the solder mask), by etching the film from the substrate (e.g., if a polymer, silicon oxide, glass, or silicon nitride is used as the solder mask), or otherwise, as known in the art. Alternatively, the thickness of the solder mask may be reduced to expose the sides, or peripheries, of the conductive structures. For example, if the solder mask is comprised of a polymeric material that may be shrunken when exposed to a certain chemical or chemicals, to a plasma, or to radiation, the solder mask may be shrunken to expose the sides, or peripheries, of the conductive structures formed therewith. As another example, the thickness of the solder mask may be reduced by etching the dielectric material.
  • [0018]
    One embodiment of a semiconductor device according to the present invention, which represents an intermediate point in the method of the present invention, includes a substrate having contact pads on an active surface thereof and a solder mask comprising a dielectric material disposed over the active surface. The solder mask has a thickness that is substantially the same as the desired height of the conductive structures to be formed with the solder mask. The solder mask also includes apertures through which selected ones of the contact pads are exposed and into which conductive material is disposable. Thus, the conductive structures of the semiconductor device have not yet been exposed by removing or reducing the thickness of the solder mask. In one variation, the substrate is a bare or minimally packaged semiconductor die and the contact pads are the bond pads of the semiconductor die. In another variation, the substrate is a printed circuit board and the contact pads are the terminals of the printed circuit board.
  • [0019]
    In another embodiment of a semiconductor device according to the present invention, a solder mask made of dielectric material is disposed on an active surface of a substrate. The thickness of the solder mask is reduced (e.g., the layer is shrunken or etched). Conductive structures are secured to and communicate electrically with the contact pads of the substrate, extend through apertures of the reduced-thickness solder mask, and protrude from the solder mask. In one variation, the substrate is a bare or minimally packaged semiconductor die and the contact pads are the bond pads of the semiconductor die. In another variation, the substrate is a printed circuit board and the contact pads are the terminals of the printed circuit board.
  • [0020]
    Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • [0021]
    FIG. 1 is a perspective schematic representation of a semiconductor device according to the present invention;
  • [0022]
    FIG. 2 is a cross-sectional representation illustrating the placement of a solder mask on a semiconductor device;
  • [0023]
    FIG. 3 is a cross-sectional representation illustrating the disposal of conductive material in the apertures of the solder mask of FIG. 2;
  • [0024]
    FIG. 4A is a cross-sectional representation illustrating the removal of the solder mask of FIG. 3 from the semiconductor device to expose the conductive structures on the contact pads of the semiconductor device;
  • [0025]
    FIG. 4B is a cross-sectional representation illustrating a reduction in the thickness of the solder mask of FIG. 3 to expose the conductive structures on the contact pads of the semiconductor device;
  • [0026]
    FIG. 5 is a cross-sectional representation illustrating a variation of the configuration of a solder bump fabricated by the method of the present invention;
  • [0027]
    FIG. 6 is a cross-sectional representation illustrating a second variation of the configuration of a solder bump fabricated by the method of the present invention;
  • [0028]
    FIG. 7 is a cross-sectional representation illustrating a third variation of the configuration of a solder bump fabricated by the method of the present invention;
  • [0029]
    FIG. 8 is a cross-sectional representation illustrating a fourth variation of the configuration of a solder bump fabricated by the method of the present invention; and
  • [0030]
    FIG. 9 is a schematic representation, in perspective view, of a semiconductor wafer including a plurality of unsingulated, conductively bumped semiconductor dice.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0031]
    With reference to FIG. 1, a semiconductor device 10 according to the present invention, which includes a substrate 12 with integrated circuitry thereon and contact pads 14 (see FIGS. 2-8) in electrical communication with the integrated circuitry is illustrated. As depicted, substrate 12 is a semiconductor die and contact pads 14 are the bond pads of the semiconductor die. Typically and conventionally, the bond pads, when used with a tin/lead solder, may be coated with a plurality of superimposed metal layers to enhance the bonding of the solder to the metal of the bond pad. Further, contact pads may be offset from the bond pads and connected thereto by circuit traces extending over the active surface so as to rearrange an input/output pattern of bond pads to a pattern more suitable for an array of conductive bumps. Semiconductor device 10 also includes a solder mask 16 comprised of dielectric material disposed over an active surface 13 of substrate 12. Solder mask 16 includes apertures 18 aligned substantially over contact pads 14. Conductive structures 24 are disposed in apertures 18 so as to communicate electrically with their corresponding contact pads 14 exposed to apertures 18. As used herein, the term “semiconductor die” encompasses partial and full wafers as well as other nonwafer-based substrates, including, by way of example only, silicon on sapphire (“SOS”), silicon on glass (“SOG”) and, in general, silicon on insulator (“SOI”) substrates.
  • [0032]
    While semiconductor device 10 is depicted as including a semiconductor die, solder masks and conductive structures within the scope of the present invention may also be disposed on other types of substrates, such as printed circuit boards and other substrates with electrical circuitry and electrical contact pads thereon.
  • [0033]
    An exemplary method for fabricating semiconductor device 10 is illustrated in FIGS. 2-4B. FIG. 2 illustrates the alignment of a solder mask 16 with features on active surface 13 of substrate 12 and the disposal of solder mask 16 on active surface 13. Specifically, apertures 18 through solder mask 16 are substantially aligned with corresponding contact pads 14 on active surface 13. Thus, contact pads 14 are each exposed through their corresponding aperture 18.
  • [0034]
    As an example of the manner in which solder mask 16 may be disposed on active surface 13, a solder mask 16 comprising a film of a dielectric material with preformed apertures 18 therethrough may be aligned with the features of active surface 13, such as contact pads 14, and secured (e.g., by a pressure sensitive adhesive) to active surface 13. Preferably, the material from which solder mask 16 is made is a nonconductive polymer, such as a polyimide, that withstands the temperatures of the molten conductive materials, such as solders (e.g., temperatures from about 190° C. to about 260° C.) or conductive elastomers, to be disposed within apertures 18 without undergoing substantial conformational changes and without substantially degrading. Alternatively, solder mask 16 can be made of other dielectric materials, such as silicon oxide, glass (e.g., BPSG, PSG, or BSG), or silicon nitride. Apertures 18 may be preformed through the film of dielectric material by known laser ablation or laser drilling processes, by known mask and etch processes, or by other known micron-scale and submicron-scale processes for patterning the particular dielectric material employed as solder mask 16.
  • [0035]
    Alternatively, a layer of photoimageable polymeric material, such as a photoimageable polyimide, may be disposed on active surface 13 by known processes, such as by spin-on techniques, by curtain coating, by roller coating or by use of electrostatic spray. Solder mask 16 and the apertures 18 therethrough may then be formed from the layer of photoimageable material by known photoimaging processes, thereby substantially exposing contact pads 14 to apertures 18 and through solder mask 16. Again, the photoimageable polymeric material preferably withstands the temperatures of molten conductive material (e.g., solders, metals, and metal alloys) to be disposed within apertures 18 without undergoing substantial conformational changes or substantial degradation.
  • [0036]
    As another alternative, solder mask 16 may be fabricated by disposing a layer of dielectric material, such as a nonphotoimageable polyimide, silicon oxide, glass, or silicon nitride, on active surface 13 of substrate 12 by known processes. For example, known spin-on techniques may be employed to form layers of polymeric material and glass on active surface 13. As another example, layers of polymeric material may also be disposed on active surface 13, by curtain coating, by roller coating, by use of electrostatic spray, or by screen printing, which also patterns the layer of polymeric material substantially simultaneously with disposing the polymeric material on active surface 13. Known chemical vapor deposition (“CVD”) techniques may be employed to dispose a layer of silicon oxide, glass, or silicon nitride on active surface 13.
  • [0037]
    Apertures 18 may be formed through the dielectric material by known processes, such as by disposing a photomask over regions of the layer of dielectric material that are to remain on active surface 13 and by removing the dielectric material located above contact pads 14 through holes in the photomask. For example, known isotropic (e.g., wet chemical etching) and anisotropic, or dry, etch processes, such as barrel plasma etching (“BPE”) and reactive ion etching (“RIE”) processes, may be employed to form apertures 18 through a layer of polymeric material. Etching processes may likewise be used to form apertures 18 through silicon oxide, glass, and silicon nitride solder masks 16.
  • [0038]
    With reference to FIG. 3, a quantity of conductive material 22 is then disposed within each aperture 18 of solder mask 16. Conductive material 22 may be disposed within apertures 18 in molten or liquid form, as a powder, or as a paste. If solder, such as a tin/lead solder, is employed as conductive material 22, known processes may be employed to apply flux and the solder to the exposed surface of solder mask 16 and to dispose the solder within apertures 18. For example, known wave solder processes or solder ball disposition techniques may be employed to dispose the conductive material 22 into apertures 18. While in apertures 18, conductive material 22 is liquefied, which permits conductive material 22 to substantially fill each aperture 18. As the conductive material solidifies, it bonds to the portions of contact pads 14 exposed through apertures 18, forming conductive structures 24 that are electrically linked to each of the contact pads 14 exposed to apertures 18. The shape of each conductive structure 24 is determined by the shape of the aperture 18 in which conductive structure 24 was formed.
  • [0039]
    Alternatively, other types of conductive materials, such as z-axis and other conductive or conductor-filled elastomers, other metals, and metal alloys, may be similarly disposed within apertures 18 and in contact with contact pads 14 to form conductive structures 24. If a conductive elastomer is employed as the conductive material 22 used to form conductive structures 24, the conductive elastomer will preferably not adhere substantially to or diffuse substantially into adjacent regions of the material of solder mask 16.
  • [0040]
    Referring now to FIG. 4A, a method of exposing the sides, or peripheries, of conductive structures 24 is illustrated. Once conductive structures 24 have been formed on contact pads 14, solder mask 16 may be removed from active surface 13 of substrate 12. Solder mask 16 may be peeled from active surface 13, removed therefrom by use of a suitable solvent, such as antimony trichloride when solder mask 16 is fabricated from a polyimide material, or etched from active surface 13 by known processes. If an etchant is employed to remove solder mask 16, the etchant preferably removes the material of solder mask 16 with selectivity over conductive material 22 of conductive structures 24. If an elastomeric conductive material is employed to fabricate conductive structures 24, the technique by which solder mask 16 is removed from active surface 13 preferably does not substantially affect the configurations of the elastomeric conductive structures 24.
  • [0041]
    FIG. 4B illustrates a method of exposing the sides, or peripheries, of conductive structures 24 by reducing the thickness of solder mask 16 relative to the height of conductive structures 24. The thickness of solder mask 16 may be reduced by use of a suitable solvent or by etching the material of solder mask 16. If an etchant is employed to reduce the thickness of solder mask 16, the etchant preferably removes the material of solder mask 16 with selectivity over conductive material 22 of conductive structures 24.
  • [0042]
    Alternatively, other means of reducing the thickness of solder mask 16 may also be employed, such as shrinking a polymeric solder mask 16 with an oxygen plasma, with another type of plasma, with chemical shrinking agents, or by exposing solder mask 16 to radiation. An exemplary method of shrinking small spheres made of polystyrene, polydivinylbenzene, or polytoluene is disclosed in U.S. Pat. No. 5,510,156, which issued to Zhao on Apr. 23, 1996, the disclosure of which is hereby incorporated herein by this reference in its entirety. If an elastomeric material is employed to fabricate conductive structures 24, the technique by which the thickness of solder mask 16 is reduced preferably does not substantially affect the configurations of the elastomeric conductive structures 24.
  • [0043]
    Although FIGS. 2-4B illustrate substantially cylindrically configured conductive structures 24, conductive structures of other shapes are also within the scope of the present invention. FIGS. 5-8 illustrate some alternatively configured conductive structures that may be fabricated in accordance with the method of the present invention.
  • [0044]
    With reference to FIG. 5, a conductive structure 24′ that tapers inward from the top portion thereof toward contact pad 14 is shown. Thus, the portion of conductive structure 24′ adjacent to contact pad 14 is the narrowest portion of conductive structure 24′. The aperture 18 (see FIGS. 2-4B) within which conductive structure 24′ is formed may be defined through solder mask 16 by known processes, such as isotropic etching processes, that will provide an aperture 18 having a configuration complementary to that of conductive structure 24′.
  • [0045]
    FIG. 6 illustrates a conductive structure 24″ that tapers outward from the top portion thereof toward contact pad 14. As illustrated, the thickest portion of conductive structure 24″ is adjacent to contact pad 14, while the narrowest portion of conductive structure 24″ is the top thereof. The aperture 18 (see FIGS. 2-4B) within which conductive structure 24″ is formed may be defined through solder mask 16 by known processes, such as isotropic etching processes, that will provide an aperture 18 having a configuration complementary to that of conductive structure 24″.
  • [0046]
    FIG. 7 illustrates a conductive structure 24′″ with an upper portion 24 a′″ having a transverse cross section taken along the height of upper portion 24 a′″ of substantially uniform configuration. A lower portion 24 b′″ of conductive structure 24′″ is located between contact pad 14 and upper portion 24 a′″. The transverse cross section taken along the height of lower portion 24 b′″ also has a substantially uniform configuration. Lower portion 24 b′″ has a smaller transverse cross section than upper portion 24 a′″. The aperture 18 (see FIGS. 2-4B) within which conductive structure 24′″ is formed may be defined by disposing a photomask of the type disclosed in U.S. Pat. No. 5,741,624, which issued to Jeng et al. on Apr. 21, 1998, the disclosure of which is hereby incorporated herein in its entirety by this reference. Material of the solder mask 16 may then be removed by known etching processes through holes in the photomask to define stepped apertures 18 over contact pads 14.
  • [0047]
    Turning to FIG. 8, another conductive structure 124 is illustrated. Conductive structure 124 has an outwardly curved center portion, which is thicker than the ends of conductive structure 124. Known processes, such as isotropic etching techniques, may be employed to form apertures 18 through solder mask 16 (see FIGS. 2-4B) within which conductive structure 124 may be formed.
  • [0048]
    Of course, solder masks 16 having different shapes of apertures 18, as well as solder masks 16 having apertures 18 with combinations of different shapes, are also within the scope of the present invention. Accordingly, the present invention also includes semiconductor devices with combinations of different shapes of conductive structures on the contact pads thereof.
  • [0049]
    FIG. 9 illustrates that the above-described processes may be employed to form conductive structures on substrates 12 (FIGS. 1-8), in this case semiconductor dice, before the semiconductor dice have been singulated from a semiconductor wafer 30. Accordingly, semiconductor wafers 30 including a plurality of unsingulated, conductively bumped substrates 12 are also within the scope of the present invention. Individual conductively bumped semiconductor devices 10 may subsequently be singulated from semiconductor wafer 30 by known singulation processes, such as by the use of a wafer saw 40.
  • [0050]
    Although the foregoing description contains many specifics and examples, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of this invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein and which fall within the meaning of the claims are to be embraced within their scope.

Claims (16)

  1. 1. A method for forming at least one conductive structure in communication with at least one contact pad of a semiconductor device substrate, comprising:
    forming a layer of mask material having a thickness that corresponds substantially to a desired height of the at least one conductive structure, the layer configured to be positioned over the substrate;
    forming at least one aperture through the layer to expose at least a portion of the at least one contact pad;
    introducing conductive material into the at least one aperture to form the at least one conductive structure to substantially the desired height; and
    partially exposing a lateral periphery of the at least one conductive structure through the layer.
  2. 2. The method of claim 1, further comprising:
    positioning the layer over the substrate.
  3. 3. The method of claim 2, further comprising:
    securing the layer to the substrate.
  4. 4. The method of claim 2, wherein forming the at least one aperture is effected before positioning the layer over the substrate.
  5. 5. The method of claim 2, wherein forming the at least one aperture is effected after the layer has been secured to the substrate.
  6. 6. The method of claim 1, wherein forming the layer is effected on the substrate.
  7. 7. The method of claim 1, further comprising:
    bonding the conductive material within the at least one aperture to at least the portion of the at least one contact pad.
  8. 8. The method of claim 1, wherein partially exposing comprises reducing a thickness of the layer of mask material.
  9. 9. The method of claim 8, wherein reducing the thickness of the layer of mask material comprises shrinking the layer of mask material.
  10. 10. The method of claim 9, wherein shrinking comprises exposing the mask material to radiation, a shrinking agent, or a plasma.
  11. 11. The method of claim 8, wherein reducing the thickness of the layer of mask material comprises removing mask material.
  12. 12. A method for forming a solder mask, comprising:
    applying a solder mask material to a contact pad-bearing surface of a substrate to form a layer of reducible thickness, the layer having an initial thickness that corresponds substantially to a desired height of at least one conductive structure to be formed over the substrate; and
    forming at least one aperture through the layer in a location that corresponds to at least one contact pad carried by the substrate to expose at least a portion of the at least one contact pad.
  13. 13. The method of claim 12, wherein applying comprises applying unconsolidated material to the contact pad-bearing surface of the substrate.
  14. 14. The method of claim 13, further comprising at least partially consolidating the unconsolidated material.
  15. 15. The method of claim 14, wherein at least partially consolidating includes forming the at least one aperture.
  16. 16. The method of claim 12, wherein forming the at least one aperture comprises removing solder mask material from the layer.
US11068676 1999-08-27 2005-03-01 Method of disposing conductive bumps onto a semiconductor device and semiconductor devices so formed Abandoned US20050142835A1 (en)

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