JP2001223232A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JP2001223232A JP2001223232A JP2000030077A JP2000030077A JP2001223232A JP 2001223232 A JP2001223232 A JP 2001223232A JP 2000030077 A JP2000030077 A JP 2000030077A JP 2000030077 A JP2000030077 A JP 2000030077A JP 2001223232 A JP2001223232 A JP 2001223232A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- protective film
- semiconductor device
- manufacturing
- conductive portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子の外部
接続用の電極上に導電部を形成する半導体装置の製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a conductive portion is formed on an electrode for external connection of a semiconductor element.
【0002】[0002]
【従来の技術】半導体装置に用いられるシリコン基板の
製造工程では、半導体装置の薄型化にともない基板の厚
さを薄くするための薄化加工が行われる。この薄化加工
は、シリコン基板の表面に回路パターンを形成した後
に、回路形成面と反対側の裏面を機械研削、湿式エッチ
ングあるいはプラズマ処理などによって除去することに
より行われる。従来この薄化加工は一般に電極上に半田
バンプなどの導電部を形成した後に行われていた。2. Description of the Related Art In a process of manufacturing a silicon substrate used for a semiconductor device, a thinning process is performed to reduce the thickness of the substrate as the semiconductor device is thinned. This thinning is performed by forming a circuit pattern on the surface of the silicon substrate and then removing the back surface opposite to the circuit formation surface by mechanical grinding, wet etching, plasma processing, or the like. Conventionally, the thinning process is generally performed after forming a conductive portion such as a solder bump on an electrode.
【0003】[0003]
【発明が解決しようとする課題】ところが、半田バンプ
形成後に薄化加工を行うと、バンプ形成部の形状不連続
部分には応力集中が発生しやすいことからこの部分の強
度が低下する結果、半導体ウェハにクラックが生じる場
合があった。また、薄化加工後の半導体ウェハは全体の
強度がきわめて脆弱で、ハンドリングが難しいことから
破損が生じやすく、製品歩留まりを低下させる要因とな
っていた。However, when thinning is performed after the formation of the solder bumps, stress concentration tends to occur at the discontinuity in the shape of the bump formation portion, so that the strength of this portion is reduced. Cracks sometimes occurred on the wafer. Further, the semiconductor wafer after the thinning processing has an extremely weak overall strength and is difficult to handle, so that the semiconductor wafer is likely to be damaged, which is a factor of lowering the product yield.
【0004】そこで本発明は、半導体ウェハの破損を防
止して製品歩留まりを向上させることができる半導体装
置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing a semiconductor wafer from being damaged and improving a product yield.
【0005】[0005]
【課題を解決するための手段】請求項1記載の半導体装
置の製造方法は、半導体素子の外部接続用の電極に導電
部が形成された半導体装置を製造する半導体装置の製造
方法であって、半導体素子が形成された半導体ウェハの
回路形成面に保護膜を形成する工程と、保護膜が形成さ
れた半導体ウェハの回路形成面の反対側を除去して半導
体ウェハを薄化する工程と、前記保護膜に前記電極の位
置に対応して保護膜を貫通する貫通孔を形成する工程
と、この貫通孔内に前記電極と導通する導電部を形成す
る工程と、導電部形成後に前記保護膜を半導体ウェハか
ら除去する工程とを含む。According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing a semiconductor device in which a conductive portion is formed on an external connection electrode of a semiconductor element. Forming a protective film on the circuit forming surface of the semiconductor wafer on which the semiconductor element is formed; removing the opposite side of the circuit forming surface of the semiconductor wafer on which the protective film is formed to thin the semiconductor wafer; A step of forming a through hole through the protective film corresponding to the position of the electrode in the protective film, a step of forming a conductive portion in conduction with the electrode in the through hole, and forming the protective film after forming the conductive portion. Removing from the semiconductor wafer.
【0006】請求項2記載の半導体装置の製造方法は、
請求項1記載の半導体装置の製造方法であって、前記導
電部形成を、導電性ペーストを前記貫通孔に充填するこ
とにより行う。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive portion is formed by filling a conductive paste into the through hole.
【0007】請求項3記載の半導体装置の製造方法は、
請求項1記載の半導体装置の製造方法であって、前記導
電部形成を、前記貫通孔に導電性ボールを搭載すること
により行う。According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the conductive portion is formed by mounting a conductive ball in the through hole.
【0008】請求項4記載の半導体装置の製造方法は、
請求項1記載の半導体装置の製造方法であって、前記導
電部形成を、前記貫通孔内に金属メッキ層を形成するこ
とにより行う。According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive portion is formed by forming a metal plating layer in the through hole.
【0009】本発明によれば、半導体ウェハの回路形成
面を保護する保護膜を形成した状態の半導体ウェハの回
路形成面の反対側を除去して半導体ウェハを薄化し、こ
の後に保護膜を貫通して設けられた貫通孔内に電極と導
通する導電部を形成することにより、導電部形成時の半
導体ウェハを補強して半導体素子の破損を防止すること
ができる。According to the present invention, the semiconductor wafer is thinned by removing the side opposite to the circuit forming surface of the semiconductor wafer in a state where the protective film for protecting the circuit forming surface of the semiconductor wafer is formed, and thereafter, the protective film is penetrated. By forming a conductive portion in conduction with an electrode in the through hole provided as described above, the semiconductor wafer at the time of forming the conductive portion can be reinforced to prevent damage to the semiconductor element.
【0010】[0010]
【発明の実施の形態】次に本発明の実施の形態を図面を
参照して説明する。図1、図2、図3、図4は本発明の
一実施の形態の半導体装置の製造方法の工程説明図であ
る。図1(a),(b),(c)、図2(a),
(b),(c)は、半導体装置の製造方法を工程順に示
している。Embodiments of the present invention will now be described with reference to the drawings. 1, 2, 3, and 4 are process explanatory views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1 (a), (b), (c), FIG. 2 (a),
4B and 4C show a method of manufacturing a semiconductor device in the order of steps.
【0011】図1(a)において、1は複数の半導体素
子が形成された半導体ウェハである。半導体ウェハ1の
上面は回路形成面であり、外部接続用の電極2が形成さ
れている。次に、図1(b)に示すように、半導体ウェ
ハ1の上面の回路形成面にはポリイミドなどの耐熱性を
有する樹脂材質の保護膜3が形成されており、保護膜3
は半導体ウェハ1の回路形成面を保護するとともに、こ
の後の薄化工程で脆弱になった半導体ウェハ1を補強す
る機能を有している。In FIG. 1A, reference numeral 1 denotes a semiconductor wafer on which a plurality of semiconductor elements are formed. The upper surface of the semiconductor wafer 1 is a circuit formation surface, on which electrodes 2 for external connection are formed. Next, as shown in FIG. 1B, a protective film 3 made of a heat-resistant resin material such as polyimide is formed on the circuit forming surface on the upper surface of the semiconductor wafer 1.
Has a function of protecting the circuit formation surface of the semiconductor wafer 1 and reinforcing the semiconductor wafer 1 that has become weak in the subsequent thinning process.
【0012】この保護膜3は、半導体ウェハ1の表面を
保護するのみならず、半導体ウェハ1を加工して半導体
装置を製造する以下の工程において半導体ウェハ1を補
強する役割を有している。この保護膜3形成は、シート
状に加工した樹脂膜を接着剤によって半導体ウェハ1の
回路形成面に接着する方法の他、液状の樹脂を回路形成
面上に均一に塗布する方法などを用いることができる。The protective film 3 not only protects the surface of the semiconductor wafer 1 but also has the role of reinforcing the semiconductor wafer 1 in the following steps of processing the semiconductor wafer 1 and manufacturing semiconductor devices. The protective film 3 is formed by using a method in which a resin film processed into a sheet shape is bonded to the circuit forming surface of the semiconductor wafer 1 with an adhesive, or a method in which a liquid resin is uniformly applied on the circuit forming surface. Can be.
【0013】次に、保護膜3が形成された半導体ウェハ
1は、薄化工程に送られる。ここでは、図1(c)に示
すように、半導体ウェハ1の回路形成面の反対側を除去
することにより、半導体ウェハ1を薄化する(破線で示
す下側部分参照)。この薄化の方法としては、研磨など
の機械的研削加工や、薬液により化学的に半導体ウェハ
をエッチングする湿式加工の他、プラズマ処理装置によ
ってプラズマエッチングを行う方法、あるいはこれらの
方法を組み合わせて薄化を行う方法などを用いることが
できる。この薄化工程に先立って、半導体ウェハ1は保
護膜3によって補強されているため、薄化工程において
半導体ウェハ1が破損することがなく、製品信頼性や歩
留まりを向上させることができる。Next, the semiconductor wafer 1 on which the protective film 3 is formed is sent to a thinning step. Here, as shown in FIG. 1C, the semiconductor wafer 1 is thinned by removing the side opposite to the circuit forming surface of the semiconductor wafer 1 (see the lower part shown by a broken line). Examples of the thinning method include mechanical grinding such as polishing, wet processing of chemically etching a semiconductor wafer with a chemical, plasma etching using a plasma processing apparatus, or a combination of these methods. For example, a method of performing chemical conversion can be used. Prior to this thinning step, the semiconductor wafer 1 is reinforced by the protective film 3, so that the semiconductor wafer 1 is not damaged in the thinning step, and product reliability and yield can be improved.
【0014】次に、薄化が完了した半導体ウェハ1は貫
通孔形成工程に送られる。ここでは、図2(a)に示す
ように、半導体ウェハ1の上面に形成された保護膜3に
貫通孔形成が行われる。この貫通孔形成にはレーザ加工
が用いられ、電極2の位置に対応して保護膜3を貫通す
る貫通孔3aを形成する。保護膜3の所定位置にレーザ
光を照射することにより、照射位置にある樹脂が昇華
し、保護膜3には電極2の表面に到達する貫通孔3aが
形成される。Next, the thinned semiconductor wafer 1 is sent to a through hole forming step. Here, as shown in FIG. 2A, through holes are formed in the protective film 3 formed on the upper surface of the semiconductor wafer 1. Laser processing is used to form this through-hole, and a through-hole 3 a penetrating through the protective film 3 is formed corresponding to the position of the electrode 2. By irradiating the predetermined position of the protective film 3 with the laser beam, the resin at the irradiation position sublimates, and a through hole 3 a reaching the surface of the electrode 2 is formed in the protective film 3.
【0015】次に、貫通孔3a内に導電部7を形成する
工程について説明する。本発明では、導電性ペーストを
貫通孔3aの内部に充填し、この導電性ペーストを加熱
することにより、図2(b)に示すように、電極2と導
通する導電部7を形成する。導電性ペーストとしては、
クリーム半田5等の金属ペーストや熱硬化性の導電性樹
脂が用いられる。金属ペーストの場合には、加熱によっ
て金属成分を溶融させて半導体ウェハ1の電極2と接合
して導電部7となり、導電性樹脂の場合は貫通孔3a内
で熱硬化することによって電極2と電気的に導通した導
電部7となる。次に図面を用いて導電部形成工程を具体
的に説明する。Next, a process for forming the conductive portion 7 in the through hole 3a will be described. In the present invention, the conductive paste is filled into the through holes 3a, and the conductive paste is heated to form the conductive portions 7 that are electrically connected to the electrodes 2 as shown in FIG. 2B. As the conductive paste,
A metal paste such as cream solder 5 or a thermosetting conductive resin is used. In the case of a metal paste, the metal component is melted by heating and joined to the electrode 2 of the semiconductor wafer 1 to form a conductive portion 7. In the case of a conductive resin, the electrode 2 is electrically cured by being thermally cured in the through hole 3 a. The electrically conductive portion 7 becomes electrically conductive. Next, the conductive portion forming step will be specifically described with reference to the drawings.
【0016】図3は、金属ペーストを用いて導電部を形
成する工程を示している。金属ペーストは導電性の金属
粒子と液状の有機溶剤とを混合してペースト状としたも
のであり、その代表的なものとしてクリーム半田が知ら
れている。図3(a)に示すように、貫通孔3aが設け
られた保護膜3の上面にスクリーンマスク10を装着
し、貫通孔3aの位置に対応して設けられたパターン孔
10aを介して、貫通孔3a内とパターン孔10a内に
クリーム半田5を充填する。FIG. 3 shows a step of forming a conductive portion using a metal paste. The metal paste is a paste made by mixing conductive metal particles and a liquid organic solvent, and cream solder is known as a typical example thereof. As shown in FIG. 3A, a screen mask 10 is mounted on the upper surface of the protective film 3 provided with the through holes 3a, and the screen mask 10 is formed through the pattern holes 10a provided corresponding to the positions of the through holes 3a. The cream solder 5 is filled in the holes 3a and the pattern holes 10a.
【0017】これにより、図3(b)に示すように貫通
孔3a内部のみならず保護膜3の上面にもクリーム半田
5が供給される。そしてこの後加熱によりクリーム半田
5中の半田粒子を溶融させるが、各貫通孔3aの位置に
は充分な量のクリーム半田5が供給されているので、溶
融した半田は貫通孔3aの上側に突出した状態で固化
し、図3(c)に示すように各貫通孔3aの位置には、
電極2と導通し保護膜3の上面よりも上方に突出する突
出部を一体的に備えた導電部7が形成される。As a result, as shown in FIG. 3B, the cream solder 5 is supplied not only to the inside of the through hole 3a but also to the upper surface of the protective film 3. After that, the solder particles in the cream solder 5 are melted by heating. Since a sufficient amount of the cream solder 5 is supplied to the position of each through-hole 3a, the molten solder projects above the through-hole 3a. In a state where the through holes 3a are solidified as shown in FIG.
A conductive portion 7 integrally formed with a protruding portion that is electrically connected to the electrode 2 and protrudes above the upper surface of the protective film 3 is formed.
【0018】図4は、導電部形成の他の例を示してい
る。まず図4(a)に示すように、金属ペーストである
クリーム半田5が充填される。クリーム半田5はスキー
ジ等のへら状のものを用いて充填される。次いで、貫通
孔3aに充填されたクリーム半田5上には、図4(b)
に示すように導電性ボールとしての半田ボール6が搭載
される。この半田ボール6はクリーム半田5と同じ半田
で形成されている。このボール搭載時に、貫通孔3aの
周囲の保護膜3は半田ボール6の位置ずれを防ぐガイド
として機能する。FIG. 4 shows another example of the formation of the conductive portion. First, as shown in FIG. 4A, a cream solder 5 which is a metal paste is filled. The cream solder 5 is filled using a spatula-shaped material such as a squeegee. Next, on the cream solder 5 filled in the through-hole 3a, FIG.
As shown in FIG. 7, a solder ball 6 as a conductive ball is mounted. The solder balls 6 are formed of the same solder as the cream solder 5. During the mounting of the ball, the protective film 3 around the through hole 3a functions as a guide for preventing the solder ball 6 from being displaced.
【0019】この後半導体ウェハ1はリフロー工程に送
られここで加熱される。これにより、半田ボール6およ
びクリーム半田5中の半田粒子が溶融し、電極2上面と
半田接合される。これにより、図4(c)に示すよう
に、貫通孔3aには電極2と導通する導電部7が形成さ
れる。Thereafter, the semiconductor wafer 1 is sent to a reflow process, where it is heated. Thereby, the solder particles in the solder ball 6 and the cream solder 5 are melted, and are soldered to the upper surface of the electrode 2. As a result, as shown in FIG. 4C, a conductive portion 7 electrically connected to the electrode 2 is formed in the through hole 3a.
【0020】なお、貫通孔3a内に導電部を形成する方
法としては、上記2例以外にも無電解メッキなどによっ
て、電極2表面に金属メッキ層を積層することにより、
貫通孔3a内に導電部を形成するようにしてもよい。こ
の場合には、保護膜3がメッキ膜形成用のレジストとし
て機能する。As a method of forming a conductive portion in the through hole 3a, a metal plating layer may be laminated on the surface of the electrode 2 by electroless plating or the like in addition to the above two examples.
A conductive portion may be formed in the through hole 3a. In this case, the protective film 3 functions as a resist for forming a plating film.
【0021】この後、導電部7が形成された半導体ウェ
ハ1は、保護膜剥離工程に送られる。ここでは、図2
(c)に示すように、半導体ウェハ1の上面から保護膜
3が剥離される。これにより、半導体素子の外部接続用
の電極に導電部が形成された半導体装置が完成する。な
お保護膜3の除去方法としては、薬液やプラズマを用い
たエッチングによる方法でも良い。Thereafter, the semiconductor wafer 1 on which the conductive portions 7 are formed is sent to a protective film peeling step. Here, FIG.
As shown in (c), the protective film 3 is peeled off from the upper surface of the semiconductor wafer 1. Thus, a semiconductor device in which a conductive portion is formed on an external connection electrode of a semiconductor element is completed. The protective film 3 may be removed by etching using a chemical solution or plasma.
【0022】上記説明したように、本実施の形態に示す
半導体装置の製造過程では、半導体ウェハ1の電極2に
導通する導電部7の形成に先だって、半導体ウェハ1の
回路形成面に保護膜3を形成するようにしている。これ
により、導電部形成過程において回路形成面が保護され
ると共に、脆弱な半導体ウェハ1が保護膜により補強さ
れているため、導電部形成工程を含む半導体装置の製造
過程において、半導体ウェハ1の破損が生じることがな
い。したがって、完成した半導体装置の品質が確保され
ると共に、製品歩留まりを向上させることができる。As described above, in the manufacturing process of the semiconductor device shown in the present embodiment, prior to the formation of the conductive portion 7 conducting to the electrode 2 of the semiconductor wafer 1, the protective film 3 is formed on the circuit formation surface of the semiconductor wafer 1. Is formed. Thereby, the circuit formation surface is protected in the conductive part forming process, and the fragile semiconductor wafer 1 is reinforced by the protective film. Therefore, the semiconductor wafer 1 is damaged in the manufacturing process of the semiconductor device including the conductive part forming step. Does not occur. Therefore, the quality of the completed semiconductor device can be ensured, and the product yield can be improved.
【0023】[0023]
【発明の効果】本発明によれば、半導体ウェハの回路形
成面を保護する保護膜を形成した状態の半導体ウェハの
回路形成面の反対側を除去して半導体ウェハを薄化し、
この後に保護膜を貫通して設けられた貫通孔内に電極と
導通する導電部を形成するようにしたので、導電部形成
時の半導体ウェハを補強して半導体素子の破損を防止す
ることができ、完成した半導体装置の品質が確保される
と共に、製品歩留まりを向上させることができる。According to the present invention, the semiconductor wafer is thinned by removing the side opposite to the circuit forming surface of the semiconductor wafer on which a protective film for protecting the circuit forming surface of the semiconductor wafer has been formed,
Thereafter, a conductive portion that is electrically connected to the electrode is formed in a through hole provided through the protective film, so that the semiconductor wafer at the time of forming the conductive portion can be reinforced to prevent damage to the semiconductor element. In addition, the quality of the completed semiconductor device can be ensured, and the product yield can be improved.
【図1】本発明の一実施の形態の半導体装置の製造方法
の工程説明図FIG. 1 is a process explanatory view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図2】本発明の一実施の形態の半導体装置の製造方法
の工程説明図FIG. 2 is a process explanatory view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図3】本発明の一実施の形態の半導体装置の製造方法
の工程説明図FIG. 3 is a process explanatory view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図4】本発明の一実施の形態の半導体装置の製造方法
の工程説明図FIG. 4 is a process explanatory view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
1 半導体ウェハ 2 電極 3 保護膜 3a 貫通孔 5 クリーム半田 6 半田ボール 7 導電部 Reference Signs List 1 semiconductor wafer 2 electrode 3 protective film 3a through hole 5 cream solder 6 solder ball 7 conductive part
Claims (4)
形成された半導体装置を製造する半導体装置の製造方法
であって、半導体素子が形成された半導体ウェハの回路
形成面に保護膜を形成する工程と、保護膜が形成された
半導体ウェハの回路形成面の反対側を除去して半導体ウ
ェハを薄化する工程と、前記保護膜に前記電極の位置に
対応して保護膜を貫通する貫通孔を形成する工程と、こ
の貫通孔内に前記電極と導通する導電部を形成する工程
と、導電部形成後に前記保護膜を半導体ウェハから除去
する工程とを含むことを特徴とする半導体装置の製造方
法。1. A method of manufacturing a semiconductor device in which a conductive portion is formed on an electrode for external connection of the semiconductor device, comprising: forming a protective film on a circuit forming surface of a semiconductor wafer on which the semiconductor device is formed. A step of forming, a step of removing the opposite side of the circuit formation surface of the semiconductor wafer on which the protective film is formed, to thin the semiconductor wafer, and a step of penetrating the protective film through the protective film corresponding to the position of the electrode. A semiconductor device comprising: a step of forming a through hole; a step of forming a conductive portion in conduction with the electrode in the through hole; and a step of removing the protective film from the semiconductor wafer after the formation of the conductive portion. Manufacturing method.
貫通孔に充填することにより行うことを特徴とする請求
項1記載の半導体装置の製造方法。2. The method according to claim 1, wherein the conductive portion is formed by filling a conductive paste into the through hole.
ールを搭載することにより行うことを特徴とする請求項
1記載の半導体装置の製造方法。3. The method according to claim 1, wherein the conductive portion is formed by mounting a conductive ball in the through hole.
ッキ層を形成することにより行うことを特徴とする請求
項1記載の半導体装置の製造方法。4. The method according to claim 1, wherein the conductive portion is formed by forming a metal plating layer in the through hole.
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JP2000030077A JP2001223232A (en) | 2000-02-08 | 2000-02-08 | Manufacturing method of semiconductor device |
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Cited By (5)
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---|---|---|---|---|
WO2003060987A1 (en) * | 2002-01-10 | 2003-07-24 | Nec Corporation | Method of arranging micro spheres with liquid, micro sphere arranging device, and semiconductor device |
US7235428B2 (en) | 2002-11-21 | 2007-06-26 | Rohm Co., Ltd. | Semiconductor device production method |
JPWO2006077630A1 (en) * | 2005-01-19 | 2008-06-12 | 新日本無線株式会社 | Manufacturing method of semiconductor device |
JP2008166340A (en) * | 2006-12-27 | 2008-07-17 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
JP2010500935A (en) * | 2006-08-16 | 2010-01-14 | サン−ゴバン セラミックス アンド プラスティクス,インコーポレイティド | Injection molding of ceramic elements |
-
2000
- 2000-02-08 JP JP2000030077A patent/JP2001223232A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003060987A1 (en) * | 2002-01-10 | 2003-07-24 | Nec Corporation | Method of arranging micro spheres with liquid, micro sphere arranging device, and semiconductor device |
US7119438B2 (en) | 2002-01-10 | 2006-10-10 | Nec Corporation | Method of arranging microspheres with liquid, microsphere arranging device, and semiconductor device |
CN100341126C (en) * | 2002-01-10 | 2007-10-03 | 日本电气株式会社 | Method of arranging micro spheres with liquid, micro sphere arranging device, and semiconductor device |
US7235428B2 (en) | 2002-11-21 | 2007-06-26 | Rohm Co., Ltd. | Semiconductor device production method |
US8089163B2 (en) | 2002-11-21 | 2012-01-03 | Rohm Co., Ltd. | Semiconductor device production method and semiconductor device |
KR101120128B1 (en) | 2002-11-21 | 2012-02-22 | 로무 가부시키가이샤 | Semiconductor device production method and semiconductor device |
JPWO2006077630A1 (en) * | 2005-01-19 | 2008-06-12 | 新日本無線株式会社 | Manufacturing method of semiconductor device |
JP4739198B2 (en) * | 2005-01-19 | 2011-08-03 | 新日本無線株式会社 | Manufacturing method of semiconductor device |
JP2010500935A (en) * | 2006-08-16 | 2010-01-14 | サン−ゴバン セラミックス アンド プラスティクス,インコーポレイティド | Injection molding of ceramic elements |
JP2008166340A (en) * | 2006-12-27 | 2008-07-17 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
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