TWI402925B - 金屬柱凸塊結構及其形成方法 - Google Patents

金屬柱凸塊結構及其形成方法 Download PDF

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TWI402925B
TWI402925B TW099122293A TW99122293A TWI402925B TW I402925 B TWI402925 B TW I402925B TW 099122293 A TW099122293 A TW 099122293A TW 99122293 A TW99122293 A TW 99122293A TW I402925 B TWI402925 B TW I402925B
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layer
metal
forming
bump structure
stud bump
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TW099122293A
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TW201103093A (en
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Ming Hung Tseng
Young Chang Lien
Chen Shien Chen
Chen Cheng Kuo
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Taiwan Semiconductor Mfg
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Description

金屬柱凸塊結構及其形成方法
本發明係關於覆晶(flip chip)與晶圓層級(wafer-level)封裝，且特別是關於一種具有側壁保護物之金屬柱凸塊結構(metal pillar bump structure)及其形成方法。
銅柱凸塊(copper pillar bump)已為英特爾(intel)於2006年導入於其65奈米”Yonah”微處理器中。隨著接腳數量(pin counts)與內連物密度(interconnect densities)的增加，對於採用銅柱凸塊以替代用於覆晶與晶圓層級封裝之習知銲錫凸塊以外的興趣逐漸成長。
銅柱(copper pillar)提供了優於銲錫凸塊(solder bump)之數個優點，例如較高之內連物密度、較高之可靠度、較佳之電性與熱表現與鉛使用量的降低或消除。於銲錫迴銲時，銲錫凸塊會倒塌，而銅柱則維持了其於x、y、z等方向上之形狀。如此使得用於更高內連物密度之更精密之凸塊間距、較小之保護層開口與精細之重分佈導線等製作成為可能。
然而，於製作過程中，銅柱之側壁可能於一蝕刻過程中產生化學劣化情形，以及於後續組裝接合製程中可能於銅柱側壁上產生氧化情形，因而造成了不良的銅可靠度以及於銅與一底膠(underfill)材料間之不良附著情形。
基於上述因素以及於後續內容中描述之其他因素，便需要用於覆晶與晶圓層級封裝之較佳銅柱凸塊，以避免習知銅柱凸塊所遭遇之可靠度問題。
有鑑於此，本發明提供了金屬柱凸塊結構及其形成方法，以解決上述之習知問題。
依據一實施例，本發明提供了一種金屬柱凸塊結構，包括：一保護層，形成於一半導體基板之上；一導電層，形成於該保護層之上；一金屬層，形成於該導電層之上；以及一銲錫材料層，包覆該金屬層。
依據另一實施例，本發明提供了一種金屬柱凸塊結構之形成方法，包括：形成一保護層於一半導體基板之上；形成一導電層於該保護層之上；提供經圖案化與經過蝕刻之一阻劑層於該導電層之上，該阻劑層中定義有至少一開口；沈積一金屬層於該至少一開口內；沿著介於該阻劑層與該金屬層間之一或多個界面蝕刻部份之該阻劑層，以形成複數個凹穴；沈積一銲錫材料於該至少一開口內，該銲錫材料填入該些凹穴內以及高於該金屬層之該開口之一部內；移除剩餘之該阻劑層與未形成於該金屬層之下之該導電層；以及迴銲該銲錫材料以包覆該金屬層。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
第1-4圖為一系列剖面圖，顯示了依據本發明之一實施例之於形成一銅柱凸塊結構之不同階段時，其內之一半導體裝置。此些圖式僅作為解說之用而非用以限制本發明。熟悉此技藝者可以理解的是此些實施情形亦可具有其他變化、修改與選擇情形。
第1圖顯示了依據本發明之一實施例之一半導體基板20。半導體基板20可為一半導體製程晶圓(例如為200釐米、300釐米、400釐米等之矽晶圓)且可包括藉由先前製程所形成之金屬層、絕緣層、裝置構件等構件。半導體基板20可為單晶或多晶矽之基板。可以理解的是，半導體基板20可包括磊晶矽層、絕緣層上覆矽、矽鍺或砷化鎵等實施情形。
接著於半導體基板20之上形成一保護層(passivation layer)30。保護層30可為一或多個膜層，且可包括一材料，例如為氧化物、未摻雜矽玻璃(undoped silicate glass，USG)、氮化矽、二氧化矽、氮氧化矽或聚亞醯胺。雖然未顯示於第1圖中，熟悉此技藝者可以理解的是，於保護層30內可包括如接觸墊(contact pads)與金屬導線(metal lines)等導電膜層，藉以電性接觸位於上方之一銅柱凸塊。保護層30可藉由如化學氣相沈積或旋轉塗佈技術之沈積技術而沈積於半導體基板20之上。化學氣相沈積可包括低壓化學氣相沈積(LPCVD)、電漿加強型化學氣相沈積(PECVD)、或大氣壓化學氣相沈積(APCVD)等方法。於一實施例中，保護層30包括一氧化物與一氮化物，且沈積至約為2000-12000埃之一厚度。於其他實施例中，保護層30具有約為2000-6000埃之一厚度。
接著於保護層30之上形成一導電層或一晶種層(seed layer)40，以避免金屬擴散情形。舉例來說，晶種層40可包括鈦或銅，且可藉由如濺鍍(sputtering)、蒸鍍(evaporation)或其他之沈積技術所形成。於一實施例中，晶種層40沈積至約介於1000-8000埃之一厚度。
請繼續參照第1圖，接著形成阻劑層50於晶種層40之上。阻劑層50作為金屬沈積製程之模具之用，例如為於形成銅柱凸塊時之銅電鍍之用。熟悉此技藝者可以理解的是，阻劑之材料為一種適用於塗佈、曝光、顯影、電鍍與利用裝備及適當製程化學品以進行去除(stripping)之材料。於一實施例中，阻劑層50包括化學增幅之正型阻劑，其具有高度對比與解析度以及具有約為60-120微米之一厚度。接著藉由一微影圖案化製程及經過顯影之後而圖案化阻劑層50，藉以形成一或多個開口55。
接著於阻劑層50之開口55內沈積一金屬層或一銅層60。銅層60亦可包括銅合金。如金、銀、鋁、錫-金、與錫-銅等具有良好導電率之金屬或合金皆可作為替代材料之用。銅層60可藉由銅電鍍(copper electroplating)製程或無電電鍍(electrodeless plating)製程而沈積於開口55之內。於一實施例中，銅層60係沈積於基板20上至介於約40-80微米之一厚度。於採用電鍍製程之一實施例中，阻劑層50之開口55經過電鍍而形成銅或其他銅合金材料，以形成經電鍍之銅柱之第一膜層。可更接著形成額外之膜層。於施行上述電鍍製程之前，可使用3-5倍稀釋之硫酸溶液處理半導體基板20約3分鐘，以移除油、油漬、氧化物與其他污染物，如此可確保半導體基板20與經電鍍膜層之銅柱間之較佳之附著情形。於另一實施例中，銅電鍍之最佳電流密度約為3-7ASD(A/cm2)，且可使用任何電流密度。於此實施例中，於0.5ASD條件下電鍍之沈積速率可達到0.3微米/每分鐘，且其可正比於電流密度。
於形成銅柱之後，可形成選擇性之一金屬阻障層，或一鎳層70於銅層60之表面上。鎳層70可防止了銅擴散進入後續形成之銲錫材料之內。
請參照第2圖，沿著介於阻劑層50與銅層60間之一或多個介面處之蝕刻移除阻劑層50之多個部份之後，形成了數個凹穴(cavities)80。阻劑層50可藉由蝕刻程序蝕刻，例如電漿蝕刻或採用蝕刻化學品與其他製程參數之阻劑去除。依據一實施例，阻劑層50可於包括CF4 、氬氣、氧氣、氮氣或CHF3 之一氣體、介於約50-150℃之一溫度、約800-1000瓦特之施行功率以及約40秒至1分鐘之施行時間等條件下進行蝕刻。
如第3圖所示，沈積銲錫材料90於開口55內，銲錫材料90填入了凹穴80內以及高於銅層60之開口55之一部。依據一實施例，銲錫材料90係為無鉛銲錫材料。依據部份實施例，銲錫材料90係由包含低比例之鉛之錫膏(solder paste)所形成。銲錫材料90具有低於金屬柱凸塊之一熔點。於沈積銲錫材料90之後，接著藉由一習知灰化及/或濕式去除製程以去除剩餘之阻劑層50。接著迴銲(reflow)此銲錫材料90以包覆銅層90。此迴銲製程可軟化及/或熔化銲錫材料90，但其不會軟化及或熔化銅層60，進而使得銲錫材料90可沿著銅層90之頂面與側壁而流動，或者沿著銅柱凸塊而流動並可包覆銅柱凸塊之頂面與側壁，進而形成了保護層100，如第4圖所示。包覆之銲錫材料可大體順應於銅柱凸塊之側壁而形成。於一實施例中，迴銲程序可加熱銲錫材料至介於180-320℃之溫度並施行約10-180秒之一製程時間。於其他之實施情形中，迴銲製程可採用其他之製程溫度及/或製程時間。
可採用依據本發明之實施例之用於形成具有側壁保護物之金屬柱凸塊結構之上述方法於需要形成內連物於覆晶與晶圓層級封裝中之廣泛應用中。上述方法可於製造過程中保護金屬柱凸塊的側壁，由於柱狀物的側壁於一蝕刻製程中並不遭遇化學品之劣化情形或遭遇於形成柱狀凸塊的側壁上氧化情形所導致之不良裝置表現情形。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20．．．半導體基板
30．．．保護層
40．．．晶種層
50．．．阻劑層
55．．．開口
60．．．金屬層/銅層
70．．．金屬阻障層/鎳層
80．．．凹穴
90．．．銲錫材料
100．．．保護層
第1-4圖為一系列剖面圖，顯示了依據本發明之一實施例之於形成一銅柱凸塊結構之不同階段時，其內之一半導體裝置。
20．．．半導體基板
30．．．保護層
40．．．晶種層
60．．．金屬層
70．．．金屬阻障層
100．．．保護層

Claims (10)

  1. 一種金屬柱凸塊結構之形成方法，包括：形成一保護層於一半導體基板之上；形成一導電層於該保護層之上；提供經圖案化與經過蝕刻之一阻劑層於該導電層之上，該阻劑層中定義有至少一開口；沈積一金屬層於該至少一開口內；沿著介於該阻劑層與該金屬層間之一或多個界面蝕刻部份之該阻劑層，以形成複數個凹穴；沈積一銲錫材料於該至少一開口內，該銲錫材料填入該些凹穴內以及高於該金屬層之該開口之一部內；移除剩餘之該阻劑層與未形成於該金屬層之下之該導電層；以及迴銲該銲錫材料以包覆該金屬層。
  2. 如申請專利範圍第1項所述之金屬柱凸塊結構之形成方法，其中該保護層具有擇自由一氧化物、未摻雜矽玻璃、聚亞醯胺、氮化矽、二氧化矽、氮氧化矽所組成族群內之一材料。
  3. 如申請專利範圍第1項所述之金屬柱凸塊結構之形成方法，其中該導電層包括了鈦或銅，該金屬層包括銅或銅合金。
  4. 如申請專利範圍第1項所述之金屬柱凸塊結構之形成方法，更包括形成一金屬阻障層於該金屬層之上。
  5. 如申請專利範圍第1項所述之金屬柱凸塊結構之形成方法，其中該阻劑層係經過包括CF4 、氬氣、氧氣、氮氣或CHF3 之一氣體、介於約50-150℃之一溫度、約800-1000瓦特之施行功率及約40秒至1分鐘之施行時間之蝕刻條件的蝕刻。
  6. 如申請專利範圍第1項所述之金屬柱凸塊結構之形成方法，其中迴銲該銲錫材料包覆了該導電層。
  7. 一種金屬柱凸塊結構，包括：一保護層，形成於一半導體基板之上；一導電層，形成於該保護層之上；一金屬層，形成於該導電層之上；以及一銲錫材料層，包覆該金屬層。
  8. 如申請專利範圍第7項所述之金屬柱凸塊結構，其中該保護層具有擇自由一氧化物、未摻雜矽玻璃、聚亞醯胺、氮化矽、二氧化矽、氮氧化矽所組成族群內之一材料。
  9. 如申請專利範圍第7項所述之金屬柱凸塊結構，其中該導電層包括了鈦或銅，該金屬層包括銅或銅合金，而該銲錫材料包覆了該導電層。
  10. 如申請專利範圍第7項所述之金屬柱凸塊結構，更包括一金屬阻障層，形成於該金屬層之上。
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