CN101950728A - 金属柱凸块结构及其形成方法 - Google Patents

金属柱凸块结构及其形成方法 Download PDF

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CN101950728A
CN101950728A CN2010102263126A CN201010226312A CN101950728A CN 101950728 A CN101950728 A CN 101950728A CN 2010102263126 A CN2010102263126 A CN 2010102263126A CN 201010226312 A CN201010226312 A CN 201010226312A CN 101950728 A CN101950728 A CN 101950728A
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layer
metal
cube structure
conductive layer
projection cube
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CN101950728B (zh
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曾明鸿
连永昌
陈承先
郭正铮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种金属柱凸块结构及其形成方法，该方法包括：形成一保护层于一半导体基板之上；形成一导电层于该保护层之上；提供经图案化与经过蚀刻的一阻剂层于该导电层之上，该阻剂层中定义有至少一开口；沉积一金属层于该至少一开口内；沿着介于该阻剂层与该金属层间的一或多个界面蚀刻部分的该阻剂层，以形成多个凹穴；沉积一焊锡材料于该至少一开口内，该焊锡材料填入所述多个凹穴内以及高于该金属层的该开口的一部内；移除剩余的该阻剂层与未形成于该金属层之下的该导电层；以及回焊该焊锡材料以包覆该金属层。本发明可于制造过程中保护金属柱凸块的侧壁。

Description

金属柱凸块结构及其形成方法
技术领域
本发明涉及倒装芯片(flip chip)与晶片层级(wafer-level)封装，尤其涉及一种具有侧壁保护物的金属柱凸块结构(metal pillar bump structure)及其形成方法。
背景技术
铜柱凸块(copper pillar bump)已为英特尔(intel)于2006年导入于其65纳米“Yonah”微处理器中。随着接脚数量(pin counts)与内连物密度(interconnectdensities)的增加，对于采用铜柱凸块以替代用于倒装芯片与晶片层级封装的公知焊锡凸块以外的兴趣逐渐成长。
铜柱(copper pillar)提供了优于焊锡凸块(solder bump)的数个优点，例如较高的内连物密度、较高的可靠度、较佳的电性与热表现与铅使用量的降低或消除。于焊锡回焊时，焊锡凸块会倒塌，而铜柱则维持了其于x、y、z等方向上的形状。如此使得用于更高内连物密度的更精密的凸块间距、较小的保护层开口与精细的重分布导线等制作成为可能。
然而，于制作过程中，铜柱的侧壁可能于一蚀刻过程中产生化学劣化情形，以及于后续组装接合工艺中可能于铜柱侧壁上产生氧化情形，因而造成了不良的铜可靠度以及于铜与一底胶(underfill)材料间的不良附着情形。
基于上述因素以及于后续内容中描述的其他因素，便需要用于倒装芯片与晶片层级封装的较佳铜柱凸块，以避免公知铜柱凸块所遭遇的可靠度问题。
发明内容
有鉴于此，本发明提供了金属柱凸块结构及其形成方法，以解决上述的公知问题。
依据一实施例，本发明提供了一种金属柱凸块结构，包括：
一保护层，形成于一半导体基板之上；一导电层，形成于该保护层之上；一金属层，形成于该导电层之上；以及一焊锡材料层，包覆该金属层。
依据另一实施例，本发明提供了一种金属柱凸块结构的形成方法，包括：
形成一保护层于一半导体基板之上；形成一导电层于该保护层之上；提供经图案化与经过蚀刻的一阻剂层于该导电层之上，该阻剂层中定义有至少一开口；沉积一金属层于该至少一开口内；沿着介于该阻剂层与该金属层间的一或多个界面蚀刻部分的该阻剂层，以形成多个凹穴；沉积一焊锡材料于该至少一开口内，该焊锡材料填入所述多个凹穴内以及高于该金属层的该开口的一部内；移除剩余的该阻剂层与未形成于该金属层之下的该导电层；以及回焊该焊锡材料以包覆该金属层。
本发明可于制造过程中保护金属柱凸块的侧壁，由于柱状物的侧壁于一蚀刻工艺中并不遭遇化学品的劣化情形或遭遇于形成柱状凸块的侧壁上氧化情形所导致的不良装置表现情形。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一优选实施例，并配合所附的附图，作详细说明如下：
附图说明
图1-图4为一系列剖面图，显示了依据本发明的一实施例的于形成一铜柱凸块结构的不同阶段时，其内的一半导体装置。
其中，附图标记说明如下：
20～半导体基板；
30～保护层；
40～晶种层；
50～阻剂层；
55～开口；
60～金属层/铜层；
70～金属阻障层/镍层；
80～凹穴；
90～焊锡材料；
100～保护层。
具体实施方式
图1-图4为一系列剖面图，显示了依据本发明的一实施例的于形成一铜柱凸块结构的不同阶段时，其内的一半导体装置。这些附图仅作为解说之用而非用以限制本发明。本领域普通技术人员可以理解的是这些实施情形也可具有其他变化、修改与选择情形。
图1显示了依据本发明的一实施例的一半导体基板20。半导体基板20可为一半导体工艺晶片(例如为200厘米、300厘米、400厘米等的硅晶片)且可包括借由先前工艺所形成的金属层、绝缘层、装置构件等构件。半导体基板20可为单晶或多晶硅的基板。可以理解的是，半导体基板20可包括外延硅层、绝缘层上覆硅、硅锗或砷化镓等实施情形。
接着于半导体基板20之上形成一保护层(passivation layer)30。保护层30可为一或多个膜层，且可包括一材料，例如为氧化物、未掺杂硅玻璃(undopedsilicate glass，USG)、氮化硅、二氧化硅、氮氧化硅或聚亚酰胺。虽然未显示于图1中，本领域普通技术人员可以理解的是，于保护层30内可包括如接触垫(contact pads)与金属导线(metal lines)等导电膜层，借以电性接触位于上方的一铜柱凸块。保护层30可借由如化学气相沉积或旋转涂布技术的沉积技术而沉积于半导体基板20之上。化学气相沉积可包括低压化学气相沉积(LPCVD)、等离子体加强型化学气相沉积(PECVD)、或大气压化学气相沉积(APCVD)等方法。于一实施例中，保护层30包括一氧化物与一氮化物，且沉积至约为2000-12000埃的一厚度。于其他实施例中，保护层30具有约为2000-6000埃的一厚度。
接着于保护层30之上形成一导电层或一晶种层(seed layer)40，以避免金属扩散情形。举例来说，晶种层40可包括钛或铜，且可借由如溅镀(sputtering)、蒸镀(evaporation)或其他的沉积技术所形成。于一实施例中，晶种层40沉积至约介于1000-8000埃的一厚度。
请继续参照图1，接着形成阻剂层50于晶种层40之上。阻剂层50作为金属沉积工艺的模具之用，例如为于形成铜柱凸块时的铜电镀之用。本领域普通技术人员可以理解的是，阻剂的材料为一种适用于涂布、曝光、显影、电镀与利用装备及适当工艺化学品以进行去除(stripping)的材料。于一实施例中，阻剂层50包括化学增幅的正型阻剂，其具有高度对比与解析度以及具有约为60-120微米的一厚度。接着借由一光刻图案化工艺及经过显影之后而图案化阻剂层50，借以形成一或多个开口55。
接着于阻剂层50的开口55内沉积一金属层或一铜层60。铜层60也可包括铜合金。如金、银、铝、锡-金、与锡-铜等具有良好导电率的金属或合金均可作为替代材料之用。铜层60可借由铜电镀(copper electroplating)工艺或无电电镀(electrodeless plating)工艺而沉积于开口55之内。于一实施例中，铜层60沉积于基板20上至介于约40-80微米的一厚度。于采用电镀工艺的一实施例中，阻剂层50的开口55经过电镀而形成铜或其他铜合金材料，以形成经电镀的铜柱的第一膜层。可更接着形成额外的膜层。于施行上述电镀工艺之前，可使用3-5倍稀释的硫酸溶液处理半导体基板20约3分钟，以移除油、油渍、氧化物与其他污染物，如此可确保半导体基板20与经电镀膜层的铜柱间的较佳的附着情形。于另一实施例中，铜电镀的最佳电流密度约为3-7ASD(A/cm2)，且可使用任何电流密度。于此实施例中，于0.5ASD条件下电镀的沉积速率可达到0.3微米/每分钟，且其可正比于电流密度。
于形成铜柱之后，可形成选择性的一金属阻障层，或一镍层70于铜层60的表面上。镍层70可防止了铜扩散进入后续形成的焊锡材料之内。
请参照图2，沿着介于阻剂层50与铜层60间的一或多个介面处的蚀刻移除阻剂层50的多个部分之后，形成了数个凹穴(cavities)80。阻剂层50可借由蚀刻程序蚀刻，例如等离子体蚀刻或采用蚀刻化学品与其他工艺参数的阻剂去除。依据一实施例，阻剂层50可于包括CF4、氩气、氧气、氮气或CHF3的一气体、介于约50-150℃的一温度、约800-1000瓦特的施行功率以及约40秒至1分钟的施行时间等条件下进行蚀刻。
如图3所示，沉积焊锡材料90于开口55内，焊锡材料90填入了凹穴80内以及高于铜层60的开口55的一部。依据一实施例，焊锡材料90为无铅焊锡材料。依据部分实施例，焊锡材料90由包含低比例的铅的锡膏(solderpaste)所形成。焊锡材料90具有低于金属柱凸块的一熔点。于沉积焊锡材料90之后，接着借由一公知灰化及/或湿式去除工艺以去除剩余的阻剂层50。接着回焊(reflow)此焊锡材料90以包覆铜层90。此回焊工艺可软化及/或熔化焊锡材料90，但其不会软化及或熔化铜层60，进而使得焊锡材料90可沿着铜层90的顶面与侧壁而流动，或者沿着铜柱凸块而流动并可包覆铜柱凸块的顶面与侧壁，进而形成了保护层100，如图4所示。包覆的焊锡材料可大体顺应于铜柱凸块的侧壁而形成。于一实施例中，回焊程序可加热焊锡材料至介于180-320℃的温度并施行约10-180秒的一工艺时间。于其他的实施情形中，回焊工艺可采用其他的工艺温度及/或工艺时间。
可采用依据本发明的实施例的用于形成具有侧壁保护物的金属柱凸块结构的上述方法于需要形成内连物于倒装芯片与晶片层级封装中的广泛应用中。上述方法可于制造过程中保护金属柱凸块的侧壁，由于柱状物的侧壁于一蚀刻工艺中并不遭遇化学品的劣化情形或遭遇于形成柱状凸块的侧壁上氧化情形所导致的不良装置表现情形。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种金属柱凸块结构的形成方法，包括：
形成一保护层于一半导体基板之上；
形成一导电层于该保护层之上；
提供经图案化与经过蚀刻的一阻剂层于该导电层之上，该阻剂层中定义有至少一开口；
沉积一金属层于该至少一开口内；
沿着介于该阻剂层与该金属层间的一或多个界面蚀刻部分的该阻剂层，以形成多个凹穴；
沉积一焊锡材料于该至少一开口内，该焊锡材料填入所述多个凹穴内以及高于该金属层的该开口的一部内；
移除剩余的该阻剂层与未形成于该金属层之下的该导电层；以及
回焊该焊锡材料以包覆该金属层。
2.如权利要求1所述的金属柱凸块结构的形成方法，其中该保护层具有择自由一氧化物、未掺杂硅玻璃、聚亚酰胺、氮化硅、二氧化硅、氮氧化硅所组成族群内的一材料。
3.如权利要求1所述的金属柱凸块结构的形成方法，其中该导电层包括了钛或铜，该金属层包括铜或铜合金。
4.如权利要求1所述的金属柱凸块结构的形成方法，还包括形成一金属阻障层于该金属层之上。
5.如权利要求1所述的金属柱凸块结构的形成方法，其中该阻剂层经过包括CF4、氩气、氧气、氮气或CHF3的一气体、介于约50-150℃的一温度、约800-1000瓦特的施行功率及约40秒至1分钟的施行时间的蚀刻条件的蚀刻。
6.如权利要求1所述的金属柱凸块结构的形成方法，其中回焊该焊锡材料包覆了该导电层。
7.一种金属柱凸块结构，包括：
一保护层，形成于一半导体基板之上；
一导电层，形成于该保护层之上；
一金属层，形成于该导电层之上；以及
一焊锡材料层，包覆该金属层。
8.如权利要求7所述的金属柱凸块结构，其中该保护层具有择自由一氧化物、未掺杂硅玻璃、聚亚酰胺、氮化硅、二氧化硅、氮氧化硅所组成族群内的一材料。
9.如权利要求7所述的金属柱凸块结构，其中该导电层包括了钛或铜，该金属层包括铜或铜合金，而该焊锡材料包覆了该导电层。
10.如权利要求7所述的金属柱凸块结构，还包括一金属阻障层，形成于该金属层之上。
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CN104022090B (zh) * 2013-02-28 2018-01-23 日月光半导体制造股份有限公司 半导体接合结构及方法，以及半导体芯片
CN107017169A (zh) * 2015-11-16 2017-08-04 台湾积体电路制造股份有限公司 导电外部连接器结构、半导体器件及形成方法
CN107017169B (zh) * 2015-11-16 2020-01-10 台湾积体电路制造股份有限公司 导电外部连接器结构、半导体器件及形成方法

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