CN104022090A - 半导体接合结构及方法，以及半导体芯片 - Google Patents

半导体接合结构及方法，以及半导体芯片 Download PDF

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Publication number
CN104022090A
CN104022090A CN201310064575.5A CN201310064575A CN104022090A CN 104022090 A CN104022090 A CN 104022090A CN 201310064575 A CN201310064575 A CN 201310064575A CN 104022090 A CN104022090 A CN 104022090A
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metal
cylinder
semiconductor
zone line
layer
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CN104022090B (zh
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陈国华
林慈桦
陈冠能
黄彦斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201310064575.5A priority Critical patent/CN104022090B/zh
Priority to US14/192,029 priority patent/US9196595B2/en
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明关于一种半导体接合结构及方法，以及半导体芯片。该半导体接合结构依序包括一第一柱体、一第一界面、一中间区域、一第二界面及一第二柱体。该第一柱体、该第二柱体及该中间区域包含一第一金属。该第一界面及该第二界面包含该第一金属及一第二金属氧化物，其中该第一金属在该第一界面及该第二界面中的含量比例小于该第一金属在该中间区域中的含量比例。

Description

半导体接合结构及方法,以及半导体芯片
技术领域
本发明关于一种半导体接合结构及方法，以及半导体芯片，详言之，关于一种不需使用焊料且可在低温环境下完成的半导体接合结构及方法。
背景技术
已知半导体覆晶接合方法中，会在上芯片的金属柱(Metal Pillar)上镀上一层镍层作为障蔽层(Barrier Layer)，之后再将焊料形成于该镍层上。接着，将该上芯片置放于一下芯片或一基板上，使得该金属柱上的焊料接触该下芯片或该基板上的焊垫上的表面处理层。接着，进行回焊工艺，使得该焊料融化而接合于该焊垫上，以形成一覆晶接合结构。
该已知方法中，必须使用焊料。由于焊料的外径无法有效地缩小，因此，该金属柱之间的间距无法有效地减少。此外，为了使焊料达到熔融状态，必须加温至高于300℃，而在此高温环境下，该上芯片、该下芯片或该基板容易发生翘曲，而且该金属柱容易发生氧化。为了避免该金属柱的氧化，另一种已知技术将此高温接合步骤改至真空环境下进行，如此，将会增加制造成本，然而仍无法解决翘曲的问题。
因此，有必要提供一种半导体接合结构及方法，以及半导体芯片，以解决上述问题。
发明内容
本揭露的一方面关于一种半导体接合结构。在一实施例中，该半导体接合结构包括一第一柱体、一第二柱体、一中间区域、一第一界面及一第二界面。该第一柱体包含一第一金属。该第二柱体包含该第一金属。该中间区域位于该第一柱体及该第二柱体之间，且包含该第一金属。该第一界面位于该第一柱体及该中间区域之间，且包含该第一金属及一第二金属氧化物，其中该第一金属在该第一界面中的含量比例小于该第一金属在该中间区域中的含量比例。该第二界面位于该第二柱体及该中间区域之间，且包含该第一金属及该第二金属氧化物，其中该第一金属在该第二界面中的含量比例小于该第一金属在该中间区域中的含量比例。
本揭露的另一方面关于一种半导体芯片。在一实施例中，该半导体芯片包括一芯片本体、一布线层、一保护层、一球下金属层(UBM)、一柱体及一扩散层。该芯片本体具有一第一表面。该布线层位于该芯片本体的第一表面上。该保护层位于该芯片本体的第一表面上，且具有一开口，以显露部分该布线层。该球下金属层位于该保护层的开口，且接触该布线层。该柱体位于该球下金属层上，该柱体包含一第一金属，该第一金属选自由银、金、铝及铜所组成的群。该扩散层位于该柱体的末端，该扩散层包含一第二金属，该第二金属与该第一金属不同，且该第二金属选自由银、金、铂、钯、锇、铱、钌、钛、镁、铝、铜、钴、镍及锌所组成的群。该扩散层的厚度介于1纳米至30纳米之间。
本揭露的另一方面关于一种半导体接合方法。在一实施例中，该半导体接合方法包括以下步骤：(a)提供一第一半导体元件及一第二半导体元件，该第一半导体元件具有至少一第一柱体及至少一第一扩散层，该第一柱体包含一第一金属，该第一扩散层位于该第一柱体的末端且包含一第二金属，该第二半导体元件具有至少一第二柱体及至少一第二扩散层，该第二柱体包含该第一金属，该第二扩散层位于该第二柱体的末端且包含该第二金属，该扩散层的厚度介于1纳米至30纳米之间；(b)将该第一半导体元件对接该第二半导体元件，使得该第一扩散层接触该第二扩散层；及(c)对该第一半导体元件及该第二半导体元件施加一对接压力，且持续一段时间，使得该第一柱体的第一金属朝向该第二柱体扩散，该第二柱体的第一金属朝向该第一柱体扩散，而接触后形成中间区域；该第一扩散层的第二金属氧化物朝向该第一柱体扩散而与该第一金属混合后形成一第一界面；该第二扩散层的第二金属氧化物朝向该第二柱体扩散而与该第一金属混合后形成一第二界面。
附图说明
图1显示本发明半导体封装结构的一实施例的剖视示意图；
图2显示图1的半导体封装结构中该第一半导体元件及该第二半导体元件间的接合结构的一实施例的区域A的放大示意图；
图3显示图2的接合结构的穿透式电子显微镜(TEM)分析图；及
图4至图7显示本发明半导体接合方法的一实施例的示意图。
具体实施方式
参考图1，显示本发明半导体封装结构的一实施例的剖视示意图。该半导体封装结构1包括一基材10、数个外接焊球36、一第一半导体元件38、一第一底胶40、一第二半导体元件42、一第二底胶46及一封胶材料48。
该基材10为一硅基材、一晶圆或一玻璃基材，其具有一上表面101、一下表面102、一上电路层20、一下电路层30、一上保护层32及一下保护层34。该上电路层20位于该基材10的上表面101，且该下电路层30位于该基材10的下表面102。该上保护层32覆盖该上电路层20及该基材10的上表面101，且具有数个开口以显露部分该上电路层20。该下保护层34覆盖该下电路层34及该基材10的下表面102，且具有数个开口以显露部分该下电路层34。在本实施例中，该上电路层20、该下电路层30的材质为铜，且该上保护层32及该下保护层34为防焊层，其材质例如聚酰亚胺(Polyimide，PI)。该等外接焊球36位于该显露的下电路层30上，以供外界连接之用。
该第一半导体元件38为一芯片或一中介板(Interposer)，且包含一第一半导体元件本体380(例如：芯片本体或中介板本体)、一上布线层383、一下布线层384、数个导电通道385、一下保护层387、一上保护层388、数个第一球下金属层(UBM)389、数个第一柱体50及数个焊球39。该第一半导体元件本体380具有一上表面381及一下表面382。该上布线层383及该下布线层384分别位于该第一半导体元件本体380的上表面381及下表面382。在本实施例中，该上布线层383及该下布线层384包括数个条电性绝缘的线段，其材质为铝、铜或铝铜。
该等导电通道385贯穿该第一半导体元件本体380，且接触及电性连接该上布线层383及该下布线层384。该下保护层387覆盖该下布线层384及该第一半导体元件本体380的下表面382，且具有数个开口以显露部分该下布线层384。该上保护层388覆盖该上布线层383及该第一半导体元件本体380的上表面381，且具有数个开口以显露部分该上布线层383。
该等第一球下金属层(UBM)389位于该上保护层388的开口，且接触该上布线层383。该等第一柱体50位于该等第一球下金属层389上。该等焊球39接触且电性连接该显露的下布线层384及该显露的上线路层20。该第一底胶40位于该第一半导体元件本体380及该基材10之间以保护该等焊球39。在本实施例中，该上保护层388及该下保护层387为防焊层，其材质例如聚酰亚胺(Polyimide，PI)。
该第二半导体元件42为一芯片，且包含一第二半导体元件本体420(例如：芯片本体)、一布线层422、一保护层425、数个第二球下金属层(UBM)423及数个第二柱体52。该第二半导体元件本体420具有一第一表面421。该布线层422位于该第二半导体元件本体420的第一表面421。在本实施例中，该布线层422包括数个条电性绝缘的线段，其材质为铝、铜或铝铜。
该保护层425覆盖该布线层422及该第二半导体元件本体420的第一表面421，且具有数个开口以显露部分该布线层422。该第二球下金属层(UBM)423位于该保护层425的开口，且接触该布线层422。该等第二柱体52位于该等第二球下金属层423上，且与该等第一柱体50物理接合及电性连接。该保护层425可以是一防焊层(其材质例如聚酰亚胺(Polyimide，PI))或一钝化层(其材质为金属氧化物)。
该第二底胶46位于该第一半导体元件38及该第二半导体元件42之间以保护该等第一柱体50及该等第二柱体52。该封胶材料48位于该基材10的上表面101上，以包覆该第一半导体元件38、该第二半导体元件42、该第一底胶40及该第二底胶46。可以理解的是，该第一底胶40及该第二底胶46也可以省略。
参考图2，显示图1的半导体封装结构中该第一半导体元件及该第二半导体元件间的接合结构的一实施例的区域A的放大示意图。在本实施例中，该半导体接合结构包括一第一柱体50、一第二柱体52、一中间区域54、一第一界面56及一第二界面58。该第一柱体50位于该第一半导体元件38的该第一球下金属层389上，且包含一第一金属。该第二柱体52位于该第二半导体元件40的该第二球下金属层423上，且包含该第一金属。该第一金属选自由银、金、铝及铜所组成的群。在本实施例中，该第一金属为铜，亦即该该第一柱体50及该第二柱体52皆为铜金属柱。该中间区域54位于该第一柱体50及该第二柱体52之间，且包含该第一金属。
该第一界面56位于该第一柱体50及该中间区域54之间，且包含该第一金属及一第二金属氧化物，其中该第一金属在该第一界面56中的含量比例小于该第一金属在该中间区域54中的含量比例。同样地，该第二界面58位于该第二柱体52及该中间区域54之间，且包含该第一金属及该第二金属氧化物，其中该第一金属在该第二界面58中的含量比例小于该第一金属在该中间区域54中的含量比例。
该第一金属与该第二金属不同，该第二金属选自由银、金、铂、钯、锇、铱、钌、钛、镁、铝、铜、钴、镍及锌所组成的群。在本实施例中，该第二金属为钛，该第二金属氧化物为二氧化钛。要注意的是，该中间区域54、该第一柱体50及该第二柱体52不包含该第二金属氧化物(即二氧化钛)。
在本实施例中，该第一界面56接触该第一柱体50及该中间区域54，且该第二界面58接触该第二柱体52及该中间区域54。然而，在其他实施例中，该第一界面56为一不连续的界面(亦即，其非一完整平面)，使得该第一柱体50接触该中间区域54，且该第二界面58为一不连续的界面(亦即，其非一完整平面)，使得该第二柱体52接触该中间区域54。该第一柱体50、该第二柱体52及该中间区域54主要皆为金属材料，特别为高导电性的金属材料，因此可经由彼此的接触提高电性连结的效果。
参考图3，显示图2的接合结构的穿透式电子显微镜(TEM)分析图，其中曲线60代表铜元素所占的比例，曲线62代表氧元素所占的比例，曲线64代表钛元素所占的比例。在该第一柱体50、该中间区域54及该第二柱体52中，铜元素所占比例约为90％以上，其他则为氧元素。换言之，该第一柱体50、该中间区域54及该第二柱体52三者所含元素及其比例大致上是相同的。在该第一界面56及该第二界面58中，铜元素所占比例降至90％以下，氧元素所占比例大幅提高(大于10％以上)，且增加了钛元素，因此可推知其内含钛的氧化物(二氧化钛)。由图中可看出，铜元素在该第一界面56及该第二界面58中的含量比例小于其在该中间区域54中的含量比例，同时也小于其在该第一柱体50及该第二柱体52中的含量比例。氧元素在该第一界面56及该第二界面58中的含量比例大于其在该中间区域54中的含量比例。该中间区域54、该第一柱体50及该第二柱体52不包含二氧化钛。
在本实施例的该接合结构中，不须使用焊料即可实现铜铜对接，因此，该等第一柱体50之间的间距或该等第二柱体52之间的间距可以有效地减少，而达到微间距(Fine Pitch)。此外，该接合结构可在低温下(低于180℃)完成，而不易发生翘曲的情形。此外，该接合结构的推力测试可达37kg/cm2，显示其结合效果相当好。
参考图4至图7，显示本发明半导体接合方法的一实施例的示意图。参考图4及图4a，其中图4a为图4的局部放大示意图。提供该第一半导体元件38至一平台70。该第一半导体元件38包含该第一半导体元件本体380、该上布线层383、该下布线层384、该等导电通道385、该下保护层387、该上保护层388、该等第一球下金属层(UBM)389、该等第一柱体50及数个第一扩散层55。该上布线层383及该下布线层384分别位于该第一半导体元件本体380的上表面381及下表面382。该等导电通道385贯穿该第一半导体元件本体380，且接触及电性连接该上布线层383及该下布线层384。该下保护层387覆盖该下布线层384及该第一半导体元件本体380的下表面382，且具有数个开口以显露部分该下布线层384。该上保护层388覆盖该上布线层383及该第一半导体元件本体380的上表面381，且具有数个开口以显露部分该上布线层383。该等第一球下金属层(UBM)389位于该上保护层388的开口，且接触该上布线层383。该等第一柱体50位于该等第一球下金属层389上。该等第一扩散层55位于该等第一柱体50的末端，其厚度介于1纳米(nm)至纳米30(nm)之间，较佳为5纳米(nm)至纳米30(nm)之间。该第一柱体50包含该第一金属，且该第一扩散层55包含该第二金属。
参考图5及图5a，其中图5a为图5的局部放大示意图。提供该第二半导体元件42至一热压头72。该第二半导体元件42为一芯片，且包含该第二半导体元件本体420、该布线层422、该保护层425、该等第二球下金属层(UBM)423、该等第二柱体52及数个第二扩散层57。该布线层422位于该第二半导体元件本体420的第一表面421。该保护层425覆盖该布线层422及该第二半导体元件本体420的第一表面421，且具有数个开口以显露部分该布线层422。该第二球下金属层(UBM)423位于该保护层425的开口，且接触该布线层422。该等第二柱体52位于该等第二球下金属层423上。该等第二扩散层57位于该等第二柱体52的末端，其厚度介于1纳米(nm)至纳米30(nm)之间，较佳为5纳米(nm)至纳米30(nm)之间。该第二柱体52包含该第一金属，且该第二扩散层57包含该第二金属。
参考图6及图6a，其中图6a为图6的局部放大示意图。向下移动该热压头72，以将该第一半导体元件38对接该第二半导体元件42，使得该第一扩散层55接触该第二扩散层57。
参考图7，对该第一半导体元件38及该第二半导体元件42施加一对接压力，且持续一段时间。在本实施例中，该对接压力为100牛顿，且持续约50分钟。同时，于常压(约1大气压)下利用该平台70及该热压头72分别加热该第一柱体50、该第一扩散层55、该第二柱体52及该第二扩散层57，以提供一对接温度，其中该对接温度低于180℃，较佳为高于150℃且低于180℃，使得该第一扩散层55及该第二扩散层57形成该第二金属的氧化物(即二氧化钛)。要注意的是，本实施例不需在真空环境下进行，因此没有抽真空的步骤，因此可具有容易制作及成本较低的优点。
此时，该第一柱体50的第一金属(铜)朝向该第二柱体52(向上)扩散，该第二柱体52的第一金属(铜)朝向该第一柱体50(向下)扩散，而在中央接触且融合后形成该中间区域54。同时，该第一扩散层55的第二金属氧化物(二氧化钛)朝向该第一柱体50(向下)扩散而与该第一金属混合后形成该第一界面56；该第二扩散层57的第二金属氧化物(二氧化钛)朝向该第二柱体52(向上)扩散而与该第一金属混合后形成该第二界面58，以形成如图2所示的接合结构。
在该接合结构中，该中间区域54位于该第一柱体50及该第二柱体52之间，且包含该第一金属(即铜)，而不包含该第二金属氧化物(即二氧化钛)。该第一界面56夹设于位于该第一柱体50及该中间区域54之间，且包含该第一金属及该第二金属氧化物，其中该第一金属在该第一界面56中的含量比例小于该第一金属在该中间区域54中的含量比例。同样地，该第二界面58夹设于于该第二柱体52及该中间区域54之间，且包含该第一金属及该第二金属氧化物，其中该第一金属在该第二界面58中的含量比例小于该第一金属在该中间区域54中的含量比例。
在本实施例的该接合方法中，不须使用焊料即可实现铜铜对接(即该第一柱体50及该第二柱体52对接)，因此，该等第一柱体50之间的间距或该等第二柱体52之间的间距可以有效地减少，而达到微间距(Fine Pitch)。此外，该接合方法可在低温下(低于180℃)进行，使得该第一半导体元件38及该第二半导体元件42不易发生翘曲的情形，且该第一柱体50及该第二柱体52不易氧化。再者，该接合方法不需在真空环境下进行，如此，将不会增加抽真空的制造成本，此外，该接合结构的推力测试可达37kg/cm2，显示其结合效果相当好。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如后权利要求书所列。

Claims (10)

1.一种半导体接合结构，其特征在于，包括：
一第一柱体，包含一第一金属；
一第二柱体，包含该第一金属；
一中间区域，位于该第一柱体及该第二柱体之间，且包含该第一金属；
一第一界面，位于该第一柱体及该中间区域之间，且包含该第一金属及一第二金属氧化物，其中该第一金属在该第一界面中的含量比例小于该第一金属在该中间区域中的含量比例；及
一第二界面，位于该第二柱体及该中间区域之间，且包含该第一金属及该第二金属氧化物，其中该第一金属在该第二界面中的含量比例小于该第一金属在该中间区域中的含量比例。
2.如权利要求1的半导体接合结构，其特征在于，该第一金属与该第二金属不同，该第一金属选自由银、金、铝及铜所组成的群，该第二金属选自由银、金、铂、钯、锇、铱、钌、钛、镁、铝、铜、钴、镍及锌所组成的群。
3.如权利要求1的半导体接合结构，其特征在于，该第一界面接触该第一柱体及该中间区域，且该第二界面接触该第二柱体及该中间区域。
4.如权利要求1的半导体接合结构，其特征在于，该第一界面为一不连续的界面，使得该第一柱体接触该中间区域，且该第二界面为一不连续的界面，使得该第二柱体接触该中间区域。
5.一种半导体芯片，其特征在于，包括：
一芯片本体，具有一第一表面；
一布线层，位于该芯片本体的第一表面上；
一保护层，位于该芯片本体的第一表面上，且具有一开口，以显露部分该布线层；
一球下金属层，位于该保护层的开口，且接触该布线层；
一柱体，位于该球下金属层上，该柱体包含一第一金属，该第一金属选自由银、金、铝及铜所组成的群；及
一扩散层，位于该柱体的末端，该扩散层包含一第二金属，该第二金属与该第一金属不同，且该第二金属选自由银、金、铂、钯、锇、铱、钌、钛、镁、铝、铜、钴、镍及锌所组成的群，该扩散层的厚度介于1纳米至30纳米之间。
6.一种半导体接合方法，其特征在于，包括：
(a)提供一第一半导体元件及一第二半导体元件，该第一半导体元件具有至少一第一柱体及至少一第一扩散层，该第一柱体包含一第一金属，该第一扩散层位于该第一柱体的末端且包含一第二金属，该第二半导体元件具有至少一第二柱体及至少一第二扩散层，该第二柱体包含该第一金属，该第二扩散层位于该第二柱体的末端且包含该第二金属，该扩散层的厚度介于1纳米至30纳米之间；
(b)将该第一半导体元件对接该第二半导体元件，使得该第一扩散层接触该第二扩散层；及
(c)对该第一半导体元件及该第二半导体元件施加一对接压力，且持续一段时间，使得该第一柱体的第一金属朝向该第二柱体扩散，该第二柱体的第一金属朝向该第一柱体扩散，而接触后形成中间区域；该第一扩散层的第二金属氧化物朝向该第一柱体扩散而与该第一金属混合后形成一第一界面；该第二扩散层的第二金属氧化物朝向该第二柱体扩散而与该第一金属混合后形成一第二界面。
7.如权利要求6的半导体接合方法，其特征在于，该步骤(c)中，更提供一对接温度，其中该对接温度低于180℃。
8.如权利要求6的半导体接合方法，其特征在于，该步骤(a)中，该第一金属与该第二金属不同，该第一金属选自由银、金、铝及铜所组成的群，该第二金属选自由银、金、铂、钯、锇、铱、钌、钛、镁、铝、铜、钴、镍及锌所组成的群。
9.如权利要求6的半导体接合方法，其特征在于，该步骤(c)中，该第一界面接触该第一柱体及该中间区域，且该第二界面接触该第二柱体及该中间区域。
10.如权利要求6的半导体接合方法，其特征在于，该步骤(c)中，该第一界面为一不连续的界面，使得该第一柱体接触该中间区域，且该第二界面为一不连续的界面，使得该第二柱体接触该中间区域。
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