CN102201375A - 集成电路装置及封装组件 - Google Patents

集成电路装置及封装组件 Download PDF

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Publication number
CN102201375A
CN102201375A CN2010102570393A CN201010257039A CN102201375A CN 102201375 A CN102201375 A CN 102201375A CN 2010102570393 A CN2010102570393 A CN 2010102570393A CN 201010257039 A CN201010257039 A CN 201010257039A CN 102201375 A CN102201375 A CN 102201375A
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China
Prior art keywords
layer
bottom metal
metal layer
bump bottom
copper
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CN2010102570393A
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English (en)
Inventor
黄见翎
吴逸文
王俊杰
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN201510711114.1A priority Critical patent/CN105390473B/zh
Publication of CN102201375A publication Critical patent/CN102201375A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种集成电路装置及封装组件，该集成电路装置包括：半导体基板；第一凸块底金属层形成于半导体基板之上；第二凸块底金属层形成于第一凸块底金属层之上且具有侧面；导电柱形成于第二凸块底金属层之上且具有侧面与顶面；保护结构形成于导电柱的侧面与第二凸块底金属层的侧面之上；其中保护结构由非金属材料所形成而导电柱由含铜层所形成。本发明提供了用于铜柱凸块技术的侧壁保护工艺，其于铜柱凸块的侧壁上形成由例如一介电材料层、一聚合物层或上述膜层的组合的至少一种非金属的材料膜层所形成的一保护结构。本发明可调整基板的应力，避免了于回焊工艺中沿着凸块底金属层的周围的铜柱的焊锡湿润情形，因此适用于精细间距凸块技术。

Description

集成电路装置及封装组件
技术领域
本发明涉及集成电路制作，尤其涉及集成电路装置内所应用的凸块结构(bump structure)。
背景技术
当今的集成电路由如晶体管或电容的数百万个装置所形成。这些装置之间起初为相分隔的，然而之后将相互地经过内部连结而形成功能性电路。内连结构通常包括如金属导线(连接线)的横向内连情形与如介层物(via)与接触物(contact)等的垂直内连情形。这些内连情形逐渐地决定了当今集成电路的表现与密度的极限。于内连结构的顶部上，形成有焊垫(bond pad)并露出各芯片的表面。可通过焊垫以形成连结芯片与基板或另一芯片的电性连接情形。焊垫可用于打线接合(wire bonding)或倒装芯片接合(flip-chip bonding)等接合情形。
倒装芯片封装技术利用了凸块(bump)以建立介于一芯片的输出/输入焊垫(I/O pads)与基板或封装物的导线架之间的电性连接关系。结构上而言，凸块实际上包括了凸块其本身与位于凸块与输出/输入焊垫之间的所谓的凸块底金属层(under bump metallurgy，UBM)。凸块底金属层通常包括一粘着层、一阻障层与一湿润层，并按照上述顺序而设置于输出/输入焊垫之上。基于凸块其本身的使用材料，则可细分为焊锡凸块(solder bumps)、金凸块(goldbumps)、铜柱凸块(copper pillar bump)以及采用混合材料的凸块。近年来已发展出了铜柱凸块技术。于取代锡球凸块的使用情形中，电子元件借由一铜柱凸块而连结于一基板，如此可于最小的凸块桥接可能情形下以达成了更细的间距，进而降低了电路的负载电容(capacitance load)，并使得电子元件可于更高频率下操作。
铜柱凸块倒装芯片组件(Cu pillar bump flip-chip assembly)具有下述优点：(1)较佳热/电性表现、(2)高电流承载能力、(3)对于电致变迁的较佳阻抗能力，因而具有较长的凸块寿命、(4)可最小化模塑孔洞(molding voids)，即于铜柱凸块之间可形成有较为一致的空隙。此外，借由使用铜柱而达成焊锡分布的控制便可应用较为便宜的基板与消除无铅泪珠设计。然而，铜于制造过程中具有氧化的倾向。经氧化的铜柱将导致了电子构件与基板之间的不良附着情形。如此的不良附着情形可基于高漏电流情形而导致了严重的可靠性问题。经氧化的铜柱也可导致了沿着底胶与铜柱间介面的底胶破裂情形。这些破裂可能迁移至下方的低介电常数介电层或至用于连结铜柱与基板间的凸块处。因此，便需要一侧壁保护层以避免铜的氧化，但是用于制造铜柱侧壁物的公知方法受到高制造成本与介面剥落等问题的困扰。目前，采用浸润式锡工艺以于铜柱侧壁上形成一锡层，然而上述技术仍存在有关于制造成本、锡与底胶间的附着情形等问题，以及于侧壁上的焊锡的湿润问题，上述问题为新世代芯片中用于精密间距封装技术的一大挑战。
发明内容
有鉴于此，本发明提供了一种集成电路装置及封装组件，以解决上述问题。
依据一实施例，本发明提供了一种集成电路装置，包括：
一半导体基板；一第一凸块底金属层，形成于该半导体基板之上；一第二凸块底金属层，形成于该第一凸块底金属层之上，具有一侧面；一导电柱，形成于该第二凸块底金属层之上，具有一侧面与一顶面；以及一保护结构，形成于该导电柱的该侧面与该第二凸块底金属层的该侧面之上；其中该保护结构由一非金属材料所形成，而该导电柱由一含铜层所形成。
依据另一实施例，本发明提供了一种集成电路装置，包括：
一半导体基板；一凸块结构，形成于该半导体基板之上；以及一非金属的保护结构，覆盖至少该凸块结构的侧壁的一部；其中该凸块结构包括形成于该半导体基板之上的一凸块底金属层以及形成于该凸块底金属层之上的一铜柱。
依据又一实施例，本发明提供了一种封装组件，包括：
一第一基板；一凸块结构，形成于该第一基板之上，其中该凸块结构包括形成于该第一基板之上的一凸块底金属层以及形成于该凸块底金属层之上的一铜柱；一非金属的保护结构，覆盖至少该凸块结构的侧壁的一部；一第二基板；以及一接合焊锡层，形成于该第二基板与该凸块结构之间。
本发明可调整基板的应力，并避免了于回焊工艺中沿着凸块底金属层的周围的铜柱的焊锡湿润情形。因此其适用于精细间距凸块技术。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一优选实施例，并配合所附的附图，作详细说明如下：
附图说明
图1A-图1F为一系列剖面图，显示了依据本发明一实施例的铜柱凸块工艺中的不同阶段内的一半导体装置的一部；
图2A-图2D为一系列剖面图，显示了依据本发明另一实施例的铜柱凸块工艺中的不同阶段内的一半导体装置的一部；
图3A-图3F为一系列剖面图，显示了依据本发明又一实施例的铜柱凸块工艺中的不同阶段内的一半导体装置的一部；以及
图4A-图4G为一系列剖面图，显示了依据本发明另一实施例的铜柱凸块工艺中的不同阶段内的一半导体装置的一部。
其中，附图标记说明如下：
10～半导体基板；
12～凸块底金属层；
14～第一凸块底金属层；
14a～第一凸块底金属层的一部；
14”～经图案化的第一凸块底金属层；
14a”～周围表面；
16～第二凸块底金属层；
16”～经图案化的第二凸块底金属层；
16b～图案化的第二凸块底金属层的侧面；
18～掩模层；
19～开口；
20～铜层/铜柱；
20a～铜层/铜柱的顶面；
20b～铜层/铜柱的侧面；
22～保护层；
22a～侧壁间隔物/侧壁保护结构；
24～凸块结构；
30～阻障层；
32～凸块结构；
40～上盖层；
40a～上盖层的顶面；
40b～上盖层的侧面；
42～第一金属膜层；
44～第二金属膜层；
46～凸块结构；
50～焊锡层；
50a～焊锡层的顶面；
50b～焊锡层的侧面；
52～凸块结构；
100～基板；
102～接合焊锡层；
104～接合结构；
200～封装组件；
具体实施方式
本发明提供了数个适用于铜柱凸块技术的侧壁保护工艺的实施例，侧壁保护工艺中于铜柱凸块的侧壁上形成包括至少如一介电材料层、一聚合物材料层或上述材料膜层的组合等多个非金属材料膜层其中之一的保护结构。于下文中所采用的“铜柱凸块(Cu pillar bump)”指一凸块结构包括由铜或铜合金所形成的一导电柱(一柱子或一支撑座)。铜柱凸块可直接应用于倒装芯片组件的一半导体芯片的导电接垫或一重分布层之上或应用于其他的相似应用中。
于下文中借由对应的附图以详细解说本发明的范例与实施例。可能的话，于附图与描述中采用了相同的标记以代表相同或类似的构件。于附图中，基于清楚与方便的目的，实施例的形状或厚度可夸大显示。另外，附图中各元件的部分将分别描述说明，值得注意的是，图中未特别示出或描述的元件可能具有不同的形态。另外，当一膜层为位于另一膜层之上或位于一基板之上时，此膜层可能直接地位于其他膜层之上或基板之上，或者是其间存在有中间的膜层。于下文中关于“某一实施例”或“一实施例”内的参考内容表示了相关于包括至少一实施例的此实施例的一特定构件、结构或特性。因此，于不同处的“于某一实施例中”或“于一实施例中”等描述并非相关于相同的实施例。另外，于一或多个实施例中的这些特定构件、结构或特征可依照特定形态而结合。可以理解的是下述附图中并非依照实际比例绘制，而这些附图仅用于配合解说之用。
在此，图1A-图1F为一系列剖面图，显示了于一实施例中的一铜柱凸块工艺内的一半导体装置的一部的制作。
请参照图1A，于一半导体集成电路制作中采用一半导体基板10以用于凸块制作，而集成电路可形成于半导体基板10之内及/或其上。此半导体基板定义为包括半导体材料的任何结构，例如是包括块状硅、半导体晶片、绝缘层上覆硅基板或一硅锗基板，但并不以上述实施情形为限。也可采用如包括III族、IV族、与V族元素的其他半导体材料。半导体基板10可还包括如浅沟槽隔离(STI)构件或局部硅氧化(LOCOS)构件的数个隔离构件(未显示)。这些隔离构件可定义与分隔多个微电子元件(未显示)。可形成于半导体基板10上的这些微电子元件的范例包括晶体管(例如金属氧化物半导体导体晶体管(MOS)、互补型金属氧化物半导体导体晶体管(CMOS)、双极晶体管(BJT))、高压晶体管、高频晶体管、p沟道及/或n沟道场效应晶体管(PFETs或NFETs等)、电阻、二极管、电容、电感、熔丝及其他适当的元件。可施行包括沉积、蚀刻、注入、光刻、回火及其他适当工艺的多个工艺以形成上述多种微电子元件。这些微电子元件经过内部连结以形成如逻辑装置、存储器装置(如静态随机存取存储器，SRAM)、射频(RF)装置、输入/输出装置、芯片上系统装置、上述装置的结合及其他适当形态的装置的一集成电路装置。
半导体基板10可还包括位于集成电路之上的层间介电层与金属化结构。位于金属化结构内的层间介电层包括低介电常数介电材料、未掺杂硅玻璃(USG)、氮化硅、氮氧化硅或其他常用的材料。低介电材料的介电常数(k值)可少于约3.9或少于约2.8。金属化结构内的金属导线可由铜或铜合金所形成。金属化膜层的形成细节为本领域普通技术人员可以理解的。一焊垫区域(未显示)为形成于最顶层的层间介电层内的一顶金属化膜层，其为导电沟道的一部且具有经过如化学机械研磨的一平坦化程序处理的一露出表面，如果需要的话。用于焊垫区域的适当材料可包括如铜、铝、铝铜、铜合金或其他的导电材料，但并以上述材料限制其实施情形。焊垫区域用于连结位于各芯片内的集成电路至外部构件的一接合程序。
半导体基板10还包括形成于焊垫区域之上并露出焊垫区域的一部的一保护层(未显示)，以使得后续铜柱凸块工艺得以施行。此保护层是由择自如未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅、及上述材料的组合的一非有机材料(non-organic material)。或者，保护层可由一聚合物层所形成，例如环氧树脂、聚亚酰胺、苯环丁烯(BCB)、聚苯恶唑(PBO)及相似物，虽然其也可使用其他的相对柔软、更为有机的介电材料。
请参照图1，接着于基板10之上形成包括一第一凸块底金属层14与一第二凸块底金属层16的一凸块底金属层12。举例来说，凸块底金属层12形成于焊垫区域的露出部之上并延伸至保护层的一部上。第一凸块底金属层14，其也称为扩散阻障层或一粘着层，其由钛、钽、氮化钛、氮化钽或相似物所形成，并可借由如物理气相沉积或溅镀法等方法所形成。第一凸块底金属层14沉积至介于约500-2000埃的一厚度，例如为约1000埃的一厚度。形成于第一凸块底金属层14上的第二凸块底金属层16为铜晶种层，其可借由物理气相沉积或溅镀法等方式形成。第二凸块底金属层16可由包括银、铬、镍、锡、金及其组合的铜合金所形成。第二凸块底金属层16沉积至约介于500-10000埃的一厚度，例如为约5000埃的厚度。于一实施例中，凸块底金属层12包括由钛所形成的一第一凸块底金属层14以及由铜所形成的一第二凸块底金属层16。
接着，于凸块底金属层12之上形成一掩模层18，并经过图案化以于其内形成并露出凸块底金属层12的一部的一开口19，以用于铜柱凸块的形成。掩模层18可为一干膜层或一阻剂膜层。开口19接着部分或完全地为具有锡湿润性的一导电材料所填入。于一实施例中，于开口19内形成一铜层20以接触下方的凸块底金属层12。于本发明中，“铜层”的描述泛指大体包括纯元素铜、包含不可避免的杂质的铜层及包括如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆的微量元素的铜合金的一膜层。其形成方法可包括溅镀、印刷、电镀、无电电镀或常用的化学气相沉积方法。举例来说，可施行电化学电镀以形成铜层20。于一实施例中，铜层20的厚度可大于25微米，于下文中铜层20也可称呼为具有一顶面20a与一侧面20b的一铜柱20。于另一实例中，铜层的厚度则大于40微米。举例来说，铜层的厚度约为40-50微米，或约为40-70微米，虽然其厚度可能更厚或更薄。
请参照图1B，接着移除掩模层18，以露出铜柱20的顶面20a与侧面20b以及铜柱20以外的第二凸块底金属层16的一部。当掩模层18为干膜层时，可采用碱性溶液以将其移除。而当掩模层18为阻剂膜层所形成时，则可采用丙酮、N-甲基砒喀烷酮(NMP)、二甲基亚砜(DMSO)、乙氧基乙醇(aminoethoxy ethanol)或相似物以将其移除。接着如图1C所示，第二凸块底金属层16的露出部分经过蚀刻后以露出其下方位于铜凸块20以外的第一凸块底金属层14的一部14a。于一实施例中，移除第二凸块底金属层16的步骤为一干蚀刻或一湿蚀刻。举例来说，可使用采用氨基酸的一各向同性湿蚀刻(通常称其为快速蚀刻由于其处理时间较短)。因此，于铜柱20的下方，经图案化的第二凸块底金属层16”便具有侧面16b。此外，位于铜柱20之外，则露出了第一凸块底金属层14的一部14a。
请参照图1D，借由如一坦覆地沉积的程序以形成一保护层22于如图1C所示结构之上。较精确的说，沉积一保护层22以覆盖铜柱20的底面20a与侧面20b、经图案化的第二凸块底金属层16”的侧面16b以及第一凸块底金属层14的露出部14a。保护层22为一非金属材料层，例如为一介电材料层、一聚合物层，或上述膜层的组合。保护层22可为单一材料层或一多重膜层结构。保护层22的厚度约为500-1000埃。于一实施例中，保护层22为由氮化硅、氧化硅、氮氧化硅、碳化硅、氧化硅与氮化硅的交错膜层或上述材料的结合所形成的一介电材料层，其可借由下述的多个沉积技术中的任一方法所形成，包括热氧化法、低压化学气相沉积(LPCVD)、大气化学气相沉积法(APCVD)或等离子体加强型化学气相沉积(PECVD)。于一实施例中，保护层22为一聚合物材料层且由一聚合物所形成，例如环氧树脂、聚亚酰胺、苯环丁烯(BCB)、聚苯恶唑(PBO)及相似物，虽然其也可使用其他的相对柔软、更为有机的介电材料。聚合物材料层为柔软的，因此具有降低位于基板的各部分的本身应力的功能。此外，聚合物层可轻易地形成约为数十微米的一厚度。
接着，请参照图1E，经过蚀刻保护层22的数个部分后，留下沿着侧面20b与16b与露出部14a的部分，借以形成一侧壁间隔物22a，其也称为一侧壁保护结构22a，其中覆盖铜柱20的顶面20a的保护层22于此步骤中被蚀刻移除。随着光刻与掩模工艺与干蚀刻工艺的演进，如反应性离子蚀刻与其他等离子体蚀刻工艺可完成了侧壁间隔物22a的制作。
接着采用所形成的结构22a作为掩模以蚀刻第一凸块底金属层14并露出下方的基板10。可使用如采用Cl2/BCl3作为蚀刻剂的标准反应离子蚀刻工艺的一干蚀刻工艺，以形成一第一凸块底金属层14。因此，上述干蚀刻工艺图案化了露出部14a的为侧壁间隔物22a所覆盖的一周围表面14a”并露出了侧面14b。由于周围表面14a延伸至经图案化的第二凸块底金属层16”的侧面16b之外，故经图案化的第一凸块底金属层14”的区域可大于经图案化的第二凸块底金属层16”的区域。
所形成的凸块结构24包括了铜柱20、位于铜柱20下方的经图案化的第二凸块底金属层16”、位于经图案化的第二凸块底金属层16”下方的经图案化的第一凸块底金属层14”以及覆盖侧面20b与16b与周围表面14a的侧壁保护结构22a。半导体基板10接着经过切割后，利用锡球或铜凸块而安装于封装基板或另一芯片上的一焊垫上而封装至一封装基板上或另一芯片之上。
图1F为一剖面图，显示了一实施例的一倒装芯片组件的剖面情形。如图1E所示结构经上下颠倒后使其底部粘着至另一基板100。基板100可为一封装基板、电路板(如一印刷电路板)或其他的适当基板。凸块结构24接触了基板100的多个导电粘着点，例如为位于接触焊垫及/或导电线路上的一接合焊锡层102，进而形成耦接了两个基板10与100的一接合结构104。接合焊锡层102可为一共熔焊锡材料，其包括锡、铅、银、铜、镍、铋或其组合的合金。示范性的耦合工艺包括一助熔剂应用、芯片摆置、融化锡球接点的回焊与助熔剂残留物的洁净化。集成电路基板10、接合结构104与另一基板100可称其为一封装组件200，或于本实施例中称其为一倒装芯片封装组件。
本发明提供了一侧壁保护结构，其由位于铜柱侧壁上的一非金属材料以保护铜柱侧壁免于氧化并增加了铜柱侧壁与一后续形成的底胶材料间的附着情形。相较于公知的浸入锡(immersion Sn)方法及接着采用的回火程序，此非金属的侧壁保护结构可调整基板的应力，并避免了于回焊工艺中沿着凸块底金属层的周围的铜柱的焊锡湿润情形。因此其适用于精细间距凸块技术。
图2A-图2D为一系列剖面图，显示了依据另一实施例的一铜柱凸块工艺内的一半导体装置的一部的制作，其中将省略相同或相似如图1A-图1F所示部分的描述。
请参照图2A，于位于铜柱20下方的经图案化的第二凸块底金属层16”形成之后，于所形成结构之上形成一阻障层30。于一实施例中，阻障层30覆盖了铜柱20的底面20a与侧面20b以及经图案化的第二凸块底金属层16”的侧面16b。于其他实施例中，阻障层30覆盖了至少铜柱20的顶面20、铜柱20的侧面20b与经图案化的第二凸块底金属层16”的侧面之一。阻障层30作为一扩散阻障层之用，以避免位于铜柱20内的铜扩散进入如焊锡的接合材料内，接合材料用于接合半导体基板10与外部构件。阻障层30也可称为一保护层、一抗氧化层或一氧化阻挡层，以防止铜柱20的顶面20a与侧面20b免于后续工艺中的氧化。阻障层30可借由选择性的热化学气相沉积法而形成穿透耗尽表面。阻障层30为包括表列于周期表内的III族元素、IV族元素、V族元素或其组合的一含铜材料。于一实施例中，含铜材料层可包括如硼、锗、硅、碳、氮、磷或其组合，但并不以上述材料为限。于部分实施例中，含铜材料层为一CuGeN膜层、一CuGe膜层、一CuSi膜层、一CuSiN膜层、一CuSiGeN膜层、一CuN膜层、一CuP膜层、一CuC膜层、一CuB膜层或上述膜层的组合，其可借由采用含硼、锗、硅、碳、氮、磷或其组合的气体(例如B2H6、CH4、SiH4、GeH4、NH3、PH3)的一选择性化学气相沉积所形成。以形成一CuGeN膜层的一范例为例，于一GeH4的化学气相沉积后施行一去氧化处理步骤(NH3处理)。一阻障层30可成为一扩散阻障层，以防止铜于后续接合程序中进入焊锡内，以使得IMC的形成可受到控制并变得较为薄化与均匀。阻障层30的厚度为薄的，由于其形成方式类似于于扩散工艺。于一实施例中，阻障层30的厚度少于或等于约10纳米。
请参照图2B，接着形成保护层22于阻障层30与第一凸块底金属层14的露出部之上，例如是借由一坦覆沉积所形成。保护层22为非金属的一材料层，例如一介电材料层、一聚合物材料层或上述膜层的组合。保护层22可为单一材料层或一多重膜层结构。于一实施例中，保护层22为一聚合物材料层且由一聚合物所形成，例如环氧树脂、聚亚酰胺、苯环丁烯(BCB)、聚苯恶唑(PBO)及相似物。
接着，请参照图2C，蚀刻保护层22的特定部，以留下沿着侧面20b与16b的部分并形成一侧壁间隔物22a，也可称其为侧壁保护结构22a，其中覆盖铜柱20的顶面的保护层22于本步骤中被移除。于此步骤中，阻障层30仍残留于铜柱20的顶面20a之上。接着采用所形成的结构22a作为掩模而蚀刻第一凸块底金属层14，以露出下方的半导体基板10。所形成的凸块结构32包括了铜柱20、位于铜柱20下方的经图案化的第二凸块底金属层16”、位于经图案化的第二凸块底金属层16”下方且具有延伸至侧面16b以外的周围表面14a的经图案化的第一凸块底金属层14”、覆盖侧面20b与16b以及周围表面14a的侧壁保护结构22a，以及覆盖了侧壁保护结构22a与铜柱20的顶面20a的阻障层30。
请参照图2D，半导体基板10经上下颠倒后使其底部粘着至另一基板100。凸块结构32接触了基板100的多个导电粘着点，例如为位于接触焊垫及/或导电线路上的一接合焊锡层102，进而形成耦接了两个基板10与100的一接合结构104。接合焊锡层102可为一共熔焊锡材料，其包括锡、铅、银、铜、镍、铋或其组合的合金。集成电路基板10、接合结构104与另一基板100可称其为一封装组件200，或于本实施例中称其为一倒装芯片封装组件。
本发明提供了包括铜与锗的一阻障层，其形成于一侧壁保护结构与铜柱侧壁之间，其可更避免铜柱侧壁免于受到氧化并改进介于铜柱侧壁与一后续形成的底胶材料间的附着情形。如此避免了于回焊工艺中沿着凸块底金属层的周围的铜柱的焊锡湿润情形。此阻障层不至于对于片电阻值(Rs)造成太大影响。
图3A-图3F为一系列剖面图，显示了依据另一实施例的一铜柱凸块工艺内的一半导体装置的一部的制作，其中将省略相同或相似如图1A-图1F所示部分的描述。
请参照图3A，于掩模层18的开口19内形成铜层20之后，形成一上盖层40于铜层20的顶面20a之上。上盖层40可作为一阻障层，以防止铜柱内的铜免于扩散进入如焊锡合金的接合材料内，接合材料用于接合基板10与外部构件。铜扩散的防止增加了封装物的可靠度与接合强度。上盖层40可包括镍、锡、锡-铅(SnPb)、金、银、钯、铟、镍钯金(NiPdAu)、镍金(NiAu)、其他相似材料或合金并可借由电镀方法而形成。上盖材料40具有约为1-10微米的一厚度。于部分实施例中，上盖层40为包括了一第一金属膜层42与一第二金属膜层44的一多重膜层结构。第一金属膜层42可包括镍、金、钯、镍基合金、金基合金、或钯基合金。第二金属膜层44可包括镍、金、钯、镍基合金、金基合金、或钯基合金。于一实施例中，第一金属膜层42为一镍层、而第二金属膜层44可为一金层。第一金属膜层42与第二金属膜层44分别具有约为1-5微米的一厚度。
请参照图3B，接着移除掩模层18，并露出上盖层40的顶面40a与侧面40b。如图3C所示，接着蚀刻第二凸块底金属层16的露出部，以露出下方位于铜柱20之外的第一凸块底金属层14。接着，如图3D所示，于得到结构之上形成保护层22，以覆盖上盖层40、铜柱20的侧面20b、经图案化的第二凸块底金属层16”的侧面16b与第一凸块底金属层14的露出部。于施行光刻与掩模技术与干蚀刻工艺之后，以形成一侧壁保护结构22a。因而露出了上盖层40的顶面。接着采用所形成的结构22a作为掩模层以蚀刻第一凸块底金属层14，进而露出下方的基板10。
如图3E，所形成的凸块结构46包括了铜柱20、位于铜柱20的顶面20a上的上盖层40、位于铜柱20的下方经图案化的第二凸块底金属层16”、位于图案化的第二凸块底金属层16”下方且具有延伸至第二凸块底金属层16”的侧面16b以外的周围表面14a的经图案化的第一凸块底金属层14”、以及覆盖侧面40b、20b与16b与周围表面14a”的侧面保护结构22a。半导体基板10接着经过切割后，利用锡球或铜凸块而安装于封装基板或另一芯片上的一焊垫上而封装至一封装基板上或另一芯片之上。
请参照图3F，半导体基板10经上下颠倒后使其底部粘着至另一基板100。凸块结构46接触了基板100的多个导电粘着点，例如为位于接触焊垫及/或导电线路上的一接合焊锡层102，进而形成耦接了两个基板10与100的一接合结构104。集成电路基板10、接合结构104与另一基板100可称其为一封装组件200，或于本实施例中称其为一倒装芯片封装组件。
图4A-图4G为一系列剖面图，显示了依据另一实施例的一铜柱凸块工艺内的一半导体装置的一部的制作，其中将省略相同或相似如图3A-图3F所示部分的描述。
请参照图4A，于掩模层18的开口19内形成铜层20之后，形成上盖层40于铜层20的顶面20a之上，并接着形成一焊锡层50于上盖层40的顶面40a之上。焊锡50可由Sn、SnAg、Sn-Pb、SnAgCu(具有少于0.3％重量百分比的Cu)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等材料，并借由如电镀程序所形成。于一实施例中，焊锡层50为一无铅焊锡层。对于一无铅焊锡系统而言，焊锡层为SnAg，其具有可控制低于3.0重量百分比的Ag含量。举例来说，无铅焊锡层为具有金含量控制至约为2.5重量百分比的SnAg层。
如图4B所示，接着移除掩模层18，并露出焊锡层50的顶面50a与侧面50b。上盖层40的侧面40b也于此步骤中露出。如图4C所示，接着蚀刻第二凸块底金属层16的露出部，以露出下方的铜柱20以外的第一凸块底金属层14。接着，如图4D所示，形成保护层22于得到的结构上，以覆盖焊锡层50、上盖层40、铜柱20的侧面20b、经图案化的第二凸块底金属层16”的侧面16b以及第一凸块底金属层14的露出部。于施行光刻与掩模技术及干蚀刻工艺之后，形成了如图4E所示侧壁保护结构22a。因而露出焊锡层50的顶面50a。第一凸块底金属层14接着蚀刻采用所形成的结构22作为掩模，露出下方基板10。
请参照图4F，针对焊锡层50施行一回焊(reflowing)程序以形成经回焊的焊锡层50”于上盖层40之上。如此形成了一凸块结构52，其包括了铜柱20、位于铜柱20上的上盖层40、位于上盖层40上的经回焊的焊锡层50”、位于铜柱20之下的经图案化的第二凸块底金属层16”、位于经图案化的第二凸块底金属层16”且具有延伸至第二凸块底金属层16”的侧面16b以外的周围表面14a”的经图案化的第一凸块底金属层14”、以及覆盖了侧面40b、20b、16b与周围表面14a”的侧壁保护结构22a。半导体基板10接着经过切割后，利用锡球或铜凸块而安装于封装基板或另一芯片上的一焊垫上而封装至一封装基板上或另一芯片之上。
请参照图4G，半导体基板10经上下颠倒后使其底部粘着至另一基板100。凸块结构52接触了基板100的多个导电粘着点，例如为位于接触焊垫及/或导电线路上的一接合焊锡层102，进而形成耦接了两个基板10与100的一接合结构104。集成电路基板10、接合结构104与另一基板100可称其为一封装组件200，或于本实施例中称其为一倒装芯片封装组件。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种集成电路装置，包括：
一半导体基板；
一第一凸块底金属层，形成于该半导体基板之上；
一第二凸块底金属层，形成于该第一凸块底金属层之上，具有一侧面；
一导电柱，形成于该第二凸块底金属层之上，具有一侧面与一顶面；以及
一保护结构，形成于该导电柱的该侧面与该第二凸块底金属层的该侧面之上；
其中该保护结构由一非金属材料所形成，而该导电柱由一含铜层所形成。
2.如权利要求1所述的集成电路装置，其中该保护结构包括一介电层、一聚合物层、一氮化硅层、一聚亚酰胺层或上述膜层的组合。
3.如权利要求1所述的集成电路装置，其中该第一凸块底金属层包括未为该第二凸块底金属层所覆盖的一周围表面，其中该保护结构形成于该第一凸块底金属层的该周围表面之上。
4.如权利要求1所述的集成电路装置，还包括一阻障层，形成于该导电柱与该保护结构之间，其中该阻障层为包括锗的一含铜材料层，其中该阻障层形成于该导电柱的该顶面之上。
5.如权利要求1所述的集成电路装置，还包括一上盖层，位于该导电柱的该顶面之上，其中该上盖层包括位于该导电柱之上的一镍层与位于该镍层上的一金层，其中该保护结构覆盖了至少该上盖层的该侧面的一部。
6.如权利要求1所述的集成电路装置，其中该第一凸块底金属膜层包括钛，而该第二凸块底金属层包括铜。
7.一种集成电路装置，包括：
一半导体基板；
一凸块结构，形成于该半导体基板之上；以及
一非金属的保护结构，覆盖至少该凸块结构的侧壁的一部；
其中该凸块结构包括形成于该半导体基板之上的一凸块底金属层以及形成于该凸块底金属层之上的一铜柱。
8.如权利要求7所述的集成电路装置，其中该非金属的保护结构包括一氮化硅层、一聚合物层或上述膜层的组合。
9.如权利要求7所述的集成电路装置，还包括一阻障层，形成于该凸块结构与该非金属的保护结构之间，其中该阻障层包括铜与锗。
10.一种封装组件，包括：
一第一基板；
一凸块结构，形成于该第一基板之上，其中该凸块结构包括形成于该第一基板之上的一凸块底金属层以及形成于该凸块底金属层之上的一铜柱；
一非金属的保护结构，覆盖至少该凸块结构的侧壁的一部，其中该非金属的保护结构包括一氮化硅层、一聚合物层或上述膜层的组合；
一第二基板；以及
一接合焊锡层，形成于该第二基板与该凸块结构之间。
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