CN108400097A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN108400097A
CN108400097A CN201710177590.9A CN201710177590A CN108400097A CN 108400097 A CN108400097 A CN 108400097A CN 201710177590 A CN201710177590 A CN 201710177590A CN 108400097 A CN108400097 A CN 108400097A
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convex block
dielectric layer
encapsulating structure
layer
tablet
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CN201710177590.9A
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CN108400097B (zh
Inventor
林柏均
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种封装结构及其制造方法，封装结构包含半导体基板、球下金属层，以及至少一个凸块。球下金属层配置于半导体基板上。凸块配置于球下金属层上，且包含第一部分及位于第一部分下方的第二部分，其中第一部分的上表面包含平坦部分以及圆弧部分。本发明提供了一种形成具有平坦上表面的凸块的方法，使得凸块可容易地连接至其他元件。此外，由于此方法运行于凸块的材料的熔点，使得元件的表现不易受到高温的影响，因此元件的表现也可提升。

Description

封装结构及其制造方法
技术领域
本发明是关于一种封装结构及其制造方法。
背景技术
近年来，覆晶技术(flip-chip)以及球栅阵列(ball grid array techniques)技术已广泛地用于将集成电路连接至内连接基板(如印刷电路板)以及封装基板。覆晶技术将集成电路组件晶片连接至内连接基板或印刷电路板的过程中，多个(如：阵列)锡球(也称为锡凸块)形成于组件(如集成电路晶片)的表面上，将组件上的锡凸块连接至其他组件。两个组件透过加热(如：在熔炉中加热)以回流(reflow)两个组件之间的凸块(如加热凸块，并使凸块冷却)，借此在两组件的端部之间形成电性连接。
然而，回流工艺一般导致高温，并影响组件的表现。因此，为得到较高品质以及稳定性，封装结构及形成方法是需要改良的。
发明内容
本发明的目的在于提供一种可以使得元件的表现不易受到高温的影响，而且元件的表现也可提升的封装结构及其制造方法。
本发明的一实施例为一种形成封装的方法，包含在半导体基板上形成介电层。在介电层中形成开口。在介电层的开口中形成至少一个凸块。移除介电层。对凸块执行压缩工艺。
依据部分实施例，其中执行压缩工艺包含提供平板，并以平板压缩凸块的上表面。
依据部分实施例，其中平板的杨氏模量大于凸块的杨氏模量。
依据部分实施例，其中移除介电层是在对凸块执行压缩工艺之后执行。
依据部分实施例，其中移除介电层是在对凸块执压缩工艺之前执行。
依据部分实施例，此方法还包含连接电子元件至凸块，其中凸块是由导电材料所形成，且此方法是在低于导电材料的熔点的温度下执行。
本发明的另一实施例为一种封装结构，包含半导体基板以及至少一个凸块，凸块配置于半导体基板上，其中凸块包含第一部分以及位于第一部分下方的第二部分，且第一部分的上表面包含平坦部分及圆弧部分。
依据部分实施例，其中第一部分的宽度大于第二部分的宽度。
依据部分实施例，封装结构还包含球下金属层，配置于基板与凸块之间，其中凸块的侧壁与球下金属层的上表面之间的夹角实质上小于90度。
依据部分实施例，其中凸块的侧壁具有倾斜笔直表面。
本发明与现有技术相比，其可以使得元件的表现不易受到高温的影响，而且元件的表现也可以得到提升。
附图说明
阅读以下详细叙述并搭配对应的附图，可了解本发明的多个方面。应注意，根据业界中的标准做法，多个特征并非按比例绘制。事实上，多个特征的尺寸可任意增加或减少以利于讨论的清晰性。
图1A至图1I为本发明的部分实施例的形成封装结构的方法在不同制造阶段的剖面图。
图2A至图2C为本发明的部分实施例的形成封装结构的方法在不同制造阶段的剖面图。
具体实施方式
以下公开提供众多不同的实施例或范例，用于实施本案提供的主要内容的不同特征。下文描述一特定范例的组件及配置以简化本发明。当然，此范例仅为示意性，且并不拟定限制。举例而言，以下描述“第一特征形成在第二特征之上方或之上”，在实施例中可包括第一特征与第二特征直接接触，且也可包括在第一特征与第二特征之间形成额外特征使得第一特征及第二特征无直接接触。此外，本发明可在各范例中重复使用元件符号及/或字母。此重复的目的在于简化及厘清，且其自身并不规定所讨论的各实施例及/或配置之间的关系。
此外，空间相对术语，诸如“下方(beneath)”、“以下(below)”、“下部(lower)”、“上方(above)”、“上部(upper)”等等在本文中用于简化描述，以描述如附图中所图示的一个元件或特征结构与另一元件或特征结构的关系。除了描绘图示的方位外，空间相对术语也包含元件在使用中或操作下的不同方位。此设备可以其他方式定向(旋转90度或处于其他方位上)，而本案中使用的空间相对描述词可相应地进行解释。
图1A至图1I为本发明的部分实施例的形成封装结构的方法在不同制造阶段的剖面图。封装结构10图示于图1A中，其中封装结构10形成于半导体基板12，且半导体基板12内形成有主动元件。
半导体基板12可包含半导体材料，如硅(Si)、锗(Ge)，或硅锗(SiGe)。亦可包含化合物半导体，如碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(galliumphosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)，及/或锑化铟(indium antimonide)；合金半导体，如硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化铟镓(InGaAs)、磷化镓铟(GaInP)，及/或磷砷化铟镓(GaInAsP)，或上述的组合。其他基板中，也可使用多层结构或渐变结构。主动元件，如晶体管、二极管、电容器、电阻器等可形成于半导体基板12内及/或上，并可透过内连接结构连接，例如半导体基板12内的一个或多个介电层中的金属化图案以形成集成电路。
集成电路可为逻辑元件(如中央处理单元、微控制器等)、储存器元件(如动态随机存取储存器(dynamic random access memory；DRAM)或静态随机存取储存器(staticrandom access memory；SRAM)等等)、电源管理元件(如电源管理集成电路(powermanagement integrated circuit；PMIC))、射频(radio frequency；RF)元件、感测(sensor)元件、微机电系统(micro-electro-mechanical-system；MEMS)、信号处理元件(如数位信号处理元件(digital signal processing；DSP))、前端(front-end)工艺元件、相似者，或上述的组合。
连接衬垫14形成于半导体基板12的上表面，以建立与外部电路的电性连接。连接衬垫14的制造过程，举例而言，可在半导体基板12上方形成晶种层(seed layer)。在部分实施例中，晶种层为金属层，可为单层结构或多个不同材料的子层所形成的混合结构。在部分实施例中，晶种层可为钛层以及形成于钛层上方的铜层。晶种层可由，如物理气相沉积(physical vapor deposition；PVD)，或类似的方法形成。接着，形成光阻层并图案化。光阻层可由旋涂(spin on)等方法形成，并可暴露于辐射光以进行图案化。光阻的图案化界定了连接衬垫14的轮廓。图案化工艺在光阻中形成开口以曝露晶种层。经由光阻的开口，将导电材料形成于开口内，并形成于晶种层曝露的部分上方。导电材料可透过电镀，如电极电镀或无电极电镀，或类似的方法形成。导电材料可包含金属，如铜、钛、钨、铝，或相似者。接着，移除光阻以及为被导电材料覆盖的晶种层。光阻可由适合的技术移除，如灰化(ashing)或剥离(stripping)，并可通过如氧电浆或类似者来执行。一旦光阻层移除，晶种层曝露的部分可接着移除，通过蚀刻，如干蚀刻、湿蚀刻等适当的方法移除。晶种层剩余的部分以及导电材料形成连接衬垫14。
参照图1B，在半导体基板12以及连接衬垫14上形成钝化层20。钝化层20经由执行光微影工艺以在钝化层20上形成开口22。连接衬垫14经由开口22曝露，以和接下来所要形成的球下金属层26(图1C)电性连接。钝化层20可由一个或多个绝缘材料形成，如氧化物、氮化物，或有机材料。钝化层20应用于封装结构10上方以提供平坦化以及保护半导体基板12上的电路的用途。
参照图1C，球下金属层26(under bump metallurgy；UBM)接着沉积于钝化层20的上表面以及连接衬垫14的曝露的表面。球下金属层26包括了黏附阻障层30(adhesionbarrier layer)以及润湿层28(wetting layer)。黏附阻障层30可由钛、氮化钛，或是其他金属如铬。润湿层28由铜或镍层形成。球下金属层26用于强化所欲形成的凸块以及连接衬垫14之间的连接。
参照图1D，介电层34沉积于球下金属层26的上表面。在部分实施例中，介电层34由聚合物形成，可为光敏(photo-sensitive)材料，例如聚苯恶唑(Polybenzoxazole；PBO)、聚酰亚胺(polyimide；PI)、苯并环丁烯(Benzocyclobutene；BCB)，或类似者。并可通过光罩图案化。在其他部分实施例中，介电层34由氮化物形成，如氮化硅。也可由氧化物形成，如氧化硅、磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼磷硅玻璃(BPSG)，或相似者。介电层34可由旋涂、贴合(lamination)、化学气相沉积，或类似的方法形成。
图案化介电层34以形成开口38，并曝露球下金属层26的一部分。开口38界定了后续所要形成的凸块的位置。图案化可由适合的方式形成。例如，介电层34若为光敏材料，则可将介电层34曝露至辐射。或者，可对介电层34进行蚀刻，如非等向性蚀刻。
参照图1E，进行电镀工艺(electrodeposition)，将凸块40形成于开口38内，并形成自介电层34的表面凸出的结构。凸块40可为球栅阵列(ball grid array；BGA)连接器、锡球、金属柱、控制塌陷高度晶片连接(controlled collapse chip connection；C4)、微秃块、化学镀镍钯浸金(electroless nickel-electroless palladium-immersion goldtechnique；ENEPIG)所形成的凸块。凸块40可包含金属材料，如铜、铝、金、镍、银、钯、锡、类似者，或上述的组合。在部分实施例中，凸块40由焊锡所形成，并通过蒸镀、电镀、印刷、焊锡转移，或相似方法形成。
大体而言，凸块40具有第一部分40A以及第二部分40B，其中第二部分40B配置于第一部分40A下方，且第一部分40A自介电层34的上表面34S凸出，第二部分40B则是嵌入在介电层34中。更详细而言，由于第一部分40A是凸出自介电层34的上表面34S，第一部分40A会往侧向延伸并形成至介电层34的上表面34S上方。因此，第一部分40A的宽度大于第二部分40B的宽度。
在部分实施例中，介电层34的厚度经过调控。例如，若介电层34为光阻层，则介电层34的厚度范围约为30pm至约40pm，然本发明并不限定于此。介电层34的厚度经控制的理由在于：为了形成高精密节距(pitch)，介电层的厚度必须要够薄以达到高解析度。应了解，在光微影工艺中，光阻层越厚，则解析度会变差。为维持在介电层34上的高精准度，具有合理厚度的介电层34是必须的。而蘑菇(mushroom)结构的凸块40形成于介电层34中。
参照图1F，移除介电层34。在部分实施例中，若介电层34为光敏材料，如光阻等，则介电层34可由灰化、剥离等工艺移除，并通过氧电浆或类似者移除。在部分其他实施例中，介电层34可由蚀刻等适合的工艺移除。
移除介电层34之后，球下金属层26接着进行蚀刻，并以凸块40作为遮罩进行蚀刻。在部分实施例中，蚀刻工艺可为湿蚀刻。因此，位于介电层34(图1E)下方的球下金属层26被移除，而位于凸块40下方的球下金属层26则保留。
参照图1F，凸块40具有第一高度H1，亦称为原始高度。此外，凸块40的第一部分40A具有第一宽度W1，而凸块40的第二部分40B具有第二宽度W2，其中第一宽度W1大于第二宽度W2。换句话说，第一部分40A在半导体基板12上的垂直投影大于第二部分40B在半导体基板12上的垂直投影。
另一方面，第一部分40A的上表面实质上为圆弧形。第二部分40B的侧壁实质上垂直于半导体基板12。相应地，凸块40的第二部分40B的侧壁在剖面视角上为直线。
参照图1G，对封装结构10进行压缩工艺50。详细地，压缩工艺50是对凸块40的上表面执行。压缩工艺50包含提供平板52。平板52可由工具控制，使得平板52可朝着封装结构10移动，并通过提供向下的力量至凸块40，借此重新塑形凸块40的上表面。在部分实施例中，平板52具有平坦表面52S，其中平坦表面52S面向凸块40，并且与凸块40的上表面接触。平坦表面52S通过对凸块40施加向下的力量，使得凸块40形成平坦的上表面。凸块40的上表面与平板52部分接触，借此在凸块40的中央形成平坦部分，而在边缘形成圆弧部分。
应了解平板52的硬度需要大于凸块40的硬度，使得凸块40可根据平板52的轮廓(如平坦表面52S)而进行塑形。在部分实施例中，平板52的杨氏模量(Young’s modulus)大于凸块40的杨氏模量。在部分实施例中，平板52的平坦表面52S与半导体基板12的长度方向平行。
如前述所提及，凸块40可由锡、铜、铝、金、镍、银、钯、锡，或上述的组合所形成。在压缩工艺50中，由于金属的延展性，凸块40会变形，且往侧向延伸。因此，凸块40包含延伸部分40E。延伸部分40E定义为原始凸块40(虚线表示)与变形后的凸块40(实线表示)之间的形状变化。在部分实施例中，延伸部分40E平均地分布在凸块40的两侧。在本实施例中，延伸部分40E位于凸块40的第一部分40A以及第二部分40B上。意即，凸块40的第一部分40A以及第二部分40B在压缩工艺50的期间皆受到挤压而延伸。
应了解，变形后的凸块40(实线)的形状仅用于描述及解释，本发明并不限定于此。变形后的凸块40的形状(或延伸部分40E)的形状可能因为实际情况而有所不同。此外，压缩工艺50的条件，例如凸块的材料、平板的形状，或是下压力道的不同，皆可以用来控制凸块40的轮廓。
图1H中，在压缩工艺50(图1G)之后，最终凸块40完成。在压缩工艺50之后，凸块40具有第二高度H2，其中第二高度H2小于第一高度H1(即图1F中的凸块40的原始高度)。
凸块40的第一部分40A及第二部分40B分别具有第三宽度W3以及第四宽度W4。第三宽度W3大于第四宽度W4。应了解第四宽度W4定义为第二部分40B的平均宽度。此外，由于凸块40的延伸，第三宽度W3大于第一宽度W1(即图1F中的第一部分40A的原始宽度)，而第四宽度W4大于第二宽度W2(即图1F中的第二部分40B的原始宽度)。
另一方面，凸块40的第一部分40A具有上表面42，其中上表面42还包含平坦部分42A以及圆弧部分42B。平坦部分42A是根据平板52的平坦表面52S(图1G所示)所形成的。在部分实施例中，上表面42的平坦部分42A实质上平行于半导体基板12。圆弧部分42B是在压缩工艺50其间并未接触到平板52的一部分，因此圆弧部分42B实质上维持了图1F中凸块40的原始轮廓。在部分实施例中，圆弧部分42B实质上围绕了凸块40的第一部分40A。凸块40的第二部分40B具有侧壁44。在本实施例中，侧壁44与球下金属层26的上表面26S间的夹角θ实质上小于90度。在部分实施例中，侧壁44为倾斜笔直表面。
图1I中，将电子元件60连接至凸块40，已完成封装结构10。由于图1G的压缩工艺50，凸块40的上表面42的平坦部分42A提供了较佳的介面将凸块40连接至电子元件60。此外，整体工艺(将电子元件60连接至凸块40之前及之后)的执行温度低于凸块40的材料的熔点。例如，若凸块40为锡，则整体工艺的温度运行于231.9℃以下。由于半导体基板12内的集成电路以及电子元件60，例如静态随机存取储存器或动态随机存取储存器，容易受到高温工艺的影响，如回流。本发明提供了一种形成具有平坦上表面的凸块的方法，使得凸块可容易地连接至其他元件。此外，由于此方法运行于凸块的材料的熔点，使得元件的表现不易受到高温的影响，因此元件的表现也可提升。
图2A至图2C为本发明的部分实施例的形成封装结构的方法在不同制造阶段的剖面图。图2A至图2C与前一实施例不同之处在于，图2A中，压缩工艺50是在介电层34移除之前进行。
对封装结构10进行压缩工艺50。详细地，压缩工艺50是对凸块40的上表面执行。压缩工艺50包含提供平板52。平板52可由工具控制，使得平板52可朝着封装结构10移动，并通过提供向下的力量至凸块40，借此重新塑形凸块40的上表面。在部分实施例中，平板52具有平坦表面52S，其中平坦表面52S面向凸块40，并且与凸块40的上表面接触。平坦表面52S通过对凸块40施加向下的力量，使得凸块40形成平坦的上表面。凸块40的上表面与平板52部分接触，借此在凸块40的中央形成平坦部分，而在边缘形成圆弧部分。
应了解平板52的硬度需要大于凸块40的硬度，使得凸块40可根据平板52的轮廓(如平坦表面52S)而进行塑形。在部分实施例中，平板52的杨氏模量(Young’s modulus)大于凸块40的杨氏模量。在部分实施例中，平板52的平坦表面52S与半导体基板12的长度方向平行。
如前述所提及，凸块40可由锡、铜、铝、金、镍、银、钯、锡，或上述的组合所形成。在压缩工艺50中，由于金属的延展性，凸块40会变形，且往侧向延伸。因此，凸块40包含延伸部分40E。延伸部分40E定义为原始凸块40(虚线表示)与变形后的凸块40(实线表示)之间的形状变化。在部分实施例中，延伸部分40E平均地分布在凸块40的两侧。在本实施例中，由于凸块40的第二部分40B受到介电层34的限制，故延伸部分40E仅位于凸块40的第一部分40A上。
图2B中，在压缩工艺50(图2A)之后，最终凸块40完成。在压缩工艺50之后，凸块40具有第二高度H2，其中第二高度H2小于第一高度H1(即图1F中的凸块40的原始高度)。
凸块40的第一部分40A及第二部分40B分别具有第三宽度W3以及第四宽度W4。第三宽度W3大于第四宽度W4。此外，由于凸块40的延伸，第三宽度W3大于第一宽度W1(即图1F中的第一部分40A的原始宽度)。然而，由于介电层34的限制，第四宽度W4实质上等于第二宽度W2(即图1F中的第二部分40B的原始宽度)。意即，第二部分40B的宽度在压缩工艺50之后维持不变。此外，由于介电层34的限制，凸块40在压缩工艺50其间具有更稳定的结构。
另一方面，凸块40的第一部分40A具有上表面42，其中上表面42还包含平坦部分42A以及圆弧部分42B。平坦部分42A是根据平板52的平坦表面52S(图1G所示)所形成的。在部分实施例中，上表面42的平坦部分42A实质上平行于半导体基板12。圆弧部分42B是在压缩工艺50其间并未接触到平板52的一部分，因此圆弧部分42B实质上维持了图1F中凸块40的原始轮廓。在部分实施例中，圆弧部分42B实质上围绕了凸块40的第一部分40A。凸块40的第二部分40B具有侧壁44。在本实施例中，侧壁44实质上垂直于半导体基板12，且具有笔直表面。意即，侧壁44与球下金属层26的上表面26S间的夹角θ实质上等于90度。
图2C中，将电子元件60连接至凸块40，已完成封装结构10。由于图2A的压缩工艺50，凸块40的上表面42的平坦部分42A提供了较佳的介面将凸块40连接至电子元件60。此外，整体工艺(将电子元件60连接至凸块40之前及之后)的执行温度低于凸块40的材料的熔点。例如，若凸块40为锡，则整体工艺的温度运行于231.9℃以下。由于半导体基板12内的集成电路以及电子元件60，例如静态随机存取储存器或动态随机存取储存器，容易受到高温工艺的影响，如回流。本发明提供了一种形成具有平坦上表面的凸块的方法，使得凸块可容易地连接至其他元件。此外，由于此方法运行于凸块的材料的熔点，使得元件的表现不易受到高温的影响，因此元件的表现亦可提升。
上文概述了若干实施例的特征，以便本领域的技术人员可更好地理解本发明的方面。本领域的技术人员应当了解到他们可容易地使用本发明作为基础来设计或者修改其他工艺及结构，以实行相同目的及/或实现相同优势的。本领域的技术人员也应当了解到，此类等效构造不脱离本发明的精神及范畴，以及在不脱离本发明的精神及范畴的情况下，其可对本文进行各种改变、取代及变更。

Claims (10)

1.一种形成封装结构的方法，其特征在于，包含：
在基板上形成介电层；
在所述介电层中形成开口；
在所述介电层的所述开口中形成至少一个凸块；
移除所述介电层；以及
对所述凸块执行压缩工艺。
2.如权利要求1所述的方法，其特征在于，执行所述压缩工艺包含：
提供平板；以及
以所述平板压缩所述凸块的上表面。
3.如权利要求2所述的方法，其特征在于，所述平板的杨氏模量大于所述凸块的杨氏模量。
4.如权利要求1所述的方法，其特征在于，移除所述介电层是在对所述凸块执行所述压缩工艺之后执行。
5.如权利要求1所述的方法，其特征在于，移除所述介电层是在对所述凸块执行所述压缩工艺之前执行。
6.如权利要求1所述的方法，其特征在于，还包含：
连接电子元件至所述凸块，其中所述凸块是由导电材料所形成，且所述方法是在低于所述导电材料熔点的温度下执行。
7.一种封装结构，其特征在于，包含：
基板：以及
至少一个凸块，配置于所述基板上，其中所述凸块包含第一部分以及位于所述第一部分下方的第二部分，且所述第一部分的上表面包含平坦部分及圆弧部分。
8.如权利要求7所述的封装结构，其特征在于，所述第一部分的宽度大于所述第二部分的宽度。
9.如权利要求7所述的封装结构，其特征在于，还包含：
球下金属层，配置于所述基板与所述凸块之间，其中所述凸块的侧壁与所述球下金属层的上表面之间的夹角实质上小于90度。
10.如权利要求9所述的封装结构，其特征在于，所述凸块的所述侧壁具有倾斜笔直表面。
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