TW201830634A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201830634A
TW201830634A TW106107633A TW106107633A TW201830634A TW 201830634 A TW201830634 A TW 201830634A TW 106107633 A TW106107633 A TW 106107633A TW 106107633 A TW106107633 A TW 106107633A TW 201830634 A TW201830634 A TW 201830634A
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Taiwan
Prior art keywords
bump
dielectric layer
compression process
width
layer
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TW106107633A
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English (en)
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TWI604588B (zh
Inventor
林柏均
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南亞科技股份有限公司
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Publication of TWI604588B publication Critical patent/TWI604588B/zh
Publication of TW201830634A publication Critical patent/TW201830634A/zh

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Abstract

一種封裝結構，包含半導體基板、球下金屬層，以及至少一凸塊。球下金屬層配置於半導體基板上。凸塊配置於球下金屬層上，且包含第一部分及位於第一部分下方之第二部分，其中第一部分之上表面包含平坦部份以及圓弧部分。

Description

封裝結構及其製造方法
本揭露是關於一種封裝結構及其製造方法。
近年來，覆晶技術(flip-chip)以及球柵陣列(ball grid array techniques)技術已廣泛地用於將積體電路連接至內連接基板(如印刷電路板)以及封裝基板。覆晶技術將積體電路組件晶片連接至內連接基板或印刷電路板的過程中，多個(如：陣列)錫球(亦稱為錫凸塊)形成於組件(如積體電路晶片)的表面上，將組件上的錫凸塊連接至其他組件。兩個組件透過加熱(如：在熔爐中加熱)以回流(reflow)兩個組件之間的凸塊(如加熱凸塊，並使凸塊冷卻)，藉此在兩組件的端部之間形成電性連接。
然而，回流製程一般導致高溫，並影響組件的表現。因此，為得到較高品質以及穩定性，封裝結構及形成方法是需要改良的。
本揭露之一實施例為一種形成封裝的方法，包含形成介電層於半導體基板上。形成開口於介電層中。形成至少 一凸塊於該介電層之該開口中。移除介電層。對凸塊執行壓縮製程。
本揭露之另一實施例為一種封裝結構，包含半導體基板以及至少一凸塊，凸塊配置於半導體基板上，其中凸塊包含第一部分以及位於第一部分下方之第二部分，且第一部分之上表面包含平坦部分及圓弧部分。
10‧‧‧封裝結構
12‧‧‧基板
14‧‧‧連接襯墊
20‧‧‧鈍化層
22‧‧‧開口
26‧‧‧球下金屬層
26S‧‧‧上表面
28‧‧‧潤濕層
30‧‧‧黏附阻障層
34‧‧‧介電層
34S‧‧‧上表面
38‧‧‧開口
40‧‧‧凸塊
40A‧‧‧第一部分
40B‧‧‧第二部分
40E‧‧‧延伸部分
42‧‧‧上表面
42A‧‧‧平坦部分
42B‧‧‧圓弧部分
44‧‧‧側壁
50‧‧‧壓縮製程
52‧‧‧平板
52S‧‧‧表面
60‧‧‧電子元件
H1、H2‧‧‧高度
W1、W2、W3、W4‧‧‧寬度
θ‧‧‧夾角
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個態樣。應注意，根據業界中的標準做法，多個特徵並非按比例繪製。事實上，多個特徵之尺寸可任意增加或減少以利於討論的清晰性。
第1A圖至第1I圖為本揭露之部分實施例之形成封裝結構之方法在不同製造階段的剖面圖。
第2A圖至第2C圖為本揭露之部分實施例之形成封裝結構之方法在不同製造階段的剖面圖。
以下揭露提供眾多不同的實施例或範例，用於實施本案提供的主要內容之不同特徵。下文描述一特定範例之組件及配置以簡化本揭露。當然，此範例僅為示意性，且並不擬定限制。舉例而言，以下描述「第一特徵形成在第二特徵之上方或之上」，於實施例中可包括第一特徵與第二特徵直接接觸，且亦可包括在第一特徵與第二特徵之間形成額外特徵使得 第一特徵及第二特徵無直接接觸。此外，本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的在於簡化及釐清，且其自身並不規定所討論的各實施例及/或配置之間的關係。
此外，空間相對術語，諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等在本文中用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除了描繪圖示之方位外，空間相對術語也包含元件在使用中或操作下之不同方位。此設備可以其他方式定向(旋轉90度或處於其他方位上)，而本案中使用之空間相對描述詞可相應地進行解釋。
第1A圖至第1I圖為本揭露之部分實施例之形成封裝結構之方法在不同製造階段的剖面圖。封裝結構10圖示於第1A圖中，其中封裝結構10形成於半導體基板12，且半導體基板12內形成有主動元件。
半導體基板12可包含半導體材料，如矽(Si)、鍺(Ge)，或矽鍺(SiGe)。亦可包含化合物半導體，如碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)，及/或銻化銦(indium antimonide)；合金半導體，如矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化銦鎵(InGaAs)、磷化鎵銦(GaInP)，及/或磷砷化銦鎵(GaInAsP)，或上述之組合。其他基板中，亦可 使用多層結構或漸變結構。主動元件，如電晶體、二極體、電容器、電阻器等可形成於半導體基板12內及/或上，並可透過內連接結構連接，例如半導體基板12內之一個或多個介電層中的金屬化圖案以形成積體電路。
積體電路可為邏輯元件(如中央處理單元、微控制器等)、記憶體元件(如動態隨機存取記憶體(dynamic random access memory；DRAM)或靜態隨機存取記憶體(static random access memory；SRAM)等等)、電源管理元件(如電源管理積體電路(power management integrated circuit；PMIC))、射頻(radio frequency；RF)元件、感測(sensor)元件、微機電系統(micro-electro-mechanical-system；MEMS)、訊號處理元件(如數位訊號處理元件(digital signal processing；DSP))、前端(front-end)製程元件、相似者，或上述之組合。
連接襯墊14形成於半導體基板12的上表面，以建立與外部電路的電性連接。連接襯墊14的製造過程，舉例而言，可在半導體基板12上方形成晶種層(seed layer)。於部分實施例中，晶種層為金屬層，可為單層結構或多個不同材料的子層所形成的混合結構。於部分實施例中，晶種層可為鈦層以及形成於鈦層上方的銅層。晶種層可由，如物理氣相沉積(physical vapor deposition；PVD)，或類似的方法形成。接著，形成光阻層並圖案化。光阻層可由旋塗(spin on)等方法形成，並可暴露於輻射光以進行圖案化。光阻的圖案化界定了連接襯墊14之輪廓。圖案化製程在光阻中形成開口以曝露晶種 層。經由光阻的開口，將導電材料形成於開口內，並形成於晶種層曝露的部分上方。導電材料可透過電鍍，如電極電鍍或無電極電鍍，或類似的方法形成。導電材料可包含金屬，如銅、鈦、鎢、鋁，或相似者。接著，移除光阻以及為被導電材料覆蓋之晶種層。光阻可由適合的技術移除，如灰化(ashing)或剝離(stripping)，並可藉由如氧電漿或類似者來執行。一旦光阻層移除，晶種層曝露的部分可接著移除，藉由蝕刻，如乾蝕刻、濕蝕刻等適當的方法移除。晶種層剩餘的部分以及導電材料形成連接襯墊14。
參照第1B圖，在半導體基板12以及連接襯墊14上形成鈍化層20。鈍化層20經由執行光微影製程以在鈍化層20上形成開口22。連接襯墊14經由開口22曝露，以和接下來所要形成的球下金屬層26(第1C圖)電性連接。鈍化層20可由一個或多個絕緣材料形成，如氧化物、氮化物，或有機材料。鈍化層20應用於封裝結構10上方以提供平坦化以及保護半導體基板12上之電路的用途。
參照第1C圖，球下金屬層26(under bump metallurgy；UBM)接著沉積於鈍化層20之上表面以及連接襯墊14之曝露的表面。球下金屬層26包括了黏附阻障層30(adhesion barrier layer)以及潤濕層28(wetting layer)。黏附阻障層30可由鈦、氮化鈦，或是其他金屬如鉻。潤濕層28由銅或鎳層形成。球下金屬層26用於強化所欲形成之凸塊以及連接襯墊14之間的連接。
參照第1D圖，介電層34沉積於球下金屬層26之 上表面。於部分實施例中，介電層34由聚合物形成，可為光敏(photo-sensitive)材料，例如聚苯噁唑(Polybenzoxazole；PBO)、聚醯亞胺(polyimide；PI)、苯並環丁烯(Benzocyclobutene；BCB)，或類似者。並可藉由光罩圖案化。於其他部分實施例中，介電層34由氮化物形成，如氮化矽。亦可由氧化物形成，如氧化矽、磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼磷矽玻璃(BPSG)，或相似者。介電層34可由旋塗、貼合(lamination)、化學氣相沉積，或類似的方法形成。
圖案化介電層34以形成開口38，並曝露球下金屬層26的一部分。開口38界定了後續所要形成之凸塊的位置。圖案化可由適合的方式形成。例如，介電層34若為光敏材料，則可將介電層34曝露至輻射。或者，可對介電層34進行蝕刻，如非等向性蝕刻。
參照第1E圖，進行電鍍製程(electrodeposition)，將凸塊40形成於開口38內，並形成自介電層34的表面凸出的結構。凸塊40可為球柵陣列(ball grid array；BGA)連接器、錫球、金屬柱、控制塌陷高度晶片連接(controlled collapse chip connection；C4)、微禿塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)所形成之凸塊。凸塊40可包含金屬材料，如銅、鋁、金、鎳、銀、鈀、錫、類似者，或上述之組合。於部分實施例中，凸塊40由焊錫所形成，並藉由蒸鍍、電鍍、印刷、焊錫轉移，或相似方法形成。
大體而言，凸塊40具有第一部分40A以及第二部分40B，其中第二部分40B配置於第一部分40A下方，且第一部分40A自介電層34的上表面34S凸出，第二部分40B則是嵌入在介電層34中。更詳細而言，由於第一部分40A是凸出自介電層34的上表面34S，第一部分40A會往側向延伸並形成至介電層34的上表面34S上方。因此，第一部分40A的寬度大於第二部分40B的寬度。
於部分實施例中，介電層34的厚度經過調控。例如，若介電層34為光阻層，則介電層34的厚度範圍約為30pm至約40pm，然本揭露並不限定於此。介電層34的厚度經控制的理由在於：為了形成高精密節距(pitch)，介電層的厚度必須要夠薄以達到高解析度。應了解，在光微影製程中，光阻層越厚，則解析度會變差。為維持在介電層34上的高精準度，具有合理厚度之介電層34是必須的。而蘑菇(mushroom)結構的凸塊40形成於介電層34中。
參照第1F圖，移除介電層34。於部分實施例中，若介電層34為光敏材料，如光阻等，則介電層34可由灰化、剝離等製程移除，並藉由氧電漿或類似者移除。於部分其他實施例中，介電層34可由蝕刻等適合的製程移除。
移除介電層34之後，球下金屬層26接著進行蝕刻，並以凸塊40作為遮罩進行蝕刻。於部分實施例中，蝕刻製程可為濕蝕刻。因此，位於介電層34(第1E圖)下方的球下金屬層26被移除，而位於凸塊40下方的球下金屬層26則保留。
參照第1F圖，凸塊40具有第一高度H1，亦稱為 原始高度。此外，凸塊40之第一部分40A具有第一寬度W1，而凸塊40之第二部分40B具有第二寬度W2，其中第一寬度W1大於第二寬度W2。換句話說，第一部分40A在半導體基板12上之垂直投影大於第二部分40B在半導體基板12上之垂直投影。
另一方面，第一部分40A之上表面實質上為圓弧形。第二部分40B之側壁實質上垂直於半導體基板12。相應地，凸塊40之第二部分40B之側壁在剖面視角上為直線。
參照第1G圖，對封裝結構10進行壓縮製程50。詳細地，壓縮製程50是對凸塊40之上表面執行。壓縮製程50包含提供平板52。平板52可由工具控制，使得平板52可朝著封裝結構10移動，並藉由提供向下的力量至凸塊40，藉此重新塑形凸塊40之上表面。於部分實施例中，平板52具有平坦表面52S，其中平坦表面52S面向凸塊40，並且與凸塊40之上表面接觸。平坦表面52S藉由對凸塊40施加向下的力量，使得凸塊40形成平坦的上表面。凸塊40之上表面與平板52部分接觸，藉此在凸塊40的中央形成平坦部分，而在邊緣形成圓弧部分。
應了解平板52的硬度需要大於凸塊40之硬度，使得凸塊40可根據平板52的輪廓(如平坦表面52S)而進行塑形。於部分實施例中，平板52的楊式模數(Young’s modulus)大於凸塊40之楊式模數。於部分實施例中，平板52之平坦表面52S與半導體基板12的長度方向平行。
如前述所提及，凸塊40可由錫、銅、鋁、金、鎳、 銀、鈀、錫，或上述之組合所形成。在壓縮製程50中，由於金屬的延展性，凸塊40會變形，且往側向延伸。因此，凸塊40包含延伸部分40E。延伸部分40E定義為原始凸塊40(虛線表示)與變形後之凸塊40(實線表示)之間的形狀變化。於部分實施例中，延伸部分40E平均地分布在凸塊40之兩側。於本實施例中，延伸部分40E位於凸塊40之第一部分40A以及第二部分40B上。意即，凸塊40之第一部分40A以及第二部分40B在壓縮製程50的期間皆受到擠壓而延伸。
應了解，變形後之凸塊40(實線)的形狀僅用於描述及解釋，本揭露並不限定於此。形後之凸塊40的形狀(或延伸部分40E)的形狀可能因為實際情況而有所不同。此外，壓縮製程50的條件，例如凸塊之材料、平板之形狀，或是下壓力道的不同，皆可以用來控制凸塊40之輪廓。
第1H圖中，在壓縮製程50(第1G圖)之後，最終凸塊40完成。在壓縮製程50之後，凸塊40具有第二高度H2，其中第二高度H2小於第一高度H1(即第1F圖中之凸塊40的原始高度)。
凸塊40之第一部分40A及第二部分40B分別具有第三寬度W3以及第四寬度W4。第三寬度W3大於第四寬度W4。應了解第四寬度W4定義為第二部分40B的平均寬度。此外，由於凸塊40的延伸，第三寬度W3大於第一寬度W1(即第1F圖中之第一部分40A的原始寬度)，而第四寬度W4大於第二寬度W2(即第1F圖中之第二部分40B的原始寬度)。
另一方面，凸塊40的第一部分40A具有上表面 42，其中上表面42更包含平坦部分42A以及圓弧部分42B。平坦部分42A是根據平板52之平坦表面52S(第1G圖所示)所形成的。於部分實施例中，上表面42之平坦部分42A實質上平行於半導體基板12。圓弧部分42B是在壓縮製程50其間並未接觸到平板52的一部分，因此圓弧部分42B實質上維持了第1F圖中凸塊40的原始輪廓。於部分實施例中，圓弧部分42B實質上圍繞了凸塊40的第一部分40A。凸塊40之第二部分40B具有側壁44。於本實施例中，側壁44與球下金屬層26之上表面26S間的夾角θ實質上小於90度。於部分實施例中，側壁44為傾斜筆直表面。
第1I圖中，將電子元件60連接至凸塊40，已完成封裝結構10。由於第1G圖之壓縮製程50，凸塊40之上表面42的平坦部分42A提供了較佳的介面將凸塊40連接至電子元件60。此外，整體製程(將電子元件60連接至凸塊40之前及之後)的執行溫度低於凸塊40之材料的熔點。例如，若凸塊40為錫，則整體製程的溫度運行於231.9℃以下。由於半導體基板12內之積體電路以及電子元件60，例如靜態隨機存取記憶體或動態隨機存取記憶體，容易受到高溫製程的影響，如回流。本揭露提供了一種形成具有平坦上表面之凸塊的方法，使得凸塊可容易地連接至其他元件。此外，由於此方法運行於凸塊之材料的熔點，使得元件的表現不易受到高溫的影響，因此元件的表現亦可提升。
第2A圖至第2C圖為本揭露之部分實施例之形成封裝結構之方法在不同製造階段的剖面圖。第2A圖至第2C圖 與前一實施例不同之處在於，第2A圖中，壓縮製程50是在介電層34移除之前進行。
對封裝結構10進行壓縮製程50。詳細地，壓縮製程50是對凸塊40之上表面執行。壓縮製程50包含提供平板52。平板52可由工具控制，使得平板52可朝著封裝結構10移動，並藉由提供向下的力量至凸塊40，藉此重新塑形凸塊40之上表面。於部分實施例中，平板52具有平坦表面52S，其中平坦表面52S面向凸塊40，並且與凸塊40之上表面接觸。平坦表面52S藉由對凸塊40施加向下的力量，使得凸塊40形成平坦的上表面。凸塊40之上表面與平板52部分接觸，藉此在凸塊40的中央形成平坦部分，而在邊緣形成圓弧部分。
應了解平板52的硬度需要大於凸塊40之硬度，使得凸塊40可根據平板52的輪廓(如平坦表面52S)而進行塑形。於部分實施例中，平板52的楊式模數(Young’s modulus)大於凸塊40之楊式模數。於部分實施例中，平板52之平坦表面52S與半導體基板12的長度方向平行。
如前述所提及，凸塊40可由錫、銅、鋁、金、鎳、銀、鈀、錫，或上述之組合所形成。在壓縮製程50中，由於金屬的延展性，凸塊40會變形，且往側向延伸。因此，凸塊40包含延伸部分40E。延伸部分40E定義為原始凸塊40(虛線表示)與變形後之凸塊40(實線表示)之間的形狀變化。於部分實施例中，延伸部分40E平均地分布在凸塊40之兩側。於本實施例中，由於凸塊40之第二部分40B受到介電層34之限制，故延伸部分40E僅位於凸塊40之第一部分40A上。
第2B圖中，在壓縮製程50(第2A圖)之後，最終凸塊40完成。在壓縮製程50之後，凸塊40具有第二高度H2，其中第二高度H2小於第一高度H1(即第1F圖中之凸塊40的原始高度)。
凸塊40之第一部分40A及第二部分40B分別具有第三寬度W3以及第四寬度W4。第三寬度W3大於第四寬度W4。此外，由於凸塊40的延伸，第三寬度W3大於第一寬度W1(即第1F圖中之第一部分40A的原始寬度)。然而，由於介電層34之限制，第四寬度W4實質上等於第二寬度W2(即第1F圖中之第二部分40B的原始寬度)。意即，第二部分40B的寬度在壓縮製程50之後維持不變。此外，由於介電層34之限制，凸塊40在壓縮製程50其間具有更穩定的結構。
另一方面，凸塊40的第一部分40A具有上表面42，其中上表面42更包含平坦部分42A以及圓弧部分42B。平坦部分42A是根據平板52之平坦表面52S(第1G圖所示)所形成的。於部分實施例中，上表面42之平坦部分42A實質上平行於半導體基板12。圓弧部分42B是在壓縮製程50其間並未接觸到平板52的一部分，因此圓弧部分42B實質上維持了第1F圖中凸塊40的原始輪廓。於部分實施例中，圓弧部分42B實質上圍繞了凸塊40的第一部分40A。凸塊40之第二部分40B具有側壁44。於本實施例中，側壁44實質上垂直於半導體基板12，且具有筆直表面。意即，側壁44與球下金屬層26之上表面26S間的夾角θ實質上等於90度。
第2C圖中，將電子元件60連接至凸塊40，已完成 封裝結構10。由於第2A圖之壓縮製程50，凸塊40之上表面42的平坦部分42A提供了較佳的介面將凸塊40連接至電子元件60。此外，整體製程(將電子元件60連接至凸塊40之前及之後)的執行溫度低於凸塊40之材料的熔點。例如，若凸塊40為錫，則整體製程的溫度運行於231.9℃以下。由於半導體基板12內之積體電路以及電子元件60，例如靜態隨機存取記憶體或動態隨機存取記憶體，容易受到高溫製程的影響，如回流。本揭露提供了一種形成具有平坦上表面之凸塊的方法，使得凸塊可容易地連接至其他元件。此外，由於此方法運行於凸塊之材料的熔點，使得元件的表現不易受到高溫的影響，因此元件的表現亦可提升。
上文概述了若干實施例的特徵，以便本領域熟習此項技藝者可更好地理解本揭示案的態樣。本領域熟習此項技藝者應當瞭解到他們可容易地使用本揭示案作為基礎來設計或者修改其他製程及結構，以實行相同目的及/或實現相同優勢的。本領域熟習此項技藝者亦應當瞭解到，此類等效構造不脫離本揭示案的精神及範疇，以及在不脫離本揭示案的精神及範疇的情況下，其可對本文進行各種改變、取代及變更。

Claims (10)

  1. 一種形成封裝結構的方法，包含：形成一介電層於一基板上；形成一開口於該介電層中；形成至少一凸塊於該介電層之該開口中；移除該介電層；以及對該凸塊執行一壓縮製程。
  2. 如請求項1所述之方法，其中執行該壓縮製程包含：提供一平板；以及以該平板壓縮該凸塊之一上表面。
  3. 如請求項2所述之方法，其中該平板之楊式模數大於該凸塊之楊式模數。
  4. 如請求項1所述之方法，其中移除該介電層是在對該凸塊執行該壓縮製程之後執行。
  5. 如請求項1所述之方法，其中移除該介電層是在對該凸塊執行該壓縮製程之前執行。
  6. 如請求項1所述之方法，更包含：連接一電子元件至該凸塊，其中該凸塊是由一導電材料所形成，且該方法是在低於該導電材料之一熔點的溫度下執 行。
  7. 一種封裝結構，包含：一基板：以及至少一凸塊，配置於該基板上，其中該凸塊包含一第一部分以及位於該第一部分下方之一第二部分，且該第一部分之一上表面包含一平坦部分及一圓弧部分。
  8. 如請求項7所述之封裝結構，其中該第一部分之寬度大於該第二部分之寬度。
  9. 如請求項7所述之封裝結構，更包含：一球下金屬層，配置於該基板與該凸塊之間，其中該凸塊之一側壁與該球下金屬層之一上表面之間的夾角實質上小於90度。
  10. 如請求項9所述之封裝結構，其中該凸塊之該側壁具有傾斜筆直表面。
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