CN101162717A - 堆叠结构及其制造方法 - Google Patents

堆叠结构及其制造方法 Download PDF

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Publication number
CN101162717A
CN101162717A CNA2007100855230A CN200710085523A CN101162717A CN 101162717 A CN101162717 A CN 101162717A CN A2007100855230 A CNA2007100855230 A CN A2007100855230A CN 200710085523 A CN200710085523 A CN 200710085523A CN 101162717 A CN101162717 A CN 101162717A
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China
Prior art keywords
chip
supporting construction
substrate
conductive structure
conductive
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CN101162717B (zh
Inventor
赵智杰
袁从棣
潘信瑜
陈金
彭迈杉
郭祖宽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种堆叠结构，包括：第一芯片，耦接于第一基板，该第一芯片包括穿透该第一芯片的第一导电结构；第二芯片，安装于该第一芯片上，该第二芯片经由该第一导电结构而耦接该第一基板；至少一个第一支撑结构，由形成于该第一基板上的第二基板所制成，该第一支撑结构至少邻近该第一芯片与该第二芯片其中之一，该第一支撑结构的顶面大体与其邻近的该第一芯片与第二芯片其中之一共平面；以及散热片，安装于该第二芯片上。本发明的堆叠结构具有高积集度与高速度的良好效果，改善了电路的操作速率。

Description

堆叠结构及其制造方法
技术领域
本发明涉及半导体结构(semiconductor structures)及其制造方法，特别是涉及一种堆叠结构及其制造方法。
背景技术
随着电子产品的发展，半导体技术已广泛地应用于内存、中央处理器(CPU)、液晶显示器(LCD)、发光二极管(LED)、雷射二极管以及其它装置或芯片组的制作。为了达到高积集度与高速的目标，半导体集成电路的尺寸持续地微缩。为了达到如此积集度与速度的目标，便发展出多种不同的材料与技术，以克服制造上的相关问题。为了达到前述目标，便发展出了包含复合基板(multiple substrates)的堆叠结构，以改善电路的操作速率。
图1显示了公知的堆叠结构的剖面附图。
请参照图1，显示了堆叠结构100，其包括依次设置于基板110上的芯片120、130与140，堆叠结构100还包括凸块(bump)结构105。一般而言，芯片120、130与140具有不同的电路因而具有不同的功能。因此，芯片120、130、140间尺寸可能互不相同。在此，芯片120是通过凸块结构115而耦接于基板110。在芯片120与基板110间则填有底胶117。芯片120则包括穿透其本身的导电结构123。芯片130还包括穿透其本身的导电结构133。芯片120与130则通过位于芯片120与130间的焊垫125而相互耦接。芯片140则包括穿透其本身的导电结构143。芯片140经由焊垫135而耦接于芯片130。
在结合之前，芯片120、130与140需先通过判别故障芯片的电性测试。若芯片120、130与140通过此些电性测试，其便接着安装至基板100上。倘若芯片120、130与140无法通过上述电性测试，芯片120、130与140将被丢弃。芯片120、130与140则分别包括主动区(未显示)，该主动区内含有分别形成于表面121、131与141上的晶体管、二极管与电路等组件。而在这些主动区操作时，将在其表面处产生热能，例如分别在芯片120、130与140上的表面121、131与141上的a、b和/或c等处产生热能。在部分情形中，产生在这些位置处的热能可通过表面122、132和/或142处逸散。若这些热能无法逸散时，即使芯片120、130与140在安装前已分别通过电性测试，此些累积在堆叠结构内的主动区的热能仍将导致芯片120、130与140失效的情形。
此外，在邻近a处所产生的电子信号可通过形成于芯片120的表面121上的金属图案(未显示)以及通过导电结构123、125、133与135而传输至芯片140。上述传输信号的金属图案结构非常复杂。如此复杂结构的金属图案将增加金属图案内相邻金属线路间的寄生电容值。这些寄生电容值将负面地影响堆叠结构的电性表现。
基于前述理由，有需要较为改善的堆叠结构与其制造方法。
发明内容
有鉴于此，本发明提供了一种堆叠结构及其制造方法。
依据一种实施例，本发明提供了一种堆叠结构，包括：
第一芯片，耦接于第一基板，该第一芯片包括穿透该第一芯片的第一导电结构；第二芯片，安装于该第一芯片上，该第二芯片经由该第一导电结构而耦接该第一基板；至少一个第一支撑结构，由形成于该第一基板上的第二基板所制成，该第一支撑结构至少邻近该第一芯片与该第二芯片其中之一，该第一支撑结构的一个顶面大体与其邻近的该第一芯片与第二芯片其中之一共平面；以及散热片，安装于该第二芯片上。
依据又一实施例，本发明提供了一种堆叠结构的制造方法，包括下列步骤：
在第一基板上依次安装第一芯片与第二芯片；在该第一芯片上形成至少一个第一支撑结构，该第一支撑结构邻近至少该第一芯片与该第二芯片其中之一，且具有大体与其邻近的至少该第一芯片与该第二芯片之一共平面的顶面，其中该第一支撑结构的顶面具有不少于该第一与第二芯片的较大者的芯片区20％的区；以及在该第二芯片上安装散热片。
本发明的堆叠结构具有高积集度与高速度的的良好效果，改善了电路的操作速率。
为了让本发明的上述和其它目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合所附的附图，作详细说明如下：
附图说明
图1显示了一种公知堆叠结构的剖面情形；
图2A-2E为一系列剖面示意图，分别显示了依据本发明的多个实施例中的堆叠结构；
图2F为上视示意图，显示了图2A内的芯片区与支撑结构区；
图2G为剖面示意图，显示了形成于基板内的支撑结构；
图3A-3F为一系列剖面示意图，分别显示了依据本发明的多个实施例中具有三芯片的堆叠结构；
图4A与图4B为放大剖面示意图，分别显示了导电结构423的结构；
图5A-5G为一系列剖面示意图，显示了形成如图3F所示的堆叠结构的工艺；
图5H-5L为一系列剖面示意图，分别显示了具有不同芯片尺寸的堆叠芯片结构。
主要元件附图符号说明；
公知部分
100～堆叠结构；105、115～凸块结构；110～基板；120、130、140～芯片；121、131、141、122、132、142～芯片表面；123、133、143～导电结构；125、135～焊垫；a～芯片120上的一处；b～芯片130上的一处；c～芯片140上的一处。
发明部分
200～堆叠结构；205、215～凸块结构；210～基板；217～底胶层；220、230～芯片；221～黏着于凸块结构的芯片220的表面；222～黏着于芯片230的芯片220的表面；223、235～导电结构；225、225a、225b、225c～导电结构；227～隔离层；231～黏着于芯片220的芯片230的表面/切割道区；232～黏着于散热片250的芯片230的表面；235、235a、235b、235c、235d～导电结构；240、240a、240b～支撑结构；245、245a、245b～隔离结构；247～黏着层；250～散热片；260、260a、260b～导电结构；270～基板；
300～堆叠结构；305、315～凸块结构；310～基板；317～底胶层；321～黏着于凸块结构315之芯片320表面；323、325～导电结构；327～隔离层；320、330、370～芯片；331～黏着于芯片320的芯片330的表面；332～黏着于散热片350的芯片330的表面；340、380～支撑结构；345～隔离结构；347～黏着层；350～散热片；363、369～隔离层；365～导电结构；323、335、367、360、390～导电构件；369～隔离结构；371～黏着于芯片330的芯片370的表面；372～黏着于散热片350的芯片370的表面/芯片370的顶面；
411、413～阻障层；419～导电层；420～芯片；421、422～芯片420的表面；423～导电结构；447、449、455～导电层；451～阻障层；457～介电层；
501～基板；505、515～凸块结构；510～芯片区/基板；517～底胶层；523、525～导电结构；527、563～隔离层；530～芯片；535～导电结构；540～隔离结构；527、545～隔离层；547～黏着层；550～散热片；563～隔离层；565a、567a～导电结构；525、535、560、565、567、590～导电结构；563、569～隔离层；570～芯片区/芯片；570a、570b～支撑结构区；540、580～支撑结构/支撑结构区。
具体实施方式
在下文的较佳实施例及相关附图中，如“较低”、“较高”、“水平的”、“垂直的”、“之上”、“之下”、“上”、“下”、“顶”与“底”等描述及其衍生的相关描述用于指出所欲描述的方位与附图中所出现的情形。上述描述是用于说明，而非限定实际装置需要一定按照这样的方位设置。
图2A-2D为一系列剖面附图，分别表示依据不同实施例的堆叠结构。
请参照图2A，在一个实施例中，堆叠结构200包括依次设置于基板210上的芯片220与230，基板210则例如为一印刷电路板(PCB)。在部分实施例中，安装芯片220与230的方法与芯片220与230的结构可参照同属本案让与人的申请中美国专利申请案(申请号为11/563,973，申请日为11/28/2006)，并以提及方式将其内容并入于本文中。
在基板210下方设置有多个凸块结构205。凸块结构205用于机械地与电性地连结基板210与如另一印刷电路板的另一基板(未显示)。在部分实施例中，芯片220通过如球栅数组封装(BGA)程序或打线结合(wire bonding)程序而安装于基板210上。芯片220可通过多个凸块结构215而安装于芯片220上。再者，基板210与芯片220间可填入如环氧树脂的底胶层217，用以绝缘这些凸块结构215并增进如图2A所示结构的机械强度。
芯片220可包括P或N型硅基板、III-V族化合物基板、如液晶显示器、电浆显示器、电激发光显示器的显示基板或发光二极管基板。在部分实施例中，芯片220包括如内存、数字电路、模拟电路、芯片上系统(SOC)、绘图处理单元(GPU)或者包含多种类型的二极管、晶体管与电路的其它类型芯片。芯片220还包括形成并穿透芯片220的至少一个导电结构，例如为导电结构223。导电结构223形成了黏着于凸块结构215的芯片220的表面221以及黏着于芯片230的芯片220的一个对应表面222间的电性连结关系和/或热连结关系。导电结构223将通过下文中图4A-4B及相关描述做一详细描述。芯片220还可包括主动区(未显示)，在主动区内形成有晶体管、装置和/或电路。芯片220的主动区可位于上黏着于凸块结构215的芯片220的表面221上或位于黏着于芯片230的芯片220的表面222上。通过凸块结构215，则可形成位于表面221或表面222上的主动区则可通过电性耦接于通过一导电结构(未显示)，例如形成于基板210之内或之上的金属图案，而电性耦接于凸块结构205。
在部分实施例中，芯片220由分割如晶圆的基板而形成，该基板包括多个相同或相似于芯片220的芯片。在分割程序进行前，将先行基板针对施行电性测试，即施行晶圆可靠度测试(WAT)或其它电性测试，用以判定基板上芯片的可靠度。在完成电性测试后，上述基板接着通过后侧研磨程序以在进行分割之前薄化基板。并在分割程序完成后，通过电性测试的芯片220将安装在基板210上。
芯片230安装于芯片220上并介于隔离结构245间，在此隔离结构245采用斜线图标表示，以如图2A的导电结构235与223的导电结构产生区隔。隔离结构245可包括如环氧树脂或其它适用于作为底胶之用的材料。隔离结构245可为分离区域，或可为延伸并围绕芯片230的连续环状物的一部分。芯片230可通过如金属连结程序、氧化连结程序或黏着连结程序而安装于芯片220上。在部分实施例中，芯片230覆晶安装于芯片220上。在其它实施例中，芯片直接安装于芯片220上而不经过覆晶程序。在芯片220与散热片250间则形成有多个支撑结构240。这些支撑结构240将在下文中详细描述。
在部分实施例中，芯片230的尺寸少于芯片220的尺寸，芯片230至少在如图2A所示的长度(即水平)方向上尺寸少于芯片220的尺寸。芯片230可包括P或N型硅基板、III-V族化合物基板、如液晶显示器、电浆显示器、电激发光显示器的显示基板或发光二极管基板。在部分实施例中，芯片230可包括穿透它的至少一个导电构件，例如导电构件235。导电构件235形成了黏着于散热片250的芯片230的表面232与黏着于芯片220的芯片230的另一表面231间的电性耦接关系和/或热能上耦接关系。在部分实施例中，导电结构235相同或相似于前述的导电结构223。再者，芯片230可包括设置有晶体管、装置和/或电路(匀未显示)的主动区(未显示)。芯片230的主动区则可形成于黏着于散热片250的芯片230的表面232上或黏着于芯片220的芯片230的表面231上。再者，芯片230的主动区则可通过如焊垫或凸块的至少一个导电结构225而耦接于芯片220的主动区。形成于表面231或表面232上的主动区可通过导电结构223与225而耦接于凸块结构215。导电结构225可包括如铝层、铜层、铝铜层、金层、锡铅层或其它导电材料层。在部分实施例中，在芯片220与230间形成有如环氧树脂层的隔离层227，以隔离芯片220与230上的主动区与导电结构225。在部分实施例中，隔离层227与隔离结构245系由相同或不同材料所形成且可以是如分散或涂布程序等相同程序所形成。值得注意的是，当芯片230与支撑结构240间的绝缘或导电结构225间绝缘问题不重要时则可省略隔离层227和/或隔离结构245。
在部分实施例中，导电结构225首先形成于芯片220上，而芯片230的导电结构235则接着与之相黏结。在其它实施例中，导电结构225系形成于芯片230的表面231上，而芯片230的导电结构225则接着相黏于芯片220的导电结构223。而在其它实施例中，当芯片220与230的导电结构为相互黏着时，芯片220与230则分别由导电结构235所分别设置而成的导电结构(未显示)。
在部分实施例中，芯片230系通过分割如晶圆的基板(未显示)所形成，上述基板包括多个相同或相似于芯片230的芯片。形成芯片230的程序则相似于关于芯片220的先前描述。在经过电性测试、晶圆研磨程序与芯片分割程序后，芯片230将可安装于芯片220上。
在如图2A所示的实施例中，支撑结构240形成于芯片220上。支撑结构240邻近或紧贴于芯片230，其扩展至隔离结构245处并具有大体相同于芯片230高度的高度。换句话说，支撑结构240的顶面大体与芯片230的顶面232共平面。在部分实施例中，支撑结构240的顶面的区域占芯片220与230中较大者的芯片区约20％或更多。举例来说，如图2A所示，芯片220大于芯片230，而支撑结构240的顶面区域则占芯片220的芯片区的20％或更多。芯片220的芯片区可以是环绕芯片的切割道(未显示)所定义出的实际区域。在部分实施例中，支撑结构240可由如图2G所示的基板270所形成，例如为硅基底、III-V族化合物基底、印刷电路板、导电基板、塑料基板或其它可形成有导电结构的基板。在基板270内形成支撑结构240后，基板270可经过后侧研磨程序处理并沿着支撑结构240间的凹陷处(未标号)施行切割程序而分割开来。在如图2A所示的实施例中，在支撑结构240内不具有穿透支撑结构240的导电结构。在上述实施例中，当散热片250安装于芯片240上时，支撑结构240位于散热片250与芯片220之间，以形成期望的机械支撑作用。
在部分实施例中，支撑结构240是由分割包括多个结构相同或相似于支撑结构240的基板所形成。包括多个支撑结构240的基板(未显示)在经过切割后可获得具有特定尺寸的组件。在切割基板以得到支撑结构240之前，基板先需经过后侧研磨程序以将其薄化。
在其它实施例中，支撑结构240与芯片230可为形成于相同基板上且通过相同程序所形成的数个区域(例如支撑区域与芯片区域)。在这些实施例中，隔离结构245可为定义形成于基板内支撑结构240与芯片230间的隔离区域(例如为孔隙或空间或空的环状物)所取代。而在如图2F所示的其它实施例中，则可省略这些隔离区。切割道区231环绕支撑结构区240与芯片区230。换句话说，支撑区240即为占据介于切割道区231与芯片区230的区域。在如图2F所示，介于芯片区230与切割道区231间的支撑结构区240具有不少于150微米的宽度“w”。
包括这些支撑结构240与芯片区230的基板在经过电性测试后，接着施行后侧研磨程序与芯片分割程序以得到多个芯片，这些芯片则分别包括对应的支撑结构240与芯片230。芯片接着将安装于芯片220上。
散热片250安装于芯片230上并通过黏着层247而耦接于包含芯片230的区域，黏着层247例如是导热材料层。散热片250则可包括如铝层、铜层、铝铜层或其它导热的膜层。在芯片220与230的主动区(未显示)处所产生的热能，例如分别于芯片220与230的表面221与231处所产生的热能，则可为导电结构223、225、235和/或黏着层247传导至散热片250处并在该处逸散。如前所述，由于支撑结构240系设置于芯片220上且具有大体相同于芯片230高度的高度。因此芯片230与支撑结构240形成了用于安装散热片250的大体平整表面。
在部分实施例中，支撑结构240包括多个依次安装的基板。举例来说，支撑结构240可包括两堆叠基板(未显示)。堆叠基板的总高度大体相同于芯片230的高度以使得堆叠基板的顶面大体与芯片230的顶面232共平面。如果多重支撑结构具有适当的机械支撑、电子传递和/或热逸散等功效，则可采用如此的多重支撑结构240。
图2B则显示了堆叠结构的剖面示意图，其内支撑结构240包括形成并
穿透支撑结构240的至少一个导电结构，例如为导电结构260。在图2A与
图2B中，相同组件采用了相同编号。导电结构260则将详细描述在图4A-4B
等附图及其相关描述中。如图2B所示，在黏着于凸块结构215的芯片220的表面221处产生的热能此时不仅通过导电结构223、225、235以及黏着层247而逸散至散热片250处，其还通过导电结构223、225、260与黏着层247而逸散至散热片250处。此外，在芯片220与230的表面222与231所产生的热能可不仅通过导电构件235与黏着层247而传导至散热片250处，其还可通过导电构件260与黏着层247而传导至散热片250处。因此，设置于散热片250与芯片220间的支撑结构240除了在安装散热片250时具有适当的机械支撑效用，其还在芯片220与散热片250间形成适当的散热通道。
图2C显示了一种实施例的剖面示意图，其中芯片220(由隔离区245所定义出的区域)小于芯片230。在图2A与图2C中，相同的组件采用相同标号。图2C中所示的导电结构223a-c、225a-c以及235a-c相似于如图2A所示的导电结构223、225与235。在实施例中，导电结构显示为223a-c、225a-c以及235a-c。在图2C中，支撑结构240设置在基板210上。支撑结构240位于基底210与芯片230之间，以在安装芯片230和/或散热片250时提供适当之机械支撑效用。
图2D则为另一实施例的剖面示意图，其中芯片220小于芯片230。在图2B、2C与2D中，相同组件采用相同标号。导电结构在此显示为223a-c、225a-d以及235a-d。在图2D中，安装于基板210与芯片230间的支撑结构240不仅在安装芯片230和/或散热片250时提供期望的机械支撑效用，其还形成了热逸散通道，因此产生黏着于凸块215的芯片220的表面221处的热能可逸散至散热片250处。
再者，形成穿透支撑结构240的导电结构260还在芯片230与基底210间形成了电性传输。举例来说，芯片230的主动区(未显示)形成于芯片230的表面231上。电子信号(例如产生于接近导电结构235a处的芯片的表面231处的电流)可经过形成于主动区内的金属图案(未显示)而传输至如图2C所示的导电结构225a处。上述电子信号可接着通过导电结构225a与223a传输至凸块结构215与基板210处。如此，由于形成于如图2C所示的芯片230的主动区内的金属图案结构极为复杂。通过形成如图2D所示的支撑结构240，产生于接近于导电结构235a的芯片230的表面231的信号可通过导电结构225d与260而传输至导电凸块215。因此，可较为简化如图2D所示的形成于芯片230的主动区的金属图案(未显示)的绕线情形。因而可有效地降低产生于主动区内的寄生电容。
如图2E所示的其它实施例中，则依次在基板210上形成两支撑结构240a与240b，这些支撑结构240a与240b分别相同于前述的支撑结构240并分别邻近或仅靠芯片220与230，以提供适当的机械支撑、热逸散和/或电子传输功能。由于支撑结构240a与240b形成于两个芯片膜层中，而非仅环绕顶部芯片230(请参照图2A)或仅环绕底部芯片(请参照图2C)。在此，导电结构260a与260b则可相似或相同于导电结构260。隔离层245a与245b则可相同或相似于隔离层245。如图2E所示，堆叠结构至少在长度上较芯片220与230之一大。图2E还显示了上述芯片之一或全部还扩展朝向至少堆叠结构的一边。在本实施例中，位于顶部的芯片230向堆叠结构的右侧扩展，但结束于其隔离结构245b之左侧。虽然堆叠结构包括延伸超过芯片220与230的尺寸，只要具有适当的机械支撑、热逸散和/或电子传输等功能，这样的堆叠结构仍是可行的。
图3A-3F则是一系列剖面示意图，显示了依据其它实施例的具有三芯片的堆叠结构。在图3A-3F中，相同于图2A中组件的将采用图2A内标号加上100表示。
如图3A所示，芯片370安装于位于隔离结构369间的芯片330上，在图3A中隔离结构369则标示为斜线图示。芯片370可通过如金属连结程序、氧化连结程序或黏着物连结程序而安装于芯片330上。在部分实施例中，芯片370覆晶安装于芯片330上。在其它实施例中，芯片370则直接地安装在芯片330上而未经过覆晶程序。
在部分实施例中，芯片370的尺寸至少在如图3A所示的水平方向上小于芯片330的尺寸。芯片370可包括P或N型硅基底、III-V族化合物基板、如液晶显示器、电浆显示器、电激发光荧光显示器的显示基板或发光二极管基板。在部分实施例中，芯片370可包括穿透它的至少一个导电构件，例如导电构件367。导电构件367形成了黏着于散热片350的芯片370的表面372与黏着于芯片330的芯片370的另一表面371间的电性耦接情形和/或热能耦接情形。在部分实施例中，导电结构367相同或相似于如前所述的导电结构323或335。再者，芯片370可包括设置有晶体管、装置和/或电路的主动区(未显示)。芯片370的主动区可形成于黏着于散热片350的芯片370的表面372上或黏着于芯片330的芯片370的表面371上。再者，芯片370的主动区可通过如焊垫或凸块的至少一个导电结构365而耦接于芯片330的主动区。芯片370的主动区亦通过导电结构365、335、325、323和/或凸块结构315而耦接于芯片320的主动区与基板310。导电结构367可包括如铝层、铜层、铝铜层、金层、锡铅层或其它导电材料层。在部分实施例中，在芯片330与370间形成有如环氧树脂层的隔离层363，用以隔离芯片330与370的主动区以和导电结构365。在部分实施例中，隔离层363以及369由相同或不同材料所形成，且可通过如分散或涂布程序的同一程序例所形成。在部分实施例中，形成芯片370的分割方法相同或相似于相关于图2A的描述中的分割形成芯片220的方法。经过电性测试后与后侧研磨以及芯片切割后，芯片370可安装在芯片330上。
在芯片330和/或支撑结构340上可形成如支撑结构380的另一支撑结构。支撑结构380可形成于邻近芯片370处，并具有大体相同于芯片370高度的高度。换句话说，支撑结构380的顶面大体与芯片370的顶面372共平面。在部分实施例中，支撑结构380顶面的区域约占芯片320、330与370中较大者之一的区域的20％或更多。举例来说，如图3A所示，芯片320较芯片330与370为大，而支撑结构380的顶面约占芯片320区域的20％或更多。在部分实施例中，支撑结构380可包括硅基底、III-V族化合物基板、印刷电路板、导电基板、塑料基板、或可形成有导电结构在其内的其它基板。在如图3A所示的实施例中，并无导电结构形成通过支撑结构340与380。在此些实施例中，支撑结构340与380位于散热片350与芯片320之间，以安装散热片350于芯片370上时形成期望的机械支撑。支撑结构380可按照前述的形成支撑结构240的方式而形成。在部分实施例中，芯片370与支撑结构380可由按照前述方式而由同一基板所形成。
图3B显示了三芯片堆叠结构的剖面示意图，其内的支撑结构340与380中包括至少一导电结构，例如为分别形成穿透支撑结构340与380的导电结构360与390。在此，在图3A与3B中相同组件采用相同标号。如图3B所示，黏着于凸块结构315的芯片320表面321上产生的热不仅通过导电结构323、325、335、365、367以及黏着层347逸散至散热片350处且经由导电构件323、325、360、365、390以及黏着层347而逸散至散热片350处。再者，产生于芯片320与330的表面322与331上的热可不仅通过导电结构335、365、367以及黏着层347而传导至散热片350且亦通过导电结构335、365、390以及黏着层347而传导至散热片350处。这样，形成于散热片350与芯片320间的支撑结构340与380不仅于安装散热片时形成了机械上的支撑，且形成了其间的热逸散通道。
在部分实施例中，支撑结构340或380之一中具有导电结构360或390。举例来说，支撑结构380包括形成并穿透的导电结构390，而支撑结构340则不包括形成并穿透的导电结构360。对于该实施例而言，支撑结构380作为热逸散的通道和/或机械支撑。不具有形成并穿透的导电结构360的支撑结构340则在安装散热片350时作为机械支撑之用。熟悉本领域的技术人员可适度修正支撑结构340与380，以于安装散热片350时得到期望的热逸散及机械支撑效用。
在部分实施例中，芯片370的尺寸大体相似于芯片320的尺寸。在此些实施例中，支撑结构380以及隔离层369则可省略。再者，除了热逸散效用之外，参照先前图2C-2D及相关描述，导电结构325、360、365和/或390还可作为用于信号传递之用。在其它实施例中，可在基板310上邻近于芯片320处还形成具有或不具有导电结构形成穿透额外支撑结构。在这些实施例中，分别具有支撑结构380的芯片320、330与370形成并相邻。相同于图2E的堆叠结构200及其相关描述，虽然堆叠结构300的水平尺寸大于各别芯片320、330和/或370的水平尺寸，其仍可达到期望之机械支撑、热逸散和/或信号传递功效。
图3C为显示了一种实施例的示意剖面图，其中芯片330大于芯片320与370。在图3A与图3C中，相同组件采用相同标号。如图3C所示，支撑结构340与380可分别形成于基板310与芯片330之间以及于散热片350与芯片330之间。支撑结构340形成于芯片320上，以在安装芯片330、370和/或散热片350时形成适当的机械支撑作用。支撑结构380则形成于芯片330上，以在安装散热片350时形成期望的机械支撑作用。
图3D为另一实施例的剖面示意图，其中芯片330大于芯片320与370，而支撑结构340与380包括分别形成并穿透它的导电结构360与390。在图3B与图3D中，相同组件采用相同标号。在图3D中，支撑结构340与380分别安装在基板310与330之间以及散热片350与芯片330之间，其不仅在安装芯片330、370和/或散热片350形成了期望的机械支撑作用，其还通过导电结构325、335、360、365和/或390而提供了散热用和/或信号传输用的信道。
图3E则显示了另一实施例的剖面示意图，其中芯片370大于芯片320与330，而支撑结构340与380分别包括形成并穿透的导电结构360与390。在图3A与图3E中，相同组件采用了相同标号。在图3E中，支撑结构340与380分别形成于基板310与芯片330之间以及在芯片320与370之间。支撑结构340安装在基板310上以在安装芯片330、370和/或散热片350时形成适当的机械支撑作用。支撑结构380系安装于芯片320上以在安装芯片370和/或散热片350时形成机械支撑作用。
图3F为依据又一实施例的剖面示意图，其中芯片370系大于芯片320与330。在图3A与图3F中，相同组件采用了相同标号。在图3F中，支撑结构340与380分别形成于基板310与芯片330之间以及芯片320与370间之间，这些支撑结构不仅在安装芯片330、370和/或散热片350时形成适当的机械支撑作用，其还通过导电结构325、360、365、367和/或390而形成了热逸散和/或信号传递的信道。
图4A与图4B为导电结构的放大剖面图，这些导电结构可用于如图2A-2E与图3A-3F中所示的导电结构223、235、323、325。
如图4A所示，导电结构423包括介电层457、阻障层411、413以及形成并穿透芯片420的导电层419。导电结构423的一端通过形成于芯片420的表面421或422上之一金属图案(未显示)而耦接于一主动区(未显示)。导电结构423可包括如一介层结构、接触结构、沟槽结构、镶嵌结构、双镶嵌结构、多重膜层内连结构或适用于形成穿过芯片的导电通路的其它结构。
介电层457可为氧化物层、氮化物层、氮氧化物层或适用于绝缘导电层419与芯片420的其它部分的其它介电膜层。介电层457可通过如化学气相沉积法的方法所形成。阻障层411与413可包括如钛层、氮化钛层、氮化钽层、钽层或其它适于降低或避免导电层419的离子扩散进入芯片420的环绕区域中的材料层。阻障层411、413可通过如化学气相沉积或物理气相沉积的程序所形成。导电层419可包括铝层、铜层、铝铜层、多晶硅层或其它导电材料层。导电层419可通过化学气相沉积、物理气相沉积、电化学电镀、无电电镀的程序或其它适用于形成导电层的程序所形成。
图4B则显示导电结构423的另一实施例的剖面示意图。如图4B所示，导电结构423还包括多重膜层结构，其包括导电层447、449、455以及阻障层451。导电层447、449、455与阻障层451形成于介电层457中。介电层457可包括如氧化物层、氮化物层、氮氧化物层、低介电常数材料层或其它适用于绝缘多重膜层结构中的导电构件的介电材料层。导电膜层447与455可包括如铝层、铜层、铝铜层或其它含金属的膜层。导电层447与455可通过如化学气相沉积、物理气相沉积、电化学电镀、无电电镀等程序或类似程序所形成。阻障层451可包括如钛层、氮化钛层、钽层、氮化钽层及其它适用于避免或降低导电层449的金属离子扩散进入介电层457的材料层。导电层449可包括铝层、铜层、铝铜层、多晶硅层或其它导电材料层。在部分实施例中，此多重膜层结构为形成于芯片420的主动区上的一部分，且可通过于芯片420形成的主动区的工艺所形成。
在部分实施例中，当图4A与图4B的导电结构423应用分别显示在图2B、2D、2E、3B、3D与3F中的导电结构260、360与390时，当导电层419的绝缘和/或芯片420内的金属离子情形并不重要时，可省略导电结构423内的介电层457和/或阻障层413等结构。提供机械支撑、热逸散和/或信号传输等作用的支撑结构可能不包括其内装置或形成晶体管的主动区，但该支撑结构可能包括形成于其上且用于信号传输的金属图案。由于该金属图案较形成于主动区内的装置或晶体管为不敏感，故导电结构419的金属离子扩散情形将不会负面地影响金属图案的电性特性，进而允许了省略导电结构260中的导电层457与阻障层412的情形。
图5A-5G则显示了形成如图3F所示的堆叠芯片结构的实施例。在图5A-5G中，相同于图3F内的组件将采用图3F内的标号并加上200。
如图5A所示，芯片区570形成于基板501上。基板501可为P或N型硅基板、III-V族化合物基板、如液晶显示器、电浆显示器、电激发光显示器的显示基板或发光二极管基板。在这些实施例中，主动区形成于基板501的表面502上并对应于芯片区570。导电结构567则形成并穿透芯片区570。
芯片530安装于基板501上，其对应于芯片区570并通过导电结构565而耦接芯片区510。芯片530可包括形成并穿透芯片530的导电结构535。芯片530可通过金属连结程序、氧化连结程序或黏着物连结程序等程序而安装于芯片区570上。
如图5B所示，在基板501上形成有支撑结构580，支撑结构580包括形成并穿透的导电结构590且支撑结构580通过如金属连结程序、氧化连结程序或黏着物连结程序等程序而连结于基板501。在部分实施例中，支撑结构580通过如环氧树脂层的隔离层569与563与芯片530相隔离。隔离层560亦可形成于芯片530与芯片区570之间。在部分实施例中，导电结构590通过如为凸块或焊垫的导电结构565而耦接于导电结构567。
在部分实施例中，芯片530与支撑结构580形成于相同的基板内。举例来说，基板(未显示)包括相邻的预先定义芯片区(用于形成芯片530)与预先定义支撑结构区(用于形成支撑结构580)。预先定义芯片区与预先定义支撑结构区由一既定空间所分隔，在此既定空间内不具有主动区、晶体管、二极管、电路和/或导电结构。主动区与导电结构535形成于预先定义芯片区内，而导电结构590则形成于预先定义支撑结构区内。在预先定义芯片区与预先定义支撑结构区分别形成主动区与导电结构535与590位后，基板则经由电性测试以检测无效芯片。在电性测试后，基板经过研磨程序与芯片分割程序处理后，进而将基板分割成为多个芯片，每一芯片中包括芯片区530以及支撑结构区580。在部分实施例中，芯片具有大体相似于芯片区570的长度与宽度。在这些实施例中，隔离层569则忽略并为前述的既定空间所取代，而隔离层563则设置于芯片530与支撑结构580之间。
如图5C所示，芯片520分别安装于各芯片530上。芯片520可包括导电结构523且可通过导电结构525耦接芯片530。芯片530的安装可通过前述安装芯片520的方法所达到。
如图5D所示，支撑结构540形成于芯片530和/或支撑结构580上，支撑结构540内包括形成并穿透的导电结构560，支撑结构540通过如金属连结程序、氧化连结程序、黏着物连结程序等程序所安装。在部分实施例中，支撑结构540与芯片520之间为如环氧树脂层的隔离层545与527所分隔。隔离层527亦可设置于芯片530与520之间作为隔离导电结构525之用。在部分实施例中，导电结构560通过如凸块或焊垫的导电结构525而耦接导电结构590。在其它实施例中，芯片520与支撑结构540可如前述的芯片530与支撑结构580的相关描述而形成于同一基板内。
在其它实施例中，在研磨包括前述预先定义芯片区(用于形成芯片530或520)以及预先定义支撑结构区(用于形成支撑结构580或540)的基板后，整个经研磨的基板将依次安装于基板501上。接着将此安装基板经过下文的切割程序处理。
如图5E所示，在芯片520与支撑结构540上通过如球栅数组封装程序的程序形成多个凸块结构515。这些凸块结构515用于电性连结堆叠芯片与如图5F所示的基板510。
在形成凸块结构515之后，基板501接着经过研磨程序研磨，而经过研磨的基板接着沿着隔离层527与563施行芯片切割程序，进而将该经研磨结构分割成为多个堆叠芯片结构。接着颠倒放置堆叠芯片结构并通过如图5F所示的BGA程序将它安装于包括多个凸块结构505形成于其下的基板510上。接着在芯片520与基板510之间填入底胶层517，以电性隔离这些凸块结构515并提供机械支撑与避免膜层剥落的情形。
请参照图5G，接着在芯片570上安装一散热片550，并在散热片550与芯片570间设置一黏着层547。如前所述，安装在基板510与芯片570间的支撑结构540与580形成了芯片520、530、570与基板510之间的热逸散信道和/或信号传递信道。
图5H-5L为一系列剖面示意图，分别显示了具有不同芯片尺寸的堆叠结构。在图5H-5L等中，与图5E中的相同组件采用相同标号。
如图5H所示，芯片520与570具有大体相同的长度(水平)尺寸，因此支撑结构580仅安装于邻近或紧靠芯片530之处。
如图5I所示，芯片520具有至少在长度或水平方向上大于芯片530与570在该方向上尺寸的尺寸。在图5I中，支撑结构区570a设置于邻近芯片区570处。支撑结构区570a与芯片区570之间被一预先定义空间570b所分隔，其绘制成斜线标示。支撑结构区570a作为相同在前述的支撑结构540与580的功能。在部分实施例中，支撑结构区570a包括至少一个导电结构567a。再者，导电结构567a可通过导电结构565a而耦接穿透芯片530的导电结构535。
图5J显示了堆叠结构的示意剖面图，其包括邻近于各芯片520、530与570的支撑结构。这些堆叠芯片结构具有至少在其剖面情形中大于芯片520、530与570尺寸的尺寸。
如图5K所示，由于芯片区570至少在水平方向上的尺寸小于芯片530与540之一的尺寸，故支撑结构570a仅形成于芯片区570中，以形成前述结构。在图5L中，芯片530则具有大于芯片540与570长度尺寸之一长度尺寸。通过这些形成并穿透芯片520、530与570以及支撑结构540、570a以及580的导电构件的形成，便可达到期望的机械支撑、热逸散和/或电性传输等功能。
虽然本发明已以较佳实施例揭示如上，然而其并非用于限定本发明，任何熟悉本领域的技术人员，在不脱离本发明的精神和范围内，可作各种的更动与润饰，因此本发明的保护范围应以所附的权利要求书所界定的为准。

Claims (15)

1.一种堆叠结构，包括：
第一芯片，耦接于第一基板，该第一芯片包括穿透该第一芯片的第一导电结构；
第二芯片，安装于该第一芯片上，该第二芯片经由该第一导电结构而耦接该第一基板；
至少一个第一支撑结构，由形成于该第一基板上的第二基板所制成，该第一支撑结构至少邻近该第一芯片与该第二芯片其中之一，该第一支撑结构的一个顶面大体与其邻近的该第一芯片与第二芯片其中之一共平面；以及
散热片，安装于该第二芯片上。
2.如权利要求1所述的堆叠结构，其中该第一支撑结构包括穿透该第一支撑结构的至少一个第二导电结构，而该第一支撑结构则经由该第二导电结构而耦接该散热片。
3.如权利要求1所述的堆叠结构，还包括第三芯片，耦接于该第二芯片与该散热片之间。
4.如权利要求3所述的堆叠结构，还包括第二支撑结构，设置于该第二芯片与该散热片之间。
5.如权利要求4所述的堆叠结构，其中该第二支撑结构包括穿透该第二支撑结构的至少一个第二导电构件，而该第二支撑结构通过该第二导电结构而耦接该散热片。
6.一种堆叠结构，包括：
第一芯片，耦接于第一基板，该第一芯片包括穿透该第一芯片的第一导电结构；
第二芯片，安装于该第一芯片上，该第二芯片经由该第一导电结构而耦接该第一基板，其中该第二芯片包括环绕芯片区的切割道区以及邻近该切割道区的至少一个支撑结构区，而该支撑结构区位于该芯片区与该切割道区之间；以及
散热片，安装于该第二芯片上。
7.如权利要求6所述的堆叠结构，其中该支撑结构包括穿透该支撑结构区的至少一个第二导电结构，而该支撑结构区域则经由该第二导电结构而耦接该散热片。
8.如权利要求6所述的堆叠结构，还包括至少一个隔离区，位于该芯片区与该支撑结构区之间。
9.一种堆叠结构的制造方法，包括下列步骤：
在第一基板上依次安装第一芯片与第二芯片；
在该第一芯片上形成至少一个第一支撑结构，该第一支撑结构邻近至少该第一芯片与该第二芯片其中之一，且具有大体与其邻近的至少该第一芯片与该第二芯片之一共平面的顶面，其中该第一支撑结构的顶面具有不少于该第一与第二芯片的较大者的芯片区20％的区；以及
在该第二芯片上安装散热片。
10.如权利要求9所述的堆叠结构的制造方法，其中该第一支撑结构包括第二基板。
11.如权利要求10所述的堆叠结构的制造方法，还包括形成穿透该第二基板的至少一个第二导电结构的步骤，其中该第一基板通过该第二导电结构而耦接该散热片。
12.如权利要求9所述的堆叠结构的制造方法，还包括在该第二芯片与该散热片间安装第三芯片的步骤。
13.如权利要求12所述的堆叠结构的制造方法，还包括在该第二芯片与该散热片间形成第二支撑结构的步骤。
14.如权利要求13所述的堆叠结构的制造方法，其中该第二支撑结构包括第二基板。
15.如权利要求14所述的堆叠结构的制造方法，还包括形成穿透该第二基板的至少一个第二导电结构的步骤，其中该第一基板通过该第二导电构件而耦接该散热片。
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