CN206742228U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN206742228U
CN206742228U CN201720305810.7U CN201720305810U CN206742228U CN 206742228 U CN206742228 U CN 206742228U CN 201720305810 U CN201720305810 U CN 201720305810U CN 206742228 U CN206742228 U CN 206742228U
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Prior art keywords
semiconductor element
conductive layer
semiconductor
substrate
semiconductor devices
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CN201720305810.7U
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Inventor
F·J·卡尔尼
J·W·霍尔
M·J·塞登
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本实用新型涉及一种半导体器件。本实用新型的一方面的目的是提供一种节省成本的半导体器件。半导体器件包括：第一衬底；第二衬底；在所述第一衬底上方形成的第一导电层；在所述第二衬底上方形成的第二导电层，其中所述第二衬底邻近所述第一衬底设置；以及跨所述第一衬底的所述第一导电层和所述第二衬底的所述第二导电层而形成的互连件。本实用新型的一方面的技术效果是所提供的半导体器件是节省成本的。

Description

半导体器件
本申请是申请日为2016年9月14日、申请号为201621057355.5、实用新型名称为“半导体器件”的实用新型申请的分案申请。
要求本国优先权
本申请要求由Francis J.CARNEY和Michael J.SEDDON发明的、提交于2015年9月17日的名称为“SEMICONDUCTOR PACKAGES AND METHODS”(半导体封装件及制造方法)的美国临时申请No.62/219,666的权益，该临时申请以引用方式并入本文，并且据此要求该申请的共同主题的优先权。
技术领域
本实用新型总体涉及半导体器件，更具体地讲涉及半导体器件和形成微互连结构的方法。
背景技术
半导体器件在现代电子产品中很常见。电子部件中半导体器件的数量和密度各不相同。半导体器件可执行多种多样的功能，诸如模数信号处理、传感器、电磁信号的发送和接收、电子器件控制、功率管理以及音频/视频信号处理。分立半导体器件通常包含一种类型的电子部件，例如，发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、二极管、整流器、晶闸管以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百至数百万的电子部件。集成半导体器件的例子包括微控制器、专用集成电路(ASIC)、标准逻辑、放大器、时钟管理、存储器、接口电路以及各种信号处理电路。
半导体器件的重要部分是半导体管芯之间的互连结构所需的区域。图1示出了已知的管芯间互连构造，其中半导体管芯50与半导体管芯52相邻(但隔开)设置。焊丝54在半导体管芯50的有源表面58上的接触垫56和半导体管芯52的有源表面62上的接触垫60之间提供电互连。要使焊丝54形成和成形，需要半导体管芯50和52之间隔开距离D1，还需要隔开专门的边缘间距D2。另外，半导体管芯通常预留专门的边缘空间，该专门的边缘空间在进行锯片改造时用作划道栅格，在划片街区(saw street)的裂痕扩散时用作裂痕止沟，或者在划片街区开裂时用于密封管芯边缘，最终防止水分进入有源区附近。管芯边缘空间的要求仍然不清楚。人们希望减小电互连所需的专门的边缘间距，以便尽量增大有源管芯区域，从而为给定半导体封装件提供信号处理功能，同时减小半导体封装件的总体占用面积。
本领域已经使用管芯堆叠技术来尽量减小半导体封装件占用面积，管芯堆叠对低功率技术(例如，存储器器件)有用。然而，热耗散和应力过度是堆叠管芯存在的问题，尤其是对于功率MOSFET和集成驱动器。管芯间互连的另一常见方法是使用硅通孔(TSV)，但硅通孔的制造成本极高。
实用新型内容
本实用新型的一方面的目的是提供一种节省成本的半导体器件。
本实用新型的至少一方面涉及一种半导体器件，其特征在于，包括：第一衬底；第二衬底；在所述第一衬底上方形成的第一导电层；在所述第二衬底上方形成的第二导电层，其中所述第二衬底邻近所述第一衬底设置；以及跨所述第一衬底的所述第一导电层和所述第二衬底的所述第二导电层而形成的互连件。
优选地，所述第一衬底的第一侧表面和所述第一导电层接触所述第二衬底的第一侧表面和所述第二导电层。
优选地，所述第一导电层沿所述第一衬底的所述第一侧表面向下形成，并且所述第二导电层沿所述第二衬底的所述第一侧表面向下形成。
优选地，半导体器件还包括：所述第一衬底的所述第一侧表面的外延部；以及所述第二衬底的所述第一侧表面的凹陷部，其中所述外延部被设置到所述凹陷部中，以联锁所述第一衬底和所述第二衬底。
优选地，所述第一导电层在所述外延部上方延伸，并且所述第二导电层延伸到所述凹陷部中。
优选地，半导体器件还包括邻近所述第一衬底设置的第三衬底，其中所述第三衬底的侧表面接触所述第一衬底的侧表面。
优选地，所述第一衬底包括多边形形状。
优选地，所述第一衬底包括第一半导体管芯，并且所述第二衬底包括第二半导体管芯。
优选地，所述第一导电层接触所述第二导电层。
本实用新型的至少一方面涉及一种半导体器件，其特征在于，包括：第一半导体管芯；第二半导体管芯；在所述第一半导体管芯上方形成的第一导电层；以及在所述第二半导体管芯上方形成的第二导电层，其中所述第二半导体管芯邻近所述第一半导体管芯设置，其中所述第一半导体管芯的第一侧表面和所述第一导电层接触所述第二半导体管芯的第一侧表面和所述第二导电层。
本实用新型的一方面的技术效果是所提供的半导体器件是节省成本的。
附图说明
图1示出了相邻半导体管芯之间的常见焊丝互连结构；
图2a至图2d示出了具有多个由划片街区隔开的半导体管芯的半导体晶圆；
图3a至图3d示出了在具有接触侧表面的相邻半导体管芯之间形成管芯间互连的工艺；
图4a至图4b示出了沿半导体管芯的侧表面垂直向下形成导电层；
图5a至图5c示出了在半导体管芯的侧表面上形成导电外延部和凹陷部；
图6a至图6b示出了在半导体管芯的侧表面上形成具有角形轮廓的导电外延部和凹陷部；
图7a至图7b示出了在半导体管芯具有导电外延部和凹陷部的多个侧面上的管芯间互连；
图8示出了具有角形侧表面的半导体管芯的管芯间互连；
图9示出了矩形封装件中的多个半导体管芯的管芯间互连；
图10示出了六边形封装件中的多个半导体管芯的管芯间互连；以及
图11示出了衬底上的成对半导体管芯的管芯间互连。
具体实施方式
下文参照附图描述了一个或多个实施方案，其中同样的数字代表相同或相似的元件。虽然为了实现某些目标而按照最佳方式描述附图，但该描述意在覆盖可包括在本公开内容的精神和范围内的替代形式、修改形式和等同形式。本文所用的术语“半导体管芯”是指该词语的单数和复数形式，因此可指代单个半导体器件和多个半导体器件。
半导体器件一般采用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个管芯。晶圆上的每个管芯包括有源电子部件和无源电子部件，有源电子部件和无源电子部件电连接以形成功能电路。有源电子部件诸如晶体管和二极管具有控制电流流动的能力。无源电子部件(例如，电容器、电感器和电阻器)形成执行电路功能所必需的电压电流关系。
后端制造是指将成品晶圆分割或切割成单独的半导体管芯，并封装半导体管芯以实现结构支撑、电互连和环境隔离。使用等离子蚀刻、激光切割工具或锯片沿晶圆的非功能区(称为划片街区或划道)对晶圆进行切割。在切割后，单独半导体管芯被安装至封装衬底，该封装衬底包括用于与其他系统部件互连的引脚或接触焊盘。然后将形成在半导体管芯上方的接触焊盘连接至封装件内的接触焊盘。电连接可利用导电层、凸块、柱状凸块、导电膏或焊丝形成。密封剂或其他模制材料沉积在封装件上方，以提供物理支撑和电绝缘隔离。然后，将成品封装件插入到电系统中，半导体器件的功能便可提供给其他系统部件使用。
图2a示出具有基极衬底材料102诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或其他基体半导体材料以提供结构支撑的半导体晶圆100。多个半导体管芯或部件104形成在晶圆100上，通过无源的管芯间晶圆区域或者说锯道106隔开，如上所述。划片街区106提供用以将半导体晶圆100切割成单独半导体管芯104的切割区域。在一个实施方案中，半导体晶圆100的宽度或直径为100-450毫米(mm)，厚度为50-100微米(μm)或15-250μm。
图2b示出了半导体晶圆100的一部分的剖视图。每个半导体管芯104具有背面或非有源表面108以及有源表面或有源区110，有源表面或有源区包括模拟电路或数字电路，所述模拟电路或数字电路的具体实施形式是在管芯内形成的并且根据管芯的电子设计和功能而电互连的有源器件、无源器件、导电层和介电层。例如，该电路可包括一个或多个晶体管、二极管以及在有源表面110内形成以实现模拟电路或数字电路(例如，数字信号处理器(DSP)、微控制器、ASIC、标准逻辑、放大器、时钟管理、存储器、接口电路和其他信号处理电路)的其他电路元件。半导体管芯104可还包括用于RF信号处理的集成无源器件(IPD)，例如电感器、电容器和电阻器。有源表面110可包括图像传感器区域，其在互补金属氧化物半导体(CMOS)或N型金属氧化物半导体(NMOS)技术中的实施形式是半导体电荷耦合器件(CCD)和有源像素传感器。或者，半导体管芯104可以是光学透镜、检测器、垂直腔面发射激光器(VCSEL)、波导、堆叠管芯、电磁(EM)滤波器或多芯片模块。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在有源表面110上方形成导电层112。导电层112可以是一层或多层铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)、钛(Ti)、钛钨(TiW)或其他合适的导电材料。导电层112用作与有源表面110上的电路电连接的管芯间接触垫。在一个实施方案中，导电层112在半导体管芯104的边缘处或边缘附近形成。
作为质量控制流程的一部分，半导体晶圆100经过电测试和检查。使用人工目视检查和自动光学系统对半导体晶圆100进行检查。可使用软件对半导体晶圆100进行自动光学分析。目视检查方法可采用诸如扫描电子显微镜、高强度光或紫外线或者金相显微镜的设备。检查半导体晶圆100的结构特性，包括翘曲、厚度变化、表面颗粒、不规则性、开裂、分层和变色。
半导体管芯104内的有源部件和无源部件经受晶圆级的电性能和电路功能测试。如图2c中所示，使用包括多个探针或测试引线118的测试探头116或者其他测试装置来测试每个半导体管芯104的功能和电参数。探针118用于与每个半导体管芯104上的节点或导电层112形成电接触，并且向接触垫112提供电刺激。半导体管芯104响应电刺激，该响应由计算机测试系统120测量并与预期响应进行比较，以测试半导体管芯的功能。电测试内容可包括电路功能、引线完整性、电阻率、连续性、可靠性、结深、ESD、RF性能、驱动电流、阈值电流、泄漏电流以及特定于部件类型的操作参数。对半导体晶圆100进行检查和电测试使被指定为已知合格管芯(KGD)的那些半导体管芯104能够用于半导体封装。
在图2d中，采用等离子蚀刻将半导体晶圆100沿划片街区106切割成单个半导体管芯104。等离子蚀刻的优点是可使半导体管芯104形成精密的侧表面，同时可保持基极衬底材料的结构和完整性。或者，利用锯片或激光切割工具122将半导体晶圆100沿划片街区106切割成单个半导体管芯104。可对单个半导体管芯104进行检查和电测试，以鉴定切割后的KGD。
图3a至图3d示出了在具有接触侧表面的并排半导体管芯之间形成管芯间互连构造的工艺。图3a示出了包含牺牲基极材料(例如，硅、聚合物、氧化铍、玻璃或其他合适的低成本刚性材料)的载体或临时衬底130的一部分的剖视图，所述牺牲基极材料用于结构支撑。衬底130还可以是引线框、紫外(UV)或非UV胶带、安装到膜框的胶带、插入物、板或坚硬胶带。接口层或双面胶带132在衬底130上方形成为临时粘合剂结合膜、蚀刻停止层或热释放层。
采用拾放操作将图2a至图2d的半导体管芯104安装到衬底130，其中背面108朝向衬底取向，并且并排半导体管芯104的基极衬底材料102的侧表面134在135处对准。图3b示出了安装到衬底130以实现重组或重构晶圆137的半导体管芯104。具体地讲，半导体管芯104a的基极衬底材料102的侧表面134与半导体管芯104b的基极衬底材料102的侧表面134直接物理接触。一般来说，半导体管芯104的侧表面134与并排半导体管芯104的侧表面接触。或者，并排半导体管芯104之间的距离可忽略不计，为小于20微米(μm)或小于5μm。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺形成导电层136，以与半导体管芯104a-104b的导电层112重叠。在一个实施方案中，使用等离子增强化学气相沉积(PeCVD)工艺跨半导体管芯104a的导电层112和半导体管芯104b的导电层112而形成导电层136。导电层136可以是一层或多层Al、Cu、Sn、Ni、Au、Ag、Ti、TiW或其他合适的导电材料。导电层136还可以是各向异性导电膜(ACF)。导电层136提供半导体管芯104a的导电层112与半导体管芯104b的导电层112的电互连，两个导电层并排设置，并且侧表面134彼此物理接触。导电层112可包含镀覆的焊料和焊剂。半导体管芯104a-104b的导电层112在焊料回流时进行电连接。
或者，使用蒸镀、电解电镀、化学电镀、球降(ball drop)或丝网印刷工艺将导电材料沉积在半导体管芯104a的导电层112和半导体管芯104b的导电层112之间的接合处上方，参见图3c。导电材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，并且具有任选的焊剂。例如，导电材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或结合工艺将导电材料结合到半导体管芯104a-104b的导电层112。在一个实施方案中，通过将导电材料加热到其熔点以上，使该材料回流，从而形成互连件138。在一些应用中，再次使互连件138回流，以提高与导电层112的电接触效率。互连件138还可压缩结合或热压缩结合到导电层112。导电材料可以是利用紫外光或热量进行固化的导电环氧树脂。应当注意，单个互连件138在半导体管芯104a-104b上的导电层112之间提供电互连。
图3d示出了半导体管芯104a-104d的顶视图，其中每个半导体管芯的侧表面134与配对半导体管芯的侧表面直接物理接触。半导体管芯104a的基极衬底材料102的侧表面134与半导体管芯104b和104c的基极衬底材料102的侧表面134接触。半导体管芯104d的基极衬底材料102的侧表面134与半导体管芯104b和104c的基极衬底材料102的侧表面134接触。
互连件138跨半导体管芯104a的导电层112和半导体管芯104b的导电层112而形成，以在半导体管芯之间形成电互连。互连件138跨半导体管芯104a的导电层112和半导体管芯104c的导电层112而形成，以在半导体管芯之间形成电互连。互连件138跨半导体管芯104b的导电层112和半导体管芯104d的导电层112而形成，以在半导体管芯之间形成电互连。互连件138跨半导体管芯104c的导电层112和半导体管芯104d的导电层112而形成，以在半导体管芯之间形成电互连。互连件138表示可跨导电层112而形成的一种类型的互连件。半导体管芯104a-104d的侧表面134之间的直接接触(或可忽略不计的距离)允许通过以下方式实现半导体管芯104a-104d的导电层112之间的小距离管芯间互连：例如导电胶、微凸块、印刷焊料、焊丝、喷镀膜、蒸镀膜、导电环氧树脂、ACF或其他最小距离电互连。单个互连件138在半导体管芯104a-104d上的导电层112之间提供电互连。
管芯间互连构造缩减了半导体封装件的尺寸和成本，并且可应用于大部分(即便不是全部)半导体材料。如果封装件区域为矩形并且半导体管芯104a-104b在其中以联锁构型接触，则可增加半导体封装件的占用面积或总可用面积的效率。而且与图1所述的分开的半导体管芯之间的焊丝相比，这种布置的电感和电阻降低。
图4a至图4b示出了在并排半导体管芯之间形成管芯间互连构造的另一工艺。图4a示出了具有有源表面142和侧表面144的半导体管芯或衬底140a和140b(与从半导体晶圆100切割的半导体管芯104相似)的正交视图。使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在半导体管芯140a的有源表面142和侧表面144上方形成导电层146。同样，使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在半导体管芯140b的有源表面142和侧表面144上方形成导电层147。导电层146和147可以是一层或多层Al、Cu、Sn、Ni、Au、Ag、Ti、TiW或其他合适的导电材料。导电层146-147用作分别与半导体管芯140a-140b上的有源表面142上的电路电连接的管芯间接触区。
采用拾放操作将半导体管芯140a-140b放在一起。图4b示出了半导体管芯140a的基极衬底材料的侧表面144与半导体管芯140b的基极衬底材料的侧表面144直接物理接触的顶视图。半导体管芯140a的侧表面144上的导电层146与半导体管芯140b的侧表面144上的导电层147对准并形成电接触，从而实现较大的接触表面积。一般来说，每个半导体管芯140的侧表面144与另一个并排半导体管芯140的侧表面形成接触，同时导电层146与导电层147形成电连接，从而提供较大的接触表面积。
使用蒸镀、电解电镀、化学电镀、焊球滴落(ball drop)或丝网印刷工艺将导电材料沉积在半导体管芯140a的导电层146和半导体管芯140b的导电层147之间的接合处上方。导电材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，并且具有任选的焊剂。例如，导电材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或结合工艺将导电材料结合到半导体管芯140a-140b的导电层146-147。在一个实施方案中，通过将导电材料加热到其熔点以上，使该材料回流，从而形成互连件148。在一些应用中，再次使互连件148回流，以提高与导电层146-147的电接触效率。互连件148还可压缩结合或热压缩结合到导电层146-147。导电材料可以是利用紫外光或热量进行固化的导电环氧树脂。
互连件148跨半导体管芯140a的导电层146和半导体管芯140b的导电层147之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件148可沿侧表面144上的导电层146和147向下流动，以实现更大的牢固结合部并为制造公差作出考虑。互连件148表示可跨导电层146-147而形成的一种类型的互连件。半导体管芯140a-140d的侧表面144之间的直接接触允许通过以下方式实现半导体管芯140a-140d的导电层146-147之间的小距离管芯间互连：例如导电胶、微凸块、印刷焊料、焊丝、喷镀膜、蒸镀膜、导电环氧树脂、ACF或其他最小距离电互连。
图5a至图5c示出了在联锁并排半导体管芯之间形成管芯间互连构造的另一工艺。图5a示出了具有有源表面152和侧表面154的半导体管芯或衬底150a和150b(与从半导体晶圆100切割的半导体管芯104相似)的正交视图。半导体管芯150a的侧表面154经过等离子蚀刻而形成外延部156，并且半导体管芯150b的侧表面154经过等离子蚀刻而形成凹陷部158。精密等离子蚀刻允许外延部156和凹陷部158以能够紧密且牢固地联锁在一起的尺寸形成。等离子蚀刻形成了半导体管芯104具有外延部156和凹陷部158的精密侧表面，同时保持基极衬底材料的结构和完整性。
在图5b中，使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在半导体管芯150a的有源表面152和侧表面154的外延部156上方形成导电层160。同样，在半导体管芯150b的有源表面152和侧表面154的凹陷部158上方形成导电层161。导电层160-161可以是一层或多层Al、Cu、Sn、Ni、Au、Ag、Ti、TiW或其他合适的导电材料。导电层160-161用作分别与半导体管芯150a-150b的有源表面152上的电路电连接的管芯间接触区。
采用拾放操作将半导体管芯150a-150b放在一起。半导体管芯150a-150b被布置成使得被导电层160覆盖的外延部156与被导电层161覆盖的凹陷部158对准。一旦外延部156插入凹陷部158中，半导体管芯150a-150b便被牢固地联锁。图5c示出了被导电层160覆盖的外延部156插入被导电层161覆盖的凹陷部158中并且半导体管芯150a与半导体管芯150b联锁的顶视图。半导体管芯150a的基极衬底材料的侧表面154与半导体管芯150b的基极衬底材料的侧表面154直接物理接触。半导体管芯150a的外延部156上方的导电层160与半导体管芯150b的凹陷部158上的导电层161形成电连接，从而提供较大的接触表面积。
使用蒸镀、电解电镀、化学电镀、焊球滴落(ball drop)或丝网印刷工艺将导电材料沉积在半导体管芯150a的有源表面152上的导电层160和半导体管芯150b的有源表面152上的导电层161之间的接合处上方。导电材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，并且具有任选的焊剂。例如，导电材料可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或结合工艺将导电材料结合到半导体管芯150a-150b的有源表面152上的导电层160-161。在一个实施方案中，通过将导电材料加热到其熔点以上，使该材料回流，从而形成互连件162。在一些应用中，再次使互连件162回流，以提高与导电层160-161的电接触效率。互连件162还可压缩结合或热压缩结合到导电层160-161。导电材料可以是利用紫外光或热量进行固化的导电环氧树脂。
互连件162跨半导体管芯150a的有源表面152上的导电层160和半导体管芯150b的有源表面152上的导电层161之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件162可沿侧表面154上的导电层160和161向下流动，以实现更大的牢固结合部并为制造公差作出考虑。互连件162表示可跨导电层160-161而形成的一种类型的互连件。半导体管芯150a-150b的外延部156和凹陷部158之间的直接接触允许通过以下方式实现半导体管芯150a-150b的导电层160-161之间的小距离管芯间互连：例如导电胶、微凸块、印刷焊料、焊丝、喷镀膜、蒸镀膜、导电环氧树脂、ACF或其他最小距离电互连。
图6a示出了另一实施方案的正交视图，其中外延部156具有角形轮廓164并且凹陷部158具有相对的角形轮廓166，以实现更牢固的联锁。精密等离子蚀刻允许具有角形轮廓164的外延部156和具有角形轮廓166的凹陷部158以能够紧密且牢固地联锁在一起的尺寸形成。等离子蚀刻形成了半导体管芯104带有角形轮廓外延部156和角形轮廓凹陷部158的精密侧表面，同时保持基极衬底材料的结构和完整性。使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在半导体管芯150a的有源表面152和侧表面154的角形轮廓外延部156上方形成导电层160。同样，在半导体管芯150b的有源表面152和侧表面154的角形轮廓凹陷部158上方形成导电层161。
图6b是另一实施方案的顶视图，其中具有角形轮廓164的外延部156插入具有相对的角形轮廓166的凹陷部158中。半导体管芯150a的基极衬底材料的侧表面154与半导体管芯150b的基极衬底材料的侧表面154直接物理接触。半导体管芯150a的角形轮廓外延部156上方的导电层160与半导体管芯150b的角形轮廓凹陷部158上的导电层161形成电连接，从而提供较大的接触表面积。互连件168跨半导体管芯150a的有源表面152上的导电层160和半导体管芯150b的有源表面152上的导电层161之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件168可沿侧表面154上的导电层160和161向下流动，以实现更大的牢固结合部并为制造公差作出考虑。具有角形轮廓外延部和角形轮廓凹陷部的联锁特征可在半导体管芯150a-150b的任一侧表面154上形成。
联锁特征可在半导体管芯的任一侧表面上形成。图7a示出了具有凹陷部172的半导体管芯或衬底170，所述凹陷部被导电层覆盖并且在侧表面174上形成，类似于图5b。半导体管芯或衬底176,178,180,182各自具有外延部184，所述外延部被导电层覆盖并且在侧表面186上形成，类似于图5b。半导体管芯176-182的外延部184插入半导体管芯170的凹陷部172中。图7b示出了半导体管芯176-182接触半导体管芯170的每侧，其中被导电层覆盖的外延部184和被导电层覆盖的凹陷部172之间的接触提供了管芯间电互连。
图8示出了具有角形侧表面192的半导体管芯或衬底190a-190b的另一实施方案。导电层194可在半导体管芯190a的有源表面196上形成，类似于图3a至图3d，并且/或者沿侧表面192垂直向下形成，类似于图4a至图4b。同样，导电层195可在半导体管芯190b的有源表面196上形成。半导体管芯190a的基极衬底材料的侧表面192与半导体管芯190b的基极衬底材料的侧表面192直接物理接触或相距可忽略不计的距离。半导体管芯190a的导电层194与半导体管芯190b的导电层195形成接触或相距可忽略不计的距离。互连件198跨半导体管芯190a的有源表面196上的导电层194和半导体管芯190b的有源表面196上的导电层195之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件198可沿侧表面192上的导电层198向下流动，以实现更大的牢固结合部并为制造公差作出考虑。
图9示出了管芯间互连构造的另一实施方案，其中半导体管芯或衬底200具有十字或“+”形状因数。半导体管芯或衬底202,204,206,208被设置在“+”形状因数的L形凹口内，以形成矩形半导体封装件209。导电层212可在半导体管芯200-208的有源表面上形成，类似于图3a至图3d，并且/或者沿侧表面210垂直向下形成，类似于图4a至图4b。半导体管芯200的基极衬底材料的侧表面210与半导体管芯202-208的基极衬底材料的侧表面210直接物理接触或相距可忽略不计的距离。半导体管芯200的导电层212与半导体管芯202-208的导电层212形成接触或相距可忽略不计的距离。互连件214跨半导体管芯200的有源表面上的导电层212和半导体管芯202-208的有源表面上的导电层212之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件214可沿侧表面210上的导电层212向下流动，以实现更大的牢固结合部并为制造公差作出考虑。
图10示出了管芯间互连构造的另一实施方案，其中半导体管芯或衬底220具有多边形形状因数(例如，六边形管芯)。半导体管芯或衬底222,224,226,228,229,230被设置在每个侧表面232上，以制成星形半导体封装件234。导电层236可在半导体管芯222-230的有源表面上形成，类似于图3a至图3d，并且/或者沿侧表面232垂直向下形成，类似于图4a至图4b。半导体管芯220的基极衬底材料的侧表面232与半导体管芯222-230的基极衬底材料的侧表面232直接物理接触或相距可忽略不计的距离。半导体管芯220的导电层236与半导体管芯222-230的导电层236形成接触或相距可忽略不计的距离。互连件238跨半导体管芯220的有源表面上的导电层236和半导体管芯222-230的有源表面上的导电层236之间的接合处而形成，以在半导体管芯之间形成电互连。在回流期间，互连件238可沿侧表面232上的导电层236向下流动，以实现更大的牢固结合部并为制造公差作出考虑。半导体管芯220的多边形形状因数增加了半导体封装件的占用面积或总可用面积的效率。
图11示出了管芯间互连构造的另一实施方案，其中多对半导体管芯或衬底240a-240b被设置在衬底或引线框242上方。半导体管芯240a的基极衬底材料的侧表面244与半导体管芯240b的基极衬底材料的侧表面244直接物理接触或相距可忽略不计的距离。导电层246可使用电镀工艺在半导体管芯240a-240b的有源表面上形成，类似于图3a至图3c，并且/或者沿侧表面244垂直向下形成，类似于图4a至图4b。导电层246横跨半导体管芯240a-240b，以在半导体管芯之间形成电互连。
如上所述的管芯间互连构造缩减了半导体封装件尺寸和成本，并且可应用于大部分(即便不是全部)半导体材料。而且与分开的半导体管芯之间的焊丝相比，这种布置的电感和电阻降低。
虽然已详细示出并描述了一个或多个实施方案，但技术人员将认识到，在不脱离本公开的范围的情况下，可对这些实施方案做出修改和调整。下文列举了多个示例性实施方案，但其他实施方案也在本公开的范围内。
在第一实施方案中，形成半导体器件的方法包括以下步骤：提供第一半导体管芯和第二半导体管芯；在第一半导体管芯上方形成第一导电层，在第二半导体管芯上方形成第二导电层；并且邻近第一半导体管芯设置第二半导体管芯，其中第一半导体管芯的侧表面和第一导电层接触第二半导体管芯的侧表面和第二导电层。
在第二实施方案中，第一实施方案的方法还包括以下步骤：跨第一半导体管芯的第一导电层和第二半导体管芯的第二导电层形成互连件。
在第三实施方案中，第一实施方案的方法还包括以下步骤：沿第一半导体管芯的侧表面向下形成第一导电层；并且沿第二半导体管芯的侧表面向下形成第二导电层。
在第四实施方案中，第一实施方案的方法还包括以下步骤：形成第一半导体管芯的侧表面的外延部；形成第二半导体管芯的侧表面的凹陷部；并且将外延部设置到凹陷部中，以联锁第一半导体管芯和第二半导体管芯。
在第五实施方案中，第一实施方案的方法还包括以下步骤：在第一半导体管芯和第二半导体管芯的侧表面上利用等离子蚀刻工艺。
在第六实施方案中，第一实施方案的第一半导体管芯的第一导电层和第二半导体管芯的第二导电层包含导电环氧树脂或各向异性导电膜。
在第七实施方案中，半导体器件包括第一半导体管芯和第二半导体管芯。第一导电层在第一半导体管芯上方形成。第二导电层在第二半导体管芯上方形成。邻近第一半导体管芯设置第二半导体管芯，其中第一半导体管芯的第一侧表面和第一导电层接触第二半导体管芯的第一侧表面和第二导电层。
在第八实施方案中，第七实施方案的半导体器件还包括在第一半导体管芯的第一导电层和第二半导体管芯的第二导电层上方形成的互连件。
在第九实施方案中，第八实施方案的互连件包括在第一半导体管芯的第一导电层和第二半导体管芯的第二导电层之间的接合处上方形成的导电材料。
在第十实施方案中，第七实施方案的第一导电层沿第一半导体管芯的第一侧表面向下形成，并且第二导电层沿第二半导体管芯的第一侧表面向下形成。
在第十一实施方案中，第七实施方案的半导体器件还包括第一半导体管芯的第一侧表面的外延部。还形成了第二半导体管芯的第一侧表面的凹陷部。外延部被设置到凹陷部中，以联锁第一半导体管芯和第二半导体管芯。
在第十二实施方案中，第十一实施方案的第一导电层在外延部上方延伸，并且第二导电层延伸到凹陷部中。
在第十三实施方案中，第七实施方案的半导体器件还包括邻近第一半导体管芯设置的第三半导体管芯，其中第三半导体管芯的侧表面接触第一半导体管芯的第二侧表面。

Claims (10)

1.一种半导体器件，其特征在于，包括：
第一衬底；
第二衬底；
在所述第一衬底上方形成的第一导电层；
在所述第二衬底上方形成的第二导电层，其中所述第一衬底直接接触所述第二衬底以及所述第一导电层直接接触所述第二导电层，以形成半导体封装。
2.根据权利要求1所述的半导体器件，其中所述第一衬底的侧表面接触所述第二衬底的侧表面。
3.根据权利要求2所述的半导体器件，其中所述第一导电层沿所述第一衬底的侧表面向下形成，并且所述第二导电层沿所述第二衬底的侧表面向下形成。
4.根据权利要求2所述的半导体器件，还包括：
所述第一衬底的侧表面的外延部；以及
所述第二衬底的侧表面的凹陷部，其中所述外延部被设置到所述凹陷部中，以联锁所述第一衬底和所述第二衬底。
5.根据权利要求4所述的半导体器件，其中所述第一导电层在所述外延部上方延伸，并且所述第二导电层延伸到所述凹陷部中。
6.一种半导体器件，其特征在于，包括：
第一半导体管芯；以及
第二半导体管芯，所述第一半导体管芯的侧表面与所述第二半导体管芯的侧表面物理接触，并且所述第一半导体管芯电连接至所述第二半导体管芯，以形成半导体封装。
7.根据权利要求6所述的半导体器件，还包括：
在所述第一半导体管芯上方形成的第一导电层；
在所述第二半导体管芯上方形成的第二导电层，其中第一导电层直接接触所述第二导电层。
8.根据权利要求7所述的半导体器件，其中所述第一导电层沿所述第一半导体管芯的侧表面向下形成，并且所述第二导电层沿所述第二半导体管芯的侧表面向下形成。
9.根据权利要求7所述的半导体器件，还包括：
所述第一半导体管芯的侧表面的外延部；以及
所述第二半导体管芯的侧表面的凹陷部，其中所述外延部被设置到所述凹陷部中，以联锁所述第一半导体管芯和所述第二半导体管芯。
10.根据权利要求9所述的半导体器件，其中所述第一导电层在所述外延部上方延伸，并且所述第二导电层延伸到所述凹陷部中。
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