CN206639796U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN206639796U
CN206639796U CN201720199061.4U CN201720199061U CN206639796U CN 206639796 U CN206639796 U CN 206639796U CN 201720199061 U CN201720199061 U CN 201720199061U CN 206639796 U CN206639796 U CN 206639796U
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layer
layers
coupled
semiconductor devices
wafer
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林育圣
野间崇
石部真三
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本实用新型涉及半导体器件。所述半导体器件包括：具有第一侧和与第一侧相对的第二侧的半导体层；耦接在所述第二侧的一个或多个导电焊盘；一个或多个电绝缘层，其耦接在所述第二侧并且具有一个或多个开口，这些开口提供通向所述一个或多个导电焊盘的入口；耦接在所述半导体层的第一侧上的导电层；耦接在所述导电层上的一个或多个背金属层；耦接在所述一个或多个导电焊盘上方的一个或多个焊盘上金属化(OPM)层，所述一个或多个OPM层包括镍层，以及；耦接在所述一个或多个OPM层上方的扩散阻挡层；其中所述半导体器件包括绝缘栅双极晶体管和/或二极管。本实用新型解决的一个技术问题是防止镍扩散到焊料中，实现的一个技术效果是提供一种改进的半导体器件。

Description

半导体器件
背景技术
1.技术领域
本文档的各方面整体涉及半导体器件。
2.背景技术
半导体制造工艺可涉及许多步骤。在一些工艺中，晶圆接纳一个或多个层，例如导电层。导电层可用于提供从晶圆切割的各个半导体器件的电接触区域。导电层可包括位于晶圆背面的一个或多个背金属(BM)层和位于晶圆正面的一个或多个焊盘上金属化(OPM)层。
实用新型内容
本实用新型解决的一个技术问题是防止镍扩散到焊料中。
半导体器件的实施方式可包括：具有第一侧和与第一侧相对的第二侧的半导体层；耦接在所述第二侧的一个或多个导电焊盘；一个或多个电绝缘层，其耦接在所述第二侧并且具有一个或多个开口，这些开口提供通向所述一个或多个导电焊盘的入口；耦接在所述半导体层的第一侧上的导电层；耦接在所述导电层上的一个或多个背金属(BM)层；耦接在所述一个或多个导电焊盘上方的一个或多个焊盘上金属化(OPM)层，所述一个或多个OPM层包括镍层，以及；耦接在所述一个或多个OPM层上方的扩散阻挡层；其中所述半导体器件包括绝缘栅双极晶体管(IGBT)和/或二极管。
半导体器件的实施方式可包括以下各项中的一者、全部或任一者：
所述一个或多个BM层可包括镍层。
所述一个或多个BM层可包括钛层和银层。
所述扩散阻挡层可包含化学沉积的金、化学沉积的银和/或有机可焊性保护剂(OSP)。
所述导电层可包含蒸镀的铝。
本实用新型实现的一个技术效果是提供一种改进的半导体器件。
对于本领域的普通技术人员而言，通过具体实施方式以及附图并通过权利要求书，上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述各实施方式，其中类似标号表示类似元件，并且：
图1是其上具有多个半导体器件的半导体晶圆的顶视图；
图2是图1的半导体晶圆的底视图；
图3是绝缘栅双极晶体管(IGBT)的顶视图；
图4是二极管的顶视图；
图5是半导体组件的实施方式的侧面剖视图；
图6是半导体组件的另一实施方式的侧面剖视图；
图7是半导体组件的另一实施方式的侧面剖视图；
图8是在形成图5至图7的半导体组件时形成的半导体组件的实施方式的侧面剖视图；
图9是在形成图6的半导体组件时形成的半导体组件的实施方式的侧面剖视图；
图10是在形成图6的半导体组件时形成的另一半导体组件的侧面剖视图；
图11是在形成图6的半导体组件时形成的另一半导体组件的侧面剖视图；
图12是在形成图6的半导体组件时形成的另一半导体组件的侧面剖视图；
图13是具有与图6组件相同的结构的半导体组件的实施方式的侧面剖视图；
图14是在形成图7的半导体组件时形成的半导体组件的实施方式的侧面剖视图；
图15是在形成图7的半导体组件时形成的另一半导体组件的侧面剖视图；
图16是在形成图7的半导体组件时形成的另一半导体组件的侧面剖视图；
图17是在形成图7的半导体组件时形成的另一半导体组件的侧面剖视图；
图18是在形成图7的半导体组件时形成的另一半导体组件的侧面剖视图，以及；
图19是具有与图7组件相同的结构的半导体组件的实施方式的侧面剖视图。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的符合预期半导体背金属(BM)与焊盘上金属化(OPM)结构及相关方法的许多额外部件、组装工序和/或方法元素将显而易见地与本公开的特定实施方式一起使用。因此，例如，尽管本实用新型公开了特定实施方式，但此类实施方式和实施部件可包括符合预期操作和方法的针对此类半导体背金属(BM)与焊盘上金属化(OPM)结构及相关方法的本领域已知的任何形状、尺寸、样式、类型、型号、版本、量度、浓度、材料、数量、方法元素、步骤等和相关方法，以及实施部件和方法。
现在参见图1至图2，示出了半导体晶圆(晶圆)2的实施方式。该晶圆尚未被切割，并且包括第一侧10和第二侧12。第二侧上包括多个半导体器件4，并且作为非限制性实例，可包括如图3所示的绝缘栅双极晶体管(IGBT)18或如图4所示的二极管24。所述半导体器件可包括他其功率器件，例如金属氧化物半导体场效应晶体管(MOSFET)、GaN器件、SiC器件，并且可用于形成智能功率模块(IPM)、功率集成模块(PIM)等等。IGBT将包括与该晶圆的第二侧12对应的导电区域20和电绝缘区域22。如果所述半导体器件是二极管，则作为非限制性实例，它们可以是快速恢复二极管(FRD)。在各种实施方式中，IGBT可包括650伏特、200安培的IGBT，和/或二极管可包括650伏特、200安培的快速恢复二极管整流器，不过其他器件也可应用本文所公开的原理。
切割线6示出锯道等，其将用于使用诸如锯切、激光打孔、冲压等任何切割技术从晶圆切割各个半导体器件。该晶圆上可包括多个测试区域(过程控制监视器(PCM))8或换句话讲无效区域，这些在实施方式中，这些区域可用于测试各个半导体器件的可操作性和/或可以其他方式用于处理处于处理过程中的晶圆(和/或锯道区域可包括测试区域)。
图2示出了在该晶圆第一侧10中的未去除材料的环16内的凹陷部14。该凹陷部是使用由日本东京的DISCO以商品名TAIKO工艺销售的工艺通过背磨而形成。背磨留下未去除材料的环(TAIKO环)，该环可有助于防止晶圆在处理期间卷曲或以其他方式弯曲，但是同时可使该晶圆背面的大部分变薄，使得可以穿过该晶圆背面(第一侧)进行掺杂。在形成半导体器件的方法的其他实施方式中，可不使用TAIKO工艺，而是可使用(或者可排除)一些其他背磨或其他材料去除技术，和/或可改为穿过第二侧发生掺杂，从而无需在掺杂之前进行背磨或材料去除。在实施方式中，晶圆可以是背景，或以其他方式厚度减小至小至75微米的尺寸。
图5至图7示出了可使用本文所述的工艺形成的半导体组件的三个实施例。图5示出了常规组件26，其包括硅半导体层80，在其顶部是导电焊盘(焊盘)40以及包括聚酰亚胺(PI)层44和氧氮化物层46的一个或多个电绝缘层。在实施方式中，可排除PI层和/或可用一些其他电绝缘层替代氧氮化物层。在包括PI层的实施方式中，该层可以是九微米或约九微米厚。PI层可由非感光性聚酰亚胺形成，例如作为非限制性实例，由日本东京的TorayIndustries公司以商品名SP-483销售的聚酰亚胺。然而，任何合适的绝缘材料都可用于所述电绝缘层，而且这仅仅是示例。
所述电绝缘层包括一个或多个开口，这些开口提供通向焊盘40的入口，如图5所示。所述焊盘、电绝缘层和开口可使用任何材料沉积和去除技术形成，例如电镀、化学镀、旋涂、溅射、蒸镀、化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、掩模、光刻技术等。
附图中所示的所有实施方式中的焊盘40是由AlSi或AlCu形成，但是在其他实施方式中，它们可由任何其他导电材料形成。焊盘本身可形成在半导体层中(或上)的其他导电焊盘上方，因此其本身可称为“顶部金属”层或焊盘上金属化(OPM)层。图5的常规组件中的焊盘由AlSi形成。
还应注意，图5(连同图6至图7和许多其他附图)示出了该半导体晶圆的非常简化的视图以便于查看。例如，图5中所示的剖视图旨在示出整个晶圆的横截面(示出了凹陷部14和TAIKO环的整个横截面)，但是在横截面中仅看到两个焊盘。实际上，如可从图1和图2看到，在任何位置处获取的该晶圆的完整横截面更有可能显露出几十到几百或甚至几千个焊盘。然而，为了便于查看不同的层和元件，这些附图中示出了简化视图。
图5示出半导体层80包括凹陷部，该凹陷部是通过如前所述的TAIKO工艺形成的。该层还包括掺杂区58。可采用任何掺杂技术引入掺杂物，例如注入、沉积和扩散等。可使用一种或多种掺杂物，例如硼、磷等(掺杂物可根据半导体衬底例如硅、GaAs等来选择)。在掺杂区上方形成导电层62。然后形成背金属(BM)层，包括钛层92、镍层94和银层96。BM层以特定构型示出(钛在导电层上方、镍在钛层上方，并且银在镍层上方)，但是在其他实现方式中可使用其他构型。然而，最底层提供扩散阻挡层，以防止在使用焊料将最底部金属层与一些其他元件电耦接和机械耦接的情况下镍扩散到焊料中。
贯穿本公开，术语“上方”相对于各种层和元件使用。该术语不意味着传送在附图中向上或向下的位置，而是意在传达相对外部位置。例如，使用图5的上(上方)和下(下方)方向，放置在焊盘上方的层将在焊盘“上方”，并且放置在导电层下方的层将类似地在导电层“上方”。术语“上方”不意味着表达元件与在其“上方”的元件直接接触。例如，中间层可直接与焊盘耦接，并且次生层可直接与该中间层耦接，并且尽管该次生层可不直接接触焊盘，但该次生层将耦接在焊盘“上方”，因为它将是相对于焊盘的更外层。
因此，常规组件26具有焊盘上金属化(OPM)，其包括AlSi和背金属(BM)层，这些层包括在导电层上方的钛层、镍层和银层。
附图中未示出一种类似于组件26的组件，这种组件具体地讲为焊盘40使用AlCu而不是AlSi，并且使用AlCu作为导电层62的材料。然而，发现使用AlCu能够更好地控制铝楔键合，因此在某些方面比使用AlSi有利。当使用TAIKO环工艺时，在凹陷部的中心和最外面的环之间通常存在倾斜部分和/或台阶部分，并且已发现AlCu与晶圆具有良好的键合，尽管有角度和倾斜部分、斜率的差异等。
在实验中，导电层的AlCu厚度根据具体位置而变化。例如，在一些情况下，在使用TAIKO工艺之后，将AlCu溅射到晶圆的第一侧上，使得在凹陷部的最底部分中，AlCu为1.4微米厚，在最靠近凹陷部的第一倾斜部分处AlCu为1.3微米厚，在凹陷部和环之间的平坦部分处，AlCu的厚度范围从1.4微米到1.3微米，在平坦部分和环之间的第二倾斜/弯曲部分处，AlCu的厚度范围从0.8微米到1.3微米，并且在环本身处，AlCu为约1.3微米厚。在第二实验中，AlCu厚度范围为1.5微米至2.0微米，在第三实验中，其范围为2.6微米至3.2微米。在第一实验中，目标AlCu厚度为1.5微米，在第二实验中，使用了2微米的目标厚度，在第三实验中，使用了3微米的目标厚度。在每种情况下，没有发现晶圆边缘周围发生剥离，并且凹陷部和环之间的区域良好台阶覆盖了AlCu，使得当使用AlCu作为所选材料时，这些厚度中的任一者都可用于导电层。这些实验中的每一者还包括在AlCu溅射之后的退火步骤，然后进行将在下文中描述的Ni/Au化学镀。如上所述，使用AlCu代替AlSi可更好地控制铝楔键合。
图6示出了在某些方面类似于组件26的组件28。在晶圆的背面(第一侧)，代替钛、镍和银BM层，在导电层上方沉积镍层74，然后在该镍层上方沉积扩散阻挡层76。在顶面(第二侧)，镍层68沉积在焊盘40上方，并且扩散阻挡层70沉积在该镍层上方。
图7示出了在某些方面类似于组件26的组件30。在晶圆的背面(第一侧)，层是相同的，但是在顶面(第二侧)，镍层68沉积在焊盘40上方，并且扩散阻挡层70沉积在该镍层上方。
图8至图13代表性地示出了在形成图6的组件时使用/形成的工序(和中间组件)。图8至图10示出了同样在形成图7的组件时使用/形成的步骤和中间组件。
参见图8，组件32包括具有第一侧(底面或背面)36和与第一侧相对的第二侧(正面)38的半导体晶圆34。该晶圆包括一个或多个导电焊盘(焊盘)40。在该实施例中，焊盘由AlCu形成，不过焊盘可由其他导电材料(例如，如前所述的AlSi)或其他材料形成。该晶圆包括一个或多个电绝缘层42，并且在所示的实施方式中，包括耦接在晶圆的第二侧的氮氧化物层46和耦接在该氮氧化物层上方的聚酰亚胺(PI)层44，但是可如前所述使用其他材料和/或可排除PI层。在该代表性实施例中，PI层具有九微米或约九微米的厚度，并且该半导体晶圆由硅形成。所述一个或多个电绝缘层42包括一个或多个开口48，这些开口提供通向焊盘的入口。图8中示出了两个这样的开口。
参见图9，对组件32执行TAIKO研磨工艺以形成具有凹陷部52的组件50。在所示的实施方式中，所述凹陷部是基本上圆形的凹陷部，并且由未去除材料的环54界定。如前所述，可排除TAIKO工艺，并且可使用背磨工艺，将该晶圆的整个第一侧背磨(不留下未去除材料的环)，或者可完全排除背磨工艺。在其中在晶圆的第一侧进行一个或多个研磨或材料去除工艺的实施方式中，可在材料去除之后穿过晶圆的第一侧来掺杂到晶圆中。在排除背磨或材料去除的实施方式中，掺杂可发生在焊盘和一个或多个电绝缘层的沉积之前，并且由此可穿过晶圆的第二侧进行。
图10因此示出了由组件50形成的组件56。组件56包括掺杂区58。掺杂可包括硼、磷和/或其他III/V族元素组合，和/或取决于半导体材料(Si、GaAs等)的任何其他掺杂物材料，以实现所需的合适的电气性能。例如，可以进行硼或磷的第一注入，然后进行两者中的另一者的第二注入，以实现适当的结和/或电气性能。在掺杂之后，在450摄氏度下执行第一退火工艺以实现掺杂物材料的所需分布/移动。可使用例如沉积和扩散、注入等的任何方法来进行掺杂，并且在所示的实现方式中是通过注入来进行掺杂。
图11示出了由组件56形成的组件60。组件60包括导电层62。在所示的实施方式中，该层是2微米厚的溅射AlCu层，并且在360摄氏度下溅射之后进行第二退火工艺。第二退火工艺可有助于在导电层之间形成强键合和/或可导致一些AlCu如期望地扩散到掺杂区中和/或可根据需要使掺杂区中的掺杂物进一步分布/移动。溅射的AlCu层可在硅晶圆与镍BM层和/或稍后将沉积的其他材料之间提供键合层。
图12示出了由组件60形成的组件64。组件64包括背金属(BM)层72和焊盘上金属化(OPM)层66，其中BM层包括镍层(第一镍层)74和扩散阻挡层(第一扩散阻挡层)76，OPM层包括镍层(第二镍层)68和扩散阻挡层(第二扩散阻挡层)70。所述镍层被同时化学沉积，使得第一镍层和第二镍层同时沉积。所述扩散阻挡层也可被同时沉积。所述扩散阻挡层可包含多种材料，例如金(金层)、银(银层)和/或有机可焊性保护剂(OSP)。OSP可以是水基的，并且可包括化合物，例如苯并三唑、咪唑、苯并咪唑等。在所示的实施方式中，第一和第二扩散阻挡层都由金形成，并且同时化学沉积在相应的镍层上方。类似地，由银形成的扩散阻挡层可同时化学沉积。
所述扩散阻挡层有助于防止镍扩散到稍后耦接在焊盘上方或BM层上方的焊料中，并且由此使得顶部金属(TM)可焊接以形成可焊接的顶部金属(STM)。当BM层由与TM层相同的材料形成时，它们当然也是可焊接的。更厚的Ni金属层也可用于提高可靠性，例如作为非限制性实例，在一些汽车应用(和/或其他工业和/或大型家电应用)中。可在正面或底面的镍层和扩散阻挡层之间使用额外的材料。例如，可在正面和/或底面上的镍层和金层之间包括钯(Pd)层以形成Ni/Pd/Au结构，并且在每种情况下这些层中的全部三个可化学沉积(同时沉积两个镍层，然后同时沉积两个钯层，然后同时沉积两个金层)。
图13示出了由组件64形成的组件78。组件78具有例如通过锯切去除的TAIKO环的底部部分。因此，保留的半导体层80仍然包括水平部分和垂直环，并且该结构可使用任何切割技术来切割以形成各个半导体器件。图13的组件78因此具有与图6所示的组件28相同的结构。因此，可通过两个或三个同时进行的化学沉积步骤来形成双面Ni/Au或Ni/Pd/Au结构。
在使用双面Ni/Au OPM/BM层形成IGBT结构的实验中，AlCu BM层厚度的范围在2微米和3微米之间，并且在用氢氟酸(HF)清洁之前和之后检查了晶圆。实验显示晶圆正面和背面均良好化学覆盖了Ni/Au。在使用双面Ni/Au OPM/BM层形成二极管整流器结构的实验中，AlCu BM层厚度的范围在2微米和3微米之间，并且在用氢氟酸(HF)清洁之前和之后检查了晶圆。实验显示晶圆正面和背面均良好化学覆盖了Ni/Au，同时在PCM和划线区域周围覆盖不足(尽管这样的覆盖不足将不影响切割出的器件的工作)。
在其中AlCu BM层的目标厚度为1.5微米且范围在0.8至1.4微米之间的第一实验中，组合的Au/Ni层具有范围从1.6微米至2.2微米的厚度，而且在晶圆中心处，AlCu BM层为1.3微米厚并且组合的Au/Ni层具有1.6微米的厚度。在其中AlCu BM层的目标厚度为2.0微米且范围在1.5至2.0微米之间的第二实验中，组合的Au/Ni层具有范围从1.7微米至2.2微米的厚度，而且在晶圆中心处，AlCu BM层为1.8微米厚并且组合的Au/Ni层具有1.7微米的厚度。在其中AlCu BM层的目标厚度为3.0微米且范围在2.6至3.2微米之间的第三实验中，组合的Au/Ni层具有范围从1.7微米至2.4微米的厚度，而且在晶圆中心处，AlCu BM层为3.0微米厚并且组合的Au/Ni层具有1.7微米的厚度。
在这些实验的每一个中，在整个TAIKO凹陷部和环结构(以及它们之间的过渡的良好台阶覆盖)上方以及Au/Ni层和AlCu层之间，AlCu BM层对晶圆具有良好的粘附，在任一情况下都没有剥离。OPM层可具有相似的Au/Ni厚度，因为在一些情况下它们将同时被化学镀。虽然这些层可单独沉积，但是在一些实施方式中，同时沉积这些层将减少处理时间和成本。此外，对于IGBT实验，在AlCu中没有观察到空隙或尖峰，这样栅极和发射极位置被适当地形成而没有缺陷，从而产生合适的IGBT功能。
将Ni/Au或Ni/Pd/Au层用作OPM和BM层进一步允许使用焊接或其他结合技术(例如键合线、夹子或其他附件)或使用导电粘合剂等。传统结构(例如仅使用AlSi或AlCu OPM的那些结构)不允许焊接，因为薄器件没有受到保护，会使焊料扩散到其中。利用本文所公开的结构，由于存在厚的Ni层，因此器件受到保护，避免了焊料扩散到器件中。
因此已经将各种尺寸用于Ni/Au层。在一些情况下，目标厚度将为1.2微米或约1.2微米。预期该厚度可增加到4至5微米或约4至5微米，而没有应力问题，并且1至3微米或约1至3微米的范围可以是更保守的范围以实现合适的焊料保护，同时避免应力问题。如果Ni/Au层厚度小于0.7微米或小于约0.7微米，则焊点可包括所有的镍厚度，因此可去除对半导体器件的镍层保护。然而，在一些实施方式中，Ni/Au层的厚度可在0.5微米至3.0微米，或约0.5微米至约3.0微米的范围内。由于该结构的顶部部分包括整个晶圆，并且该结构的底部部分去除了大部分晶圆，所以在一些实施方式中可能因为晶圆中心变薄这一特性而需要考虑应力。
当包括金层时，金防止镍氧化。金层可仅为300埃厚，或者仅约300埃厚(其中Ni或Ni/Pd占据Ni/Au或Ni/Pd/Au结构厚度的剩余部分)。然而，在实验中，金层的厚度范围从约192埃到约551埃，并且在实施方式中，该范围内的任何厚度都可起效果。金的使用还保护焊料，免于使镍扩散到焊料中。其他材料例如银和OSP层、例如本文所公开的那些，可用于扩散阻挡层，并且可实现相同的目的。
BM层和TM/OPM层可另选地由不同的材料形成。例如，图8至图10和图14至图19可用于示出用于形成图7的组件30的第二工艺。相应地，该过程可从上文关于图8至图10描述的步骤开始，包括如上所述相同方式的背磨、掺杂物注入和第一退火步骤。图14示出了由组件56形成的组件82。组件82因此具有掺杂区84。在实施方式中，该掺杂区可与掺杂区58相同，或者可在掺杂物、厚度等方面有所不同。在所示的实施方式中，掺杂区84与掺杂区58相同或非常相似。在掺杂区上方沉积导电层86。可使用与半导体良好键合并为BM层的其余部分提供良好键合而不引起应力问题的任何导电材料。在所示的实施方式中，导电层86由蒸镀的铝形成。然后在360摄氏度下进行第二退火工艺。该工艺类似于上述的第二退火工艺，并且可具有相同的目的。
图15示出了由组件82形成的组件88。组件88具有沉积在铝层上方的多个背金属(BM)层90，包括钛层92、镍层94和银层96。在所示的实施例中，这些层被沉积为钛层在铝层上方、镍层在钛层上方并且银层在镍层上方。钛层可防止镍层扩散到铝层中(并且因此可以是扩散阻挡层)，并且银层可以防止镍扩散到焊料中(因此也可以是扩散阻挡层)。然而，其他构型是可能的，并且可使用其他材料。例如，银可以用金或OSP层替代。
BM层可例如通过溅射、蒸镀工艺或电沉积来沉积。它们可化学沉积，尽管这可能需要一个或多个额外的保护正面焊盘的步骤，使得它们不同样地镀覆有金属层。在代表性实施例中，BM层不是化学沉积而是蒸镀的。
虽然具体示出了BM层的Ti/Ni/Ag结构，但是BM层可包括其他材料和/或构型，例如作为非限制性实例：Ti/NiV/Ag、Ti/Ni/Cu、Ti/Ni/Cu/Ni等。不同的构型将适用于不同的器件和/或结合技术。例如，当在处理期间使用Ag烧结时，优选Ti/Ni/Ag结构。
图16示出了由组件88形成的组件98。保护涂层100用于覆盖BM层，使得一个或多个OPM层可化学沉积在焊盘上方而不是沉积在BM层上方。保护涂层可以是聚合物、胶带、有机层等。在所示的实施方式中，它是紫外线(UV)剥离胶带或由美国特拉华州威明顿的杜邦公司以商品名KAPTON销售的胶带。
图17示出了由组件98形成的组件102。使用上述用于双面结构的任何工艺和材料在焊盘上方形成焊盘上金属化(OPM)层104。在图17所示的代表性实施例中，OPM层包括沉积在焊盘上方的镍层106和沉积在该镍层上方的扩散阻挡层108。该镍层可化学沉积，并且如果扩散阻挡层由金或银形成，则该扩散阻挡层同样可化学沉积。如果扩散阻挡层由OSP形成，则其可旋涂或以其他方式涂覆在镍层上方。在该代表性实施例中，扩散阻挡层由金形成，使得该结构具有Ni/Au构型。在其他实施方式中，可使用Ni/Pd/Au构型，如先前关于其他组件所述。
图18示出了由组件102通过移除保护涂层100形成的组件110。例如，如果保护涂层是UV剥离胶带，可使该胶带暴露于UV，然后移除。如果保护涂层是一些其他材料，则可通过蚀刻、研磨等将其移除。图19示出了由组件110通过移除(例如通过锯切/研磨)TAIKO环的在BM层下方延伸的部分而形成的组件112。完成的组件112(其与图7的组件30相同或非常相似)的半导体层80因此包括水平部分，并且仍然包括至少部分地包围BM层的TAIKO环的一部分。组件112/30因此准备用于切割。在实施方式中，图7的OPM层66(包括镍层68和扩散阻挡层70)与图19的OPM层104(包括镍层106和扩散阻挡层108)相同或非常相似。
在使用胶带和胶带移除工艺的实验中，将保护胶带层合物放置在具有Al/Ti/Ni/Ag BM层构型的5.25密耳厚的晶圆上，并且化学沉积Ni/Au OPM层而没有发生胶带剥离。然后在化学沉积Ni/Au之后成功地移除了保护胶带而没有损坏。还在没有BM层的虚拟晶圆上完成了该工艺，类似地也没有剥离和损坏。在这些实验中，Ni/Au OPM层为1.6微米厚。
具有Ti/Ni/Ag BM结构(或Ag作为最底层的类似结构)的优点之一是其不仅允许引线接合和焊接，而且允许Ag烧结以在BM层和一些其他器件/元件/母板等之间形成键合。然而，可以看出，单面化学工艺(在正面进行化学沉积，但在背面或第一侧使用蒸镀和保护涂层)涉及稍微更长和更复杂的工艺，并且成本可能更高。
在附图中未示出但在此简要描述的另一实施方式涉及在AlCu焊盘正上方使用铜OPM层，该铜层具有超过30微米的厚度。该铜层因此可用于焊接和烧结连接件和/或可用于支撑重的Cu线。
在切割之后，各个半导体器件可被包括在任何封装类型中以便最终使用，所述封装类型诸如无引线封装、引线封装、模制封装等。例如，以引用方式并入本文的附录A公开了由美国亚利桑那州菲尼克斯的安森美半导体(ON Semiconductor)公司销售的四引线封装IGBT，并且使用本文所述的任何工艺形成的任何半导体器件可被包括在类似的封装中或采用不同的封装类型。
在使用本文所述的金属化层和其他层的实施方式中，可提高诸如IGBT和二极管(例如FRD)的半导体器件的可靠性。在实施方式中，本文所述的结构和工艺可用于形成在高温下不会扩散的OPM层和BM层(例如Ni/Au结构)。然而，在实施方式中，OPM和BM层是在退火之后添加，以避免退火期间这些层发生扩散(或其他材料扩散进入这些层)。
可使用形成多个半导体器件的方法的各种实施方式来制造本文所公开的各种半导体器件。所述方法的一个具体实施方式包括提供半导体晶圆，该晶圆具有第一侧和与第一侧相对的第二侧，其中一个或多个导电焊盘耦接在第二侧，并且一个或多个电绝缘层耦接在第二侧而且具有一个或多个开口，这些开口提供通向所述一个或多个导电焊盘的入口。所述方法包括将该晶圆的第一侧背磨到期望的厚度，在该晶圆的第一侧上沉积导电层，并且同时在该导电层上方化学沉积第一镍层和在所述一个或多个导电焊盘上方化学沉积第二镍层。所述方法包括同时在第一镍层上方沉积第一扩散阻挡层和在第二镍层上方沉积第二扩散阻挡层。
所述方法可包括其中背磨该晶圆的第一侧包括在由未去除材料的环界定的该晶圆第一侧中形成基本上圆形的凹陷部。
所述方法可包括其中第一扩散阻挡层和第二扩散阻挡层各自包括化学沉积的金和化学沉积的银中的一者。
所述方法可包括其中第一扩散阻挡层和第二扩散阻挡层各自包含有机可焊性保护剂(OSP)。
所述方法可包括其中一个或多个电绝缘层包含聚酰亚胺。
所述方法可包括穿过该晶圆的第一侧将掺杂物引入该晶圆中并将该晶圆退火。
所述方法可包括其中导电层包含AlCu。
所述方法可包括在该晶圆上形成多个绝缘栅双极晶体管(IGBT)和多个二极管中的一者。
形成多个半导体器件的方法的实施方式包括提供半导体晶圆，该晶圆具有第一侧和与第一侧相对的第二侧、耦接在第二侧的一个或多个导电焊盘，以及耦接在第二侧并且具有一个或多个开口的一个或多个电绝缘层，这些开口提供通向所述一个或多个导电焊盘的入口。所述方法包括将该晶圆的第一侧背磨到期望的厚度，在该晶圆的第一侧上沉积导电层并且在该导电层上沉积一个或多个背金属层，所述一个或多个背金属层包括钛层、镍层或银层。所述方法包括用保护涂层覆盖所述一个或多个背金属层，在所述一个或多个导电焊盘上方化学沉积镍层，在该镍层上方沉积扩散阻挡层，并且从所述一个或多个背金属层移除保护涂层。
所述方法可包括其中一个或多个背金属层包括钛层、镍层和银层。
所述方法可包括其中扩散阻挡层包含化学沉积的金、化学沉积的银和有机可焊性保护剂(OSP)中的一者。
所述方法可包括穿过该晶圆的第一侧将掺杂物引入该晶圆。
所述方法可包括其中导电层包含蒸镀的铝。
所述方法可包括其中保护涂层包括胶带。
所述方法可包括通过蒸镀沉积所述一个或多个背金属层。
在以上描述提到半导体背金属(BM)和焊盘上金属化(OPM)结构及相关方法以及实施部件、子部件、方法和子方法的特定实施方式的地方，应当易于显而易见的是，可在不脱离其精神的情况下做出多种修改，并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他半导体背金属(BM)和焊盘上金属化(OPM)结构及相关方法。

Claims (5)

1.一种半导体器件，其特征在于包括：
半导体层，所述半导体层具有第一侧和与所述第一侧相对的第二侧；
耦接在所述第二侧的一个或多个导电焊盘；
一个或多个电绝缘层，所述电绝缘层耦接在所述第二侧并且具有一个或多个开口，所述开口提供通向所述一个或多个导电焊盘的入口；
耦接在所述半导体层的所述第一侧上的导电层；
耦接在所述导电层上的一个或多个背金属层；
耦接在所述一个或多个导电焊盘上方的一个或多个焊盘上金属化层，所述一个或多个焊盘上金属化层包括镍层，以及
耦接在所述一个或多个焊盘上金属化层上方的扩散阻挡层；
其中所述半导体器件包括绝缘栅双极晶体管和二极管中的一者。
2.根据权利要求1所述的半导体器件，其中所述一个或多个背金属层包括镍层。
3.根据权利要求1所述的半导体器件，其中所述一个或多个背金属层包括钛层和银层。
4.根据权利要求1所述的半导体器件，其中所述扩散阻挡层包含化学沉积的金、化学沉积的银和有机可焊性保护剂中的一者。
5.根据权利要求1所述的半导体器件，其中所述导电层包括蒸镀的铝。
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