CN106558566A - 半导体装置和制造半导体装置的方法 - Google Patents

半导体装置和制造半导体装置的方法 Download PDF

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Publication number
CN106558566A
CN106558566A CN201610825014.6A CN201610825014A CN106558566A CN 106558566 A CN106558566 A CN 106558566A CN 201610825014 A CN201610825014 A CN 201610825014A CN 106558566 A CN106558566 A CN 106558566A
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film
interconnection
electroplated
semiconductor device
opening
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利根川丘
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及一种半导体装置和制造半导体装置的方法。半导体装置的特性得到改善。半导体装置被配置为具有设置在互连上方并且具有开口的保护膜和设置在开口中的镀敷膜。将狭缝设置在开口的侧面中，并且将镀敷膜还配置在狭缝中。由此，将镀敷膜设置在开口的侧面中，并且镀敷膜还生长在狭缝中。这导致了在随后的镀敷膜的形成期间的长的镀敷溶液渗透路径。因此，在互连(焊盘区)中不容易形成腐蚀部分，即使形成了腐蚀部分，狭缝的部分也作为牺牲物先于互连(焊盘区)被腐蚀，使得可以抑制腐蚀部分向互连(焊盘区)中的扩展。

Description

半导体装置和制造半导体装置的方法
相关申请的交叉引用
包括说明书、附图和摘要的2015年9月30日提交的日本专利申请No.2015-193172的公开内容通过引用全部并入本文中。
技术领域
本发明涉及半导体装置和制造半导体装置的方法。例如，本发明可优选地应用于在焊盘区上具有镀敷膜的半导体装置。
背景技术
包括半导体元件(诸如MOSFET)和互连的半导体装置通过在半导体衬底上堆叠绝缘膜(诸如氧化硅膜或氮化硅膜)、半导体膜以及导电膜形成。这样的半导体元件通过互连电耦接到焊盘区。焊盘区通过导线接合、夹片接合等耦接到外部端子。
例如，日本未审专利申请公布No.2003-338516公开了其中凸点下金属膜设置在铝电极上的半导体装置。凸点下金属膜具有第一镀敷膜和设置在第一镀敷膜上的第二镀敷膜。将第一镀敷膜和第二镀敷膜设置在有机绝缘膜的开口中，使得第一镀敷膜具有大于有机绝缘膜的厚度，并且第一镀敷膜的周边重叠在有机绝缘膜上。
日本未审专利申请公布No.2011-204886公开了通过焊料材料由铜夹片将电极焊盘耦接到引线框架的技术。
发明内容
本发明人从事对在焊盘区上具有镀敷膜(OPM电极)的半导体装置的研究与开发，并且对改善半导体装置的特性进行了认真的调查。在这样的调查期间，发明人发现了在镀敷膜和焊盘区之间界面处的分离的问题，并且发现在靠近焊盘区和镀敷膜(OPM电极)之间边界的部分的配置中有进一步改善的空间。
其它问题和新颖特点从本说明书和附图的描述可知。
本申请中公开的典型实施例中所描述的配置简要概括如下。
本申请中公开的典型实施例中所描述的半导体装置包括设置在互连上并且具有开口的绝缘膜，以及设置在开口中的镀敷膜。在开口的侧面中设置有狭缝，并且狭缝中也配置有镀敷膜。
本申请中公开的典型实施例中所描述的制造半导体装置的方法包括在互连上的绝缘膜中形成暴露互连表面的部分的开口的步骤，以及在开口中形成镀敷膜的步骤。开口的侧壁中有狭缝，并且在狭缝中也形成镀敷膜。
根据本申请中公开的典型实施例中所描述的半导体装置，可以改善半导体装置的特性。
根据本申请中公开的典型实施例中所描述的制造半导体装置的方法，可制造具有良好特性的半导体装置。
附图说明
图1是例示第一实施例的半导体装置的配置的截面图。
图2是例示对比示例的半导体装置的配置的截面图。
图3是示意性例示镀敷溶液的渗透路径和镀敷膜或互连的腐蚀部分的截面图。
图4是作为示例性半导体元件的功率MOSFET的截面图。
图5是例示第一实施例的半导体装置的制造工艺的截面图。
图6是例示第一实施例的半导体装置的制造工艺的截面图，示出图5之后的制造步骤。
图7是例示第一实施例的半导体装置的制造工艺的截面图，示出图6之后的制造步骤。
图8是例示第一实施例的半导体装置的制造工艺的截面图，示出图7之后的制造步骤。
图9是例示第一实施例的半导体装置的制造工艺的截面图，示出图8之后的制造步骤。
图10是例示第一实施例的半导体装置的制造工艺的截面图，示出图9之后的制造步骤。
图11是例示第一实施例的半导体装置的制造工艺的截面图，示出图10之后的制造步骤。
图12是例示第一实施例的半导体装置的制造工艺的截面图，示出图11之后的制造步骤。
图13是例示第二实施例的半导体装置的配置的截面图。
图14是例示第二实施例的半导体装置的制造工艺的截面图。
图15是例示第二实施例的半导体装置的制造工艺的截面图，示出图14之后的制造步骤。
图16是例示第二实施例的半导体装置的制造工艺的截面图，示出图15之后的制造步骤。
图17是例示第二实施例的半导体装置的制造工艺的截面图，示出图16之后的制造步骤。
图18是例示第二实施例的半导体装置的制造工艺的截面图，示出图17之后的制造步骤。
图19是例示第二实施例的半导体装置的制造工艺的截面图，示出图18之后的制造步骤。
图20是例示第二实施例的半导体装置的制造工艺的截面图，示出图19之后的制造步骤。
图21是例示第二实施例的半导体装置的制造工艺的截面图，示出图20之后的制造步骤。
图22是例示第二实施例的半导体装置的制造工艺的截面图，示出图21之后的制造步骤。
图23是例示第二实施例的半导体装置的制造工艺的截面图，示出图22之后的制造步骤。
图24是例示第三实施例的第一应用的半导体装置的配置的截面图。
图25是例示第三实施例的第一应用的半导体装置的配置的截面图。
图26是例示第三实施例的第二应用的半导体装置的配置的截面图。
图27是例示第三实施例的第三应用的半导体装置的配置的截面图。
图28是例示第三实施例的第四应用的半导体装置的配置的截面图。
具体实施方式
尽管必要时为了方便，以下实施例中的每个都可以在多个部分或实施例中分别描述，但除了特别定义的情况，它们不是彼此不相关的，并且处于一个是另一个的部分或全部的修改、应用、详细解释、补充解释等的关系中。在以下实施例中的每一个中，当提到元件的数字(包括数目、数值、数量和范围)，除了特别定义的情况和该数字原则上清楚地限于具体数字的情况外，该数字不限于具体数字。换言之，该数字可以不小于或不大于该具体数字。
在以下每个实施例中，将认识到，除了特别定义的情况和构成元件原则上可能是不可缺少的情况外，实施例的构成元件(包括元件步骤)不一定是不可缺少的。类似地，在以下每个实施例中，当描述构成元件的形状、位置关系等时，除了特别定义的情况和配置原则上可能不被包括的情况外，应该包括基本密切相关于或类似于这样的形状的任何配置或类似物。这同样适用于元件的数字和类似物(包括数目、数值、数量和范围)。
以下，将参照附图详细描述本发明的一些实施例。在所有用于解释实施例的图中，用相同或相关的标号指示具有相同功能的组件，省略重复描述。在以下实施例中，除了特别需要的情况外，原则上不重复描述相同或相似的部分。
在本实施例中使用的图中，为了更好的可视性，也可以不以阴影表示截面图。
在每个截面图中，每个部位的尺寸不对应于实际装置的尺寸，并且为了更好的可视性，可以将具体的部位例示得相对大。
第一实施例
现在参照图描述第一实施例的半导体装置的结构。
结构描述
图1是例示第一实施例的半导体装置的配置的截面图。第一实施例的半导体装置包括半导体衬底S、设置在半导体衬底S上的层间绝缘膜IL1以及设置在层间绝缘膜IL1上的互连M1。半导体元件设置在半导体衬底S的主表面上，尽管图1中未示出。例如，互连M1通过插塞P1电耦接到半导体元件。
每个都包括绝缘膜的保护膜PRO1和PRO2设置在互连M1上方。保护膜PRO1具有开口OA1，并且互连M1的部分从开口OA1的底部暴露。互连M1的这种暴露部分称为焊盘区PD。保护膜PRO2具有配置在开口OA1上并且尺寸大于开口OA1的开口OA2。
互连M1包括例如铝膜(Al膜)。换言之，互连M1包含铝。本文所描述的Al膜不限于纯净的Al膜，而是主要包含铝的导电材料膜(但示出金属导电性)。Al膜因此包括例如铝(Al)和硅(Si)的复合膜或合金膜。期望该膜中Al的成分比例大于50％(原子百分比)。
保护膜PRO1包括例如氮氧化硅膜。不仅氮氧化硅膜可用作保护膜(覆盖膜)PRO1，而且氧化硅膜或氮化硅膜也可用作保护膜(覆盖膜)PRO1。保护膜PRO2包括例如聚酰亚胺膜。
镀敷膜OPM1设置在作为开口OA1的底部的焊盘区PD上方。镀敷膜OPM2设置在镀敷膜OPM1上方。镀敷膜OPM1包括例如镍(Ni)膜。镍(Ni)膜通过无电镀敷形成在焊盘区PD上方。镀敷膜OPM2包括例如金(Au)膜。金(Au)膜通过无电镀敷形成在镀敷膜OPM1上方。镀敷膜OPM1和OPM2可以各自被称为“焊盘上方的金属”或“焊盘上方的金属电极(OPM电极)”，因为这样的镀敷膜覆盖焊盘区PD。
例如，设置镀敷膜OPM1以抑制由后述的接合导线(导电导线)对焊盘区PD的直接接触所引起的非期望的金属复合物的形成。例如，设置镀敷膜OPM2以改善后述的接合导线(导电导线)到镀敷膜OPM1的附着。
在第一实施例中，狭缝(侧狭缝、凹陷)SL设置在开口OA1的侧面中。在图1中，狭缝SL设置在开口OA1的侧面的底部部分中。狭缝SL可以是凹向开口OA1外部的侧面的一部分。在这种示例性情况下，狭缝SL具有锥形形状。从另一个角度，开口OA1具有开口区，在它的底部的开口区比在它的顶部的开口区大。在图1中，底部的开口区尺寸大于顶部的开口区。将镀敷膜OPM1也设置在狭缝SL中。
以这种方式，将狭缝SL设置在开口OA1的侧面中，并且将镀敷膜OPM1也设置在狭缝SL中，使得可以改善镀敷膜OPM1和互连M1之间的电耦接。
图2是例示对比示例的半导体装置的配置的截面图。在图2的对比示例中，在未设置狭缝SL的情况下设置直的开口OA1。当通过镀敷工艺形成镀敷膜OPM1和OPM2时，镀敷溶液可渗透进镀敷膜OPM1和保护膜PRO1之间的空间中。特别地，当多个镀敷膜(OPM1、OPM2)形成在焊盘区PD上方时，例如，用于镀敷膜OPM2的镀敷溶液可渗透进镀敷膜OPM1和保护膜PRO1之间的空间中。镀敷溶液的这种渗透引起了配置作为底层的镀敷膜或互连的金属(此处，Ni或Al)的腐蚀。特别地，Al容易被镀敷溶液或后述的清洗剂腐蚀。图2中，用MC表示的部分示出了镀敷溶液的渗透路径以及镀敷膜OPM1或互连M1的腐蚀部分。
当腐蚀部分MC这样形成在互连(Al膜)M1上时，在镀敷膜OPM1和互连(焊盘区PD)M1之间出现不良耦接。这进一步引起了在镀敷膜OPM1和互连M1之间的附着的减少，导致它们之间容易分离。
相反地，在第一实施例中，因为将狭缝SL设置在开口OA1的侧面中，所以镀敷溶液的渗透路径长(见图3)。因此不易在互连(焊盘区PD)M1中形成腐蚀部分MC。如图3中所例示的，即使形成了腐蚀部分MC，狭缝SL的一部分也作为牺牲物先于互连(焊盘区PD)M1被腐蚀，使得可以抑制腐蚀部分MC向互连(焊盘区PD)M1中的扩展。此外，填充狭缝SL中的空间的镀敷膜OPM1抑制了镀敷膜OPM1和互连M1之间的分离。图3是示意性例示镀敷溶液的渗透路径和镀敷膜或互连的腐蚀部分的截面图。
腐蚀部分MC不仅可由镀敷溶液的渗透引起，而且可以由清洗剂的渗透引起。特别地，在镀敷步骤之前或之后使用纯水或类似物执行清洗工艺，容易导致由清洗剂的渗透引起的腐蚀。在第一实施例中，也可以针对清洗剂的这种渗透抑制腐蚀部分MC的扩展。
现描述设置在半导体衬底S的主表面上的半导体元件。尽管设置在半导体衬底S的主表面上的半导体元件没有被特别地限制，可举例功率金属氧化物半导体场效应晶体管(MOSFET)作为半导体元件。图4是作为示例性半导体元件的功率MOSFET的截面图。图4中例示的功率MOSFET是沟槽栅纵向MOSFET。该MOSFET是n-沟道MOSFET。
图4中例示的功率MOSFET具有缓冲层BUF和缓冲层BUF上方的漂移层DRL。缓冲层BUF是n+型半导体层，而漂移层DRL是n型半导体层。例如，缓冲层BUF和漂移层DRL构成半导体衬底S。
包括p型半导体区的p型体区PB设置在漂移层DRL的上部中。此外，将每个都包括n+型半导体层的n型发射极区NE设置在p型体区PB上。将包括p型半导体区的p型柱PC设置在p型体区PB下面。
沟槽设置成比p型体区PB深并且延伸进漂移层DRL中。栅绝缘膜GOX设置在每个沟槽的内壁上，并且栅电极GE设置在栅绝缘膜GOX上方以填充沟槽的内部。
层间绝缘膜IL1设置在栅电极GE上方，并且互连M1设置在n型发射极区NE和p型体区PB上，其中插塞P1在n型发射极区NE和p型体区PB之间。在缓冲层BUF的底部上设置背电极EL。电耦接到栅电极GE的未示出的互连也设置在图4中例示的部分中。
在这种示例性情况下，例如，互连M1是顶层互联，参照图1所描述的保护膜PRO1和PRO2设置在互连M1上方，并且互连M1的部分充当焊盘区PD(见图1)。
尽管已举例沟槽栅纵向MOSFET作为第一实施例中的半导体元件，仍然还可以将该结构应用到其他半导体元件，诸如绝缘栅双极型晶体管(IGBT)和快速恢复二极管(FRD)。
制造方法的描述
现描述制造第一实施例的半导体装置的方法，同时进一步阐明半导体装置的配置。图5至12分别是例示第一实施例的半导体装置的制造工艺的截面图。
首先，在半导体衬底S的主表面上形成半导体元件。在这种示例性情况下，将图4中例示的功率MOSFET形成为半导体元件。现参照图4示例性地但是非限制性地描述功率MOSFET的形成工艺。
首先，将包括了包括n型半导体层的支撑衬底和形成在支撑衬底表面上的外延层的半导体衬底S设置作为半导体衬底S。外延层包括了包括n+半导体层的缓冲层BUF和形成在缓冲层BUF上的包括n型半导体层的漂移层DRL。
随后，在漂移层DRL的暴露的表面侧上形成p型体区PB、n型发射极区NE和p型柱区PC。这样的区域通过例如离子注入工艺形成。
随后，选择性地刻蚀半导体衬底S的上部以形成延伸进漂移层DRL中的沟槽。随后，在半导体衬底S和沟槽内部的上方形成栅绝缘膜GOX。例如，通过化学气相淀积(CVD)工艺形成氧化硅膜作为栅绝缘膜GOX。随后，在栅绝缘膜GOX上形成栅电极GE。例如，通过CVD工艺在栅绝缘膜GOX上形成多晶硅膜。随后，多晶硅膜被图案化以形成栅电极GE。
随后，在栅电极GE、n型发射极区NE和p型体区PB的上方形成层间绝缘膜IL1。例如，通过CVD工艺形成氧化硅膜作为层间绝缘膜IL1。
随后，刻蚀n型发射极区NE和p型体区PB上方的层间绝缘膜IL1以形成接触孔C1。随后在接触孔C1和层间绝缘膜IL1上方形成互连M1。例如，通过溅射工艺形成Al膜作为互连M1。例如，Al膜具有约5μm的厚度。可使用诸如AlSi、AlCu和AlSiCu的Al合金膜来代替Al膜。随后，Al膜被图案化以形成互连M1。
随后，如图5中所例示的，在互连M1上方形成保护膜PRO1。例如，通过CVD工艺或类似工艺在层间绝缘膜IL1和互连M1上方淀积厚度约为0.9μm的氮氧化硅膜作为保护膜PRO1。
随后，去除互连M1(Al膜)的焊盘区PD上的保护膜PRO1以形成开口OA1。例如，如图6中所例示的，在保护膜PRO1上形成光致抗蚀剂膜PR1，并且通过曝光和显影去除开口OA1的形成区中的光致抗蚀剂膜PR1。随后，如图7中所例示的，使用光致抗蚀剂膜PR1作为掩模，干法刻蚀保护膜PRO1。即使在暴露互连M1(Al膜)以后，仍然进一步刻蚀保护膜PRO1，也就是保护膜PRO1被进行过刻蚀。
尽管干法刻蚀条件不特别地受限，仍然示例性地执行干法刻蚀，该干法刻蚀在微波功率为800到1200W、压力为60到100Pa并且温度为60到100℃的环境下使用CF4和O4的混合气体作为刻蚀气体。干法刻蚀是各向同性刻蚀，因为半导体衬底不是偏置的。换言之，在刻蚀中各向同性分量大于各向异性分量。执行这样的各向同性干法刻蚀，并且此外执行过刻蚀。例如，过刻蚀的量约为80％。80％的过刻蚀的量意味着过度执行刻蚀一定时间，例如，该一定时间对应于在互连M1(Al膜)的焊盘区PD暴露之前的刻蚀时间的80％。
通过这样的干法刻蚀暴露焊盘区PD中的互连M1(Al膜)。此外，通过随后的过刻蚀形成底切，并且由此在开口OA1的侧面的底部部分中形成狭缝SL。狭缝SL具有约1μm的长度(例如，在纸平面的横向方向上的长度L)。狭缝SL的长度优选为0.5到2.0μm。狭缝SL的过短的长度(小于0.5μm)减少了抑制腐蚀部分MC的效果。大于2.0μm的狭缝SL长度可能引起彼此邻接的导电图案(不同的互连和/或插塞)之间的短路。可通过过刻蚀的量来调整狭缝SL的长度。
在这种示例性情况下，在相同的条件下执行标准刻蚀和随后的过刻蚀，其中执行该标准刻蚀直到互连M1(Al膜)的焊盘区PD暴露。在另一种可能的情况下，标准刻蚀以这样的方式执行，例如，半导体衬底被偏置以执行相对各向异性的刻蚀而非各向同性的刻蚀，而随后的过刻蚀以这样的方式执行，即半导体衬底未被偏置以执行相对各向同向的刻蚀而非各向异性的刻蚀。
随后，通过灰化或类似方法去除光致抗蚀剂膜PR1(图8)。随后，在保护膜PRO1上方形成保护膜PRO2。例如，形成聚酰亚胺膜作为保护膜PRO2。例如，如图9中所例示的，将聚酰亚胺树脂施加到保护膜PRO1上并且将其固化，由此形成光敏聚酰亚胺膜。随后，如图10中所例示的，通过曝光和显影去除开口OA2的形成区中的聚酰亚胺膜。结果是，可形成具有尺寸大于开口OA1的开口OA2的保护膜(聚酰亚胺膜)PRO2以重叠开口OA1。
随后，如图11中所例示的，在开口OA1中形成镀敷膜OPM1。例如，通过无电镀敷工艺形成Ni膜作为镀敷膜OPM1。
首先，去除焊盘区PD中的互连M1(Al膜)表面上的自然氧化膜和有机物，因而该表面从开口OA1的底部暴露。通过例如Ar等离子体处理去除自然氧化膜和有机物。脱脂可单独地执行。随后，执行第一锌酸盐处理。具体地，使锌酸盐溶液与焊盘区PD接触，并且通过用Al置换Zn的反应在焊盘区PD上形成Zn膜。随后使用稀硝酸或类似物分离Zn膜。随后，执行第二次锌酸盐处理。具体地，使锌酸盐溶液与焊盘区PD接触，并且通过用Al置换Zn的反应在焊盘区PD上形成Zn膜。如此重复两次锌酸盐处理，由此可形成致密且均匀的Zn膜。随后，以未示出的Zn膜中的Zn作为核体生长镀敷膜(Ni膜)。
例如，使具有未示出的Zn膜的焊盘区PD接触Ni镀敷溶液，由此形成镀敷膜(Ni膜)OPM1。具体地，使用次磷酸镀敷溶液，将半导体衬底S浸渍在约85℃的镀敷溶液中用于镀敷工艺，使得形成具有约2.5μm厚度的镀敷膜(Ni膜)OPM1。镀敷膜(Ni膜)OPM1生长在焊盘区PD上，同时形成在开口OA1的侧面的底部部分中的狭缝SL中。
随后，如图12中所例示的，在镀敷膜OPM1上方形成镀敷膜OPM2。例如，通过无电镀敷工艺形成Au膜作为镀敷膜OPM2。使焊盘区PD上的镀敷膜(Ni膜)OPM1接触Au镀敷溶液，由此形成镀敷膜(Au膜)OPM2。具体地，使用氰基(cyan)镀敷溶液，将半导体衬底S浸渍在约90℃的镀敷溶液中用于镀敷工艺，使得形成具有约0.05μm厚度的镀敷膜(Au膜)OPM2。
在这样的工艺期间可适当地执行清洗工艺。例如，可在第一次锌酸盐处理之后、在镀敷膜OPM1的形成之后或在镀敷膜OPM2的形成之后使用纯水执行清洗。
以这种方式，在第一实施例中，将狭缝SL设置在开口OA1的侧面中，并且镀敷膜(Ni膜)OPM1也生长在狭缝SL中。这导致了在镀敷膜(Au膜)OPM2形成期间的长的镀敷溶液渗透路径。因此在焊盘区互连(焊盘区PD)M1中不容易形成腐蚀部分MC。此外，即使形成腐蚀部分MC，狭缝SL的部分也作为牺牲物先于互连(焊盘区PD)M1被腐蚀，使得可以抑制腐蚀部分MC向互连(焊盘区PD)M1中的扩展(见图3)。此外，填充狭缝SL中的空间的镀敷膜OPM1抑制了镀敷膜OPM1和互连M1之间的分离。此外，即使在镀敷膜形成步骤之前或之后执行清洗步骤，因为长的清洗渗透路径，在互连(焊盘区PD)M1中也较不容易形成腐蚀部分MC。此外，即使形成了腐蚀部分MC，狭缝SL的部分也作为牺牲物先于互连(焊盘区PD)M1被腐蚀，使得可以抑制腐蚀部分MC向互连(焊盘区PD)M1中的扩展。
随后，半导体衬底S的背侧被抛光以减小半导体衬底S的厚度，并且在半导体衬底S的背侧上淀积金属膜或类似物以形成背电极EL(见图4)。随后，半导体衬底S被进行切割以形成为单个的半导体芯片。
第二实施例
在第一实施例中，保护膜PRO1是单层膜，并且狭缝SL设置在开口OA1的侧壁的底部部分中。在另一个可能的实施例中，开口OA1设置在堆叠膜中，而狭缝SL设置在开口OA1的侧壁的中间部分中。现参照图描述第二实施例的半导体装置的结构。
结构的描述
图13是例示第二实施例的半导体装置的配置的截面图。如同第一实施例，第二实施例的半导体装置包括半导体衬底S、设置在半导体衬底S上的层间绝缘膜IL1以及设置在层间绝缘膜IL1上的互连M1。半导体元件设置在在半导体衬底S的主表面上，尽管图13中未示出。例如，通过插塞P1将互连M1电耦接到半导体元件。
第二实施例和第一实施例(图1)的不同主要在于保护层的堆叠配置以及在于狭缝SL的形成位置；因此，详细描述这样的不同点。
如图13中所例示的，在第二实施例中，将每个都包括绝缘膜的保护膜PRO1、PRO2和PRO3设置在互连M1上。将开口OA1设置在保护膜PRO1和PRO2的堆叠膜(堆叠绝缘膜)中，并且互连M1的部分从开口OA1的底部暴露。互连M1的这种暴露部分充当焊盘区PD。保护膜PRO3具有配置在开口OA1上并且尺寸大于开口OA1的开口OA2。
如同第一实施例，互连M1包括例如铝膜(Al膜)。保护膜PRO1包括例如氮化硅膜。保护膜PRO1上的保护膜PRO2包括例如氮氧化硅膜。尽管此处使用氮化硅膜和氮氧化硅膜作为保护膜PRO1和保护膜PRO2的组合，也可以使用其它组合。例如，只要能提供一定的刻蚀选择性，可以使用两种类型的绝缘膜的任何其他组合。例如，可使用氮氧化硅膜和氧化硅膜作为保护膜PRO1和保护膜PRO2的组合。保护膜PRO2上的保护膜PRO3包括例如聚酰亚胺膜。
如同第一实施例，将镀敷膜OPM1(例如，Ni膜)设置在作为开口OA1的底部的焊盘区PD的上方。如同第一实施例，将镀敷膜OPM2(例如，Au膜)设置在镀敷膜OPM1上方。
在第二实施例中，将狭缝(侧狭缝、凹陷)SL设置在保护膜PRO1和保护膜PRO2之间的边界处的开口OA1的侧面中。在图13中，将狭缝SL设置在开口OA1的侧面的中间部分中。狭缝SL可以是凹向开口OA1外部的侧面的一部分。将镀敷膜OPM1也设置在狭缝SL里。
以这种方式，将狭缝SL设置在开口OA1的侧面中，并且将镀敷膜OPM1也设置在狭缝SL里，使得可以改善镀敷膜OPM1和互连M1之间的电耦接。具体地，如参照第一实施例中的图2和3所描述的，可以抑制由镀敷溶液或清洗剂的渗透引起的腐蚀部分MC向焊盘区PD中的扩展。
在第二实施例中，如同第一实施例，设置在半导体衬底S的主表面上的半导体元件不特别地受限，并且可举例功率MOSFET作为半导体元件(见图4)。
制造方法的描述
现描述制造第二实施例的半导体装置的方法，同时进一步阐明半导体装置的配置。图14至23各是例示第二实施例的半导体装置的制造工艺的截面图。
首先，在半导体衬底S的主表面上形成半导体元件。例如，如同在第一实施例中(见图4)，形成功率MOSFET。具体地，设置包括缓冲层BUF和漂移层DRL的半导体衬底S，并且形成p型体区PB、n型发射极区NE和p型柱区PC。在半导体衬底S的上部中形成沟槽，并且在沟槽中的栅绝缘膜GOX上方形成栅电极GE。随后，在栅电极GE和类似物上方形成层间绝缘膜IL1，并且在层间绝缘膜IL1上形成包括Al膜的互连M1。
随后，如图14中所例示的，在互连M1上方形成保护膜PRO1和PRO2。例如，通过CVD工艺或类似工艺在层间绝缘膜IL1和互连M1上方淀积厚度约为0.5μm的氮化硅膜作为保护膜PRO1。随后，通过CVD工艺或类似工艺淀积厚度约为0.5μm的氮氧化硅膜作为保护膜PRO2。结果是，在互连M1上形成包括保护膜PRO1和PRO2的堆叠膜。
随后，去除互连M1(Al膜)的焊盘区PD上的堆叠膜(保护膜PRO1和PRO2)以形成开口OA1。例如，如图15中所例示的，在保护膜PRO2上方形成光致抗蚀剂膜PR1，并且通过曝光和显影去除开口OA1的形成区中的光致抗蚀剂膜PR1。随后，如图16中所例示的，使用光致抗蚀剂膜PR1作为掩模，干法刻蚀保护膜PRO2。即使在暴露下层保护膜PRO1以后，仍然进一步刻蚀保护膜PRO2，也就是保护膜PRO2被进行过刻蚀。
尽管干法刻蚀条件并未特别地受限，仍然示例性地执行干法刻蚀，该干法刻蚀在微波功率为800到1200W、压力为60到100Pa并且温度为60到100℃的环境下使用CF4和O2的混合气体作为刻蚀气体。干法刻蚀是各向同性刻蚀，因为半导体衬底不是偏置的。换言之，在干法刻蚀中各向同性分量大于各向异性分量。执行这样的各向同性干法刻蚀，并且此外执行过刻蚀。例如，过刻蚀的量约为80％。
通过这样的干法刻蚀暴露保护膜PRO1。此外，通过随后的过刻蚀在保护膜PRO2中形成底切，并且由此在保护膜PRO2的侧面的底部部分中形成狭缝SL。狭缝SL具有约1μm的长度。狭缝SL的长度优选为0.5到2.0μm。可通过过刻蚀的量来调整狭缝SL的长度。随后，通过灰化或类似方法去除光致抗蚀剂膜PR1(图17)。
随后，如图18所例示的，在保护膜PRO1和PRO2上方形成光致抗蚀剂膜PR2，并且通过曝光和显影去除开口OA1的形成区中的光致抗蚀剂膜PR2。在这种示例性情况下，光致抗蚀剂膜PR2具有尺寸小于保护膜PRO2的开口的开口。狭缝SL因此覆盖有光致抗蚀剂膜PR2并且由此能防止变形。如果狭缝SL能保持为预定的形状，光致抗蚀剂膜PR2的开口可以与保护膜PRO2的开口具有相同的尺寸。可以以保护膜PRO2作为掩模，刻蚀保护膜PRO1。随后，如图19中所例示的，使用光致抗蚀剂膜PR2作为掩模，干法刻蚀保护膜PRO1。
尽管干法刻蚀条件并未特别地受限，仍然示例性地执行干法刻蚀，该干法刻蚀在压力为4到10Pa并且温度为30到60℃的环境下使用CH3F、O2和Ar的混合气体作为刻蚀气体。在半导体衬底被偏置时执行干法刻蚀。例如，在如下的偏置条件下执行干法刻蚀：配置在作为半导体衬底S的安装架的台的上侧的上电极在60MHz下设置为800到1200W，而配置在台的下侧的下电极在2MHz下设置为100到500W。
用这种方式偏置半导体装置，增强了刻蚀离子朝着衬底方向的直线前进性能，导致各向异性提高。换言之，各向异性的分量变得比各向同性的分量更大。通过降低腔体中的压力可进一步提高各向异性。
因此，在一些可能的情况下，保护膜PRO2被进行具有相对较大的各向同性分量的干法刻蚀，而保护膜PRO1被进行具有相对较大的各向异性分量的干法刻蚀。
随后，通过灰化或类似方法去除光致抗蚀剂膜PR2(图20)。结果是，在包括保护膜PRO1和PRO2的堆叠膜中的开口OA1的侧壁的中间部分中形成狭缝SL。
随后，在保护膜PRO2上方形成保护膜PRO3。例如，形成聚酰亚胺膜作为保护膜PRO3。如图21中所例示的，将聚酰亚胺树脂施加到保护膜PRO2上并且将其固化，由此形成光敏聚酰亚胺膜。随后，如图22中所例示的，通过曝光和显影从开口OA2的形成区去除聚酰亚胺膜。结果是，可形成具有尺寸大于开口OA1的开口OA2的保护膜(聚酰亚胺膜)PRO3以重叠开口OA1。
随后，如图23中所例示的，在开口OA1中形成镀敷膜OPM1。例如，通过无电镀敷工艺形成Ni膜作为镀敷膜OPM1。在镀敷膜OPM1上方形成镀敷膜OPM2。例如，通过无电镀敷工艺形成Au膜作为镀敷膜OPM2。如在第一实施例中，可形成镀敷膜OPM1和镀敷膜OPM2。
以这种方式，在第二实施例中，将狭缝SL设置在开口OA1的侧面的中间部分中，并且镀敷膜(Ni膜)OPM1也生长在狭缝SL中。因此可以抑制腐蚀部分MC向互连(焊盘区PD)M1中的扩展。此外，将狭缝SL设置在开口OA1的侧面的中间部分中，由此增加了到另一个互连(M1)的距离，使得可以抑制互连之间的短路。
随后，减小半导体衬底S的厚度，并且形成背电极EL(见图4)，然后半导体衬底S被进行切割以形成单个的半导体芯片。
第三实施例
在第三实施例中，描述了一些应用。
第一应用
尽管在第一和第二实施例中已经举例功率MOSFET(图4)作为半导体元件，也可将如图24中所例示的n沟道MOSFET和p沟道MOSFET设置作为半导体元件。
图24和25各是例示第三实施例的第一应用的半导体装置的配置的截面图。在图24中，将n沟道MISFET和p沟道MISFET设置在半导体衬底S的主表面上。n沟道MISFIT包括形成在半导体衬底S上的栅电极GEn和其间的栅绝缘膜GI，以及形成在栅电极GEn的任一侧上的半导体衬底(p型阱PW)S中的n型半导体区Dn。n型半导体区Dn是具有包括低浓度半导体区和高浓度半导体区的LDD结构的源或漏区。p沟道MISFET包括形成在半导体衬底S上的栅电极GEp和其间的栅绝缘膜GI，以及形成在栅电极GEp的任一侧上的半导体衬底(n型阱NW)S中的p型半导体区Dp。p型半导体区Dp是具有包括低浓度半导体区和高浓度半导体区的LDD结构的源或漏区。将侧壁SW设置在栅电极GEp和GEn中的每个的两侧上。
在n沟道MISFET和p沟道MISFET上方设置层间绝缘膜IL1。在层间绝缘膜IL1中设置插塞P1。在层间绝缘膜IL1上的层间绝缘膜IL2中设置互连M1。在互连M1上方设置层间绝缘膜IL3，并且在层间绝缘膜IL3中设置插塞P2和互连M2。类似地，在层间绝缘膜IL4中设置插塞P3和互连M3，在层间绝缘膜IL5中设置插塞P4和互连M4，在层间绝缘膜IL6中设置插塞P5和互连M5。在层间绝缘膜IL6上的层间绝缘膜IL7中设置插塞P6。在层间绝缘膜IL7和插塞P6上设置互连M6。互连M6包括例如阻挡金属膜和Al膜的堆叠膜。在这种示例性情况下，互连M6是顶层互连。
如图25中所例示的，第一应用的半导体装置包括半导体衬底S、设置在半导体衬底S上的层间绝缘膜IL7和设置在层间绝缘膜IL7上的互连M6。设置n沟道MISFET和p沟道MISFET作为半导体衬底S的主表面中的半导体元件，并且在半导体元件之上设置多层互连(M1到M6)(图24)。例如，通过插塞和其它互连将互连M6电耦接到半导体元件(n沟道MISFET)。
互连M6包括例如阻挡金属膜M6a和Al膜M6b的堆叠膜。将每个都包括绝缘膜的保护膜PRO1和PRO2设置在互连M6上方。在保护膜PRO1中设置开口OA1，并且互连M6的部分从开口OA1的底部暴露。互连M6的这样的暴露部分充当焊盘区PD。保护膜PRO2具有配置在开口OA1上并且尺寸大于开口OA1的开口OA2。
如同第一实施例，保护膜PRO1包括例如氮氧化硅膜，而保护膜PRO2包括例如聚酰亚胺膜。
将镀敷膜OPM1(例如，Ni膜)设置在作为开口OA1的底部的焊盘区PD的上方。将镀敷膜OPM2(例如，Pd膜)设置在镀敷膜OPM1的上方。将镀敷膜OPM3(例如，Au膜)设置在镀敷膜OPM2的上方。
在第三实施例中，如同第一实施例，将狭缝(侧狭缝、凹陷)SL设置在开口OA1的侧面里。镀敷膜OPM1也设置在狭缝SL中。
用这种方式，将狭缝SL设置在开口OA1的侧面里，并且将镀敷膜OPM1也设置在狭缝SL里，使得可以改善镀敷膜OPM1和互连M1之间的电耦接。具体地，如参照第一实施例中的图2和3所描述的，使得可以抑制由镀敷溶液或清洗剂的渗透引起的腐蚀部分MC向焊盘区PD中的扩展。
现描述第三实施例的半导体装置的制造工艺。尽管n沟道MISFET、p沟道MISFET和MISFET之上的多层互连(M1到M6)的形成工艺并非特别地受限，以下仍参照图24简要描述示例性形成工艺。
在半导体衬底S的每个元件隔离区中形成沟槽，并且沟槽的内部填充有绝缘膜，由此形成隔离部分STI。随后，具有p型导电性的杂质被离子注入到半导体衬底S中以形成p型阱PW，而具有n型导电性的杂质被离子注入到半导体衬底S中以形成n型阱NW。随后，在半导体衬底S上形成栅绝缘膜GI以及栅电极GEn和GEp。例如，通过CVD工艺形成氧化硅膜作为栅绝缘膜GI，并且通过CVD工艺在氧化硅膜上形成多晶硅膜。随后，多晶硅膜被图案化以形成栅电极GE。
随后，具有n型导电性的杂质被离子注入到栅电极GEn的任一侧上的p型阱PW中并且由此形成低浓度杂质区。具有p型导电性的杂质被离子注入到栅电极GEp的任一侧上的n型阱NW中并且由此形成低浓度杂质区。随后，在栅电极GEn和栅电极GEp的每个侧壁上形成侧壁SW。
随后，具有n型导电性的杂质被离子注入到栅电极GEn的任一侧上的p型阱PW中并且由此形成高浓度杂质区。具有p型导电性的杂质被离子注入到栅电极GEp的任一侧上的n型阱NW中并且由此形成高浓度杂质区。以这种方式，形成各自充当源或漏的n型半导体区Dn和p型半导体区Dp。
随后，在半导体衬底S上的n沟道MISFET和p沟道MISFET上方形成层间绝缘膜IL1，然后在层间绝缘膜IL1中形成接触孔C1。随后，用例如钨(W)填充接触孔C1的内部并且由此形成插塞P1。随后，在插塞P1上方形成具有互连沟槽的层间绝缘膜IL2，并且，例如，每个互连沟槽的内部都填充有Cu。以这种方式，形成互连M1(单镶嵌工艺)。例如，层间绝缘膜IL2包括薄氮化硅膜和氮化硅膜上的氧化硅膜的堆叠膜(对于IL3到IL6也同样)。
此外，形成第二层互连M2到第五层互连M5。通过称作双镶嵌的工艺形成互连M2到M5。例如，在层间绝缘膜IL2上形成层间绝缘膜IL3，并且层间绝缘膜IL3中形成接触孔C2和互连沟槽。接触孔C2和互连沟槽填充有Cu，并且由此同时形成插塞P2和互连M2。类似地，形成层间绝缘膜IL4、插塞P3和互连M3，然后形成层间绝缘膜IL5、插塞P4和互连M4，然后形成层间绝缘膜IL6、插塞P5和互连M5。
随后，在互连M5上方形成包括氧化硅膜的层间绝缘膜IL7。随后，处理层间绝缘膜IL7以形成接触孔C6。每个接触孔C5的内部填充有例如W，由此形成每个插塞P6。
随后，在层间绝缘膜IL7上形成阻挡金属膜M6a，并且在其上形成Al膜M6b。阻挡金属膜包括例如Ti膜、TiN膜或Ti膜和TiN膜的堆叠膜。这样的膜(M6a和M6b)被图案化以形成互连M6。
随后，如在第一实施例中，在互连M6上方形成保护膜PRO1，并且通过干法刻蚀从互连M1(Al膜)的焊盘区PD去除保护膜PRO1，由此形成开口OA1。焊盘区PD中的互连M6(Al膜)通过这样的干法刻蚀暴露。此外，通过随后的过刻蚀形成底切，并且因此在开口OA1的侧面的底部部分中形成狭缝SL。随后，如在第一实施例中，形成具有开口OA2的保护膜(聚酰亚胺膜)PRO2。
随后，在开口OA1中顺序地形成镀敷膜OPM1、OPM2和OPM3。例如，通过无电镀敷工艺形成Ni膜作为镀敷膜OPM1。随后，在镀敷膜OPM1上方形成镀敷膜OPM2。例如，通过无电镀敷工艺形成钯(Pd)膜作为镀敷膜OPM2。随后，在镀敷膜OPM2上方形成镀敷膜OPM3。例如，通过无电镀敷工艺形成Au膜作为镀敷膜OPM3。以这种方式，三层金属膜可用作焊盘上方的金属。
以这种方式，在第三实施例中，在开口OA1的侧面中设置狭缝SL，并且在狭缝SL中生长镀敷膜(Ni膜)OPM1。由此可以抑制腐蚀部分MC向互连(焊盘区PD)M1中的扩展。
第二应用
可在第一实施例中所描述的镀敷膜OPM2上设置接合导线BW。
图26是例示第三实施例的第二应用的半导体装置的配置的截面图。
例如，如第一实施例中所描述的，半导体衬底S被进行切割以形成单个的半导体芯片。随后，用膏状粘合剂(例如，银(Ag)膏)或类似物将半导体芯片接合到引线框架的管芯焊盘上。随后，通过接合导线BW将焊盘区PD耦接到引线(导线接合)。例如，通过电弧放电将Cu导线的一端熔化成球形，并且通过热压将该球接合到镀敷膜OPM2上。将Cu导线的另一端通过热压接合到引线的顶部。
可在第二实施例和第一应用中的每个中所描述的镀敷膜(OPM2或OPM3)上设置接合导线BW。
第三应用
可在第一实施例中所描述的镀敷膜OPM2上执行夹片接合。
图27是例示第三实施例的第三应用的半导体装置的配置的截面图。
例如，如第一实施例中所描述的，半导体衬底S被进行切割以形成单个的半导体芯片。随后，可将半导体芯片固定到夹片CR上。例如，将焊料膏BP配置在镀敷膜OPM3上。随后，用金属框架CR(诸如铜框架)，也就是通过称为夹片接合的方法，将镀敷膜OPM3电耦接到焊料膏BP。
尽管没有示出，当在半导体衬底S的背侧上设置背电极(见图4)时，例如，可通过焊料膏将半导体衬底S的背侧电耦接到芯片安装架框架或类似物。
可在第二实施例和第一应用之一中所描述的镀敷膜(OPM2或OPM3)上执行使用金属框架CR的夹片接合。
第四应用
图28是例示第三实施例的第四应用的半导体装置的配置的截面图。尽管在第一应用中作为顶层互连的互连M6具有包括阻挡金属膜M6a和阻挡金属膜M6a上的Al膜M6b的两层结构(图25)，作为顶层互联的互连M6也可以具有三层结构，该三层结构包括阻挡金属膜M6a、Al膜M6b和阻挡金属膜M6c。
在这样的情况下，在去除顶层阻挡金属膜M6c以后，形成镀敷膜(OPM1、OPM2、OPM3)。例如，使用光致抗蚀剂膜作为掩模，干法刻蚀保护膜PRO1。即使在互连M6暴露以后，仍进一步刻蚀保护膜PRO1，也就是保护膜PRO1被进行过刻蚀。以这种方式，在暴露互连M6以后执行过刻蚀，由此可在开口OA1的侧面的底部部分中形成狭缝SL(见图25)。随后，去除作为互连M6的顶部的阻挡金属膜M6c以暴露Al膜M6b，并且在Al膜M6b上方形成镀敷膜OPM1和类似物。
尽管前文中由本发明人实现的发明已根据它的一些实施例详细描述，但是本发明不应受限于此，并且将认识到可以在不脱离本发明的要旨的范围内作出它的各种修改或替代。

Claims (20)

1.一种半导体装置，包括：
第一绝缘膜，所述第一绝缘膜设置在半导体衬底之上；
第一互连，所述第一互连设置在所述第一绝缘膜上方；
第二绝缘膜，所述第二绝缘膜设置在所述第一互连上方并且具有第一开口；
镀敷膜，所述镀敷膜设置在所述第一开口中；以及
狭缝，所述狭缝设置在所述第一开口的侧面中，
其中所述第一开口的底部是焊盘区，所述焊盘区是第一互连的部分，并且
其中所述镀敷膜还设置在所述狭缝中。
2.根据权利要求1所述的半导体装置，
其中所述第一互连包含铝(Al)，并且
其中所述镀敷膜包含从镍(Ni)、金(Au)和钯(Pd)中选出的金属。
3.根据权利要求2所述的半导体装置，
其中所述第一互连包含铝(Al)，并且
其中所述镀敷膜包括包含镍(Ni)的第一镀敷膜和设置在所述第一镀敷膜上并且包含金(Au)的第二镀敷膜。
4.根据权利要求3所述的半导体装置，进一步包括在所述第一镀敷膜和所述第二镀敷膜之间的包含钯(Pd)的第三镀敷膜。
5.根据权利要求1所述的半导体装置，进一步包括设置在所述镀敷膜上方的接合导线和金属框架之一。
6.根据权利要求1所述的半导体装置，进一步包括设置在所述第二绝缘膜上方并且具有在所述第一开口上方的第二开口的第三绝缘膜。
7.根据权利要求6所述的半导体装置，其中所述第二绝缘膜是从氮化硅膜、氮氧化硅膜和氧化硅膜中选出的膜。
8.根据权利要求7所述的半导体装置，其中所述第三绝缘膜是聚酰亚胺膜。
9.一种半导体装置，包括：
第一绝缘膜，所述第一绝缘膜设置在半导体衬底之上；
第一互连，所述第一互连设置在所述第一绝缘膜上方；
堆叠绝缘膜，所述堆叠绝缘膜设置在所述第一互连上方并且具有第一开口；
镀敷膜，所述镀敷膜设置在所述第一开口中；以及
狭缝，所述狭缝设置在所述第一开口的侧面中；
其中所述第一开口的底部是焊盘区，所述焊盘区是所述第一互连的部分，
其中所述堆叠绝缘膜包括设置在所述第一互连上方的第一膜和设置在所述第一膜上方的第二膜，
其中所述狭缝设置在所述第一膜和所述第二膜之间的边界处，并且
其中所述镀敷膜还设置在所述狭缝中。
10.一种制造半导体装置的方法，所述方法包括如下步骤：
(a)在半导体衬底之上形成第一绝缘膜；
(b)在所述第一绝缘膜上方形成第一互连；
(c)在所述第一互连上方形成第二绝缘膜；
(d)去除所述第一互连上方的所述第二绝缘膜，由此形成暴露焊盘区的第一开口，所述焊盘区是所述第一互连的部分；以及
(e)在步骤(d)之后，在所述焊盘区上方形成镀敷膜，
其中在步骤(d)中，在所述第一开口的侧面中形成狭缝，并且
其中在步骤(e)中，在所述狭缝中形成所述镀敷膜。
11.根据权利要求10所述的方法，其中步骤(d)是通过干法刻蚀去除所述第二绝缘膜的步骤。
12.根据权利要求11所述的方法，其中步骤(d)中的所述干法刻蚀包括在暴露所述焊盘区之后执行的过刻蚀。
13.根据权利要求10所述的方法，
其中所述第一互连包含铝(Al)，并且
其中所述镀敷膜包含从镍(Ni)、金(Au)和钯(Pd)中选出的金属。
14.根据权利要求10所述的方法，
其中所述第一互连包含铝(Al)，并且
其中步骤(e)是在所述焊盘区上方形成包含镍(Ni)的第一镀敷膜以及在所述第一镀敷膜上方形成包含金(Au)的第二镀敷膜的步骤。
15.根据权利要求10所述的方法，
其中所述第一互连包含铝(Al)，并且
其中步骤(e)是在所述焊盘区上方形成包含镍(Ni)的第一镀敷膜、在所述第一镀敷膜上方形成包含钯(Pd)的第二镀敷膜以及在所述第二镀敷膜上方形成包含金(Au)的第三镀敷膜的步骤。
16.根据权利要求10所述的方法，进一步包括如下步骤：
(f)在所述镀敷膜上方设置接合导线和金属框架之一。
17.根据权利要求10所述的方法，进一步包括如下步骤：
在步骤(d)和步骤(e)之间，
(g)在所述第二绝缘膜上方形成第三绝缘膜；以及
(h)在所述第三绝缘膜中形成第二开口，
其中步骤(h)中的所述第二开口形成在所述第一开口上方。
18.根据权利要求17所述的方法，其中所述第二绝缘膜是从氮化硅膜、氮氧化硅膜和氧化硅膜中选出的膜，并且所述第三绝缘膜是聚酰亚胺膜。
19.一种制造半导体装置的方法，所述方法包括如下步骤：
(a)在半导体衬底之上形成第一绝缘膜；
(b)在所述第一绝缘膜上方形成第一互连；
(c)在所述第一互连上方形成第二绝缘膜和第三绝缘膜的堆叠膜；
(d)去除所述第一互连上方的所述堆叠膜，由此形成暴露焊盘区的第一开口，所述焊盘区是所述第一互连的部分；以及
(e)在步骤(d)之后，在所述焊盘区上方形成镀敷膜，
其中在步骤(d)中，在所述第二绝缘膜和所述第三绝缘膜之间的边界处的所述第一开口的侧面中形成狭缝，并且
其中在步骤(e)中，在所述狭缝中形成所述镀敷膜。
20.根据权利要求19所述的方法，
其中所述第二绝缘膜是氮化硅膜，并且所述第三绝缘膜是氮氧化硅膜，
其中步骤(d)包括如下步骤：
(d1)通过干法刻蚀去除所述第三绝缘膜，并且
其中步骤(d1)包括在暴露所述第二绝缘膜之后执行的过刻蚀。
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