CN106469701A - 半导体器件结构及其形成方法 - Google Patents

半导体器件结构及其形成方法 Download PDF

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Publication number
CN106469701A
CN106469701A CN201610595263.0A CN201610595263A CN106469701A CN 106469701 A CN106469701 A CN 106469701A CN 201610595263 A CN201610595263 A CN 201610595263A CN 106469701 A CN106469701 A CN 106469701A
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layer
semiconductor device
device structure
wiring layer
dielectric layer
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CN106469701B (zh
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杨明宪
王俊智
杨敦年
洪丰基
黄信耀
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了半导体器件结构。该半导体器件结构包括具有第一表面、第二表面和凹槽的第一半导体衬底。第二表面与第一表面相对。该凹槽穿过第一半导体衬底。该半导体器件结构包括位于第二表面上方的第一布线层。该半导体器件结构包括第一接合焊盘，该第一接合焊盘位于凹槽中并且延伸至第一布线层以电连接至第一布线层。该半导体器件结构包括位于第一接合焊盘上方的镍层。该半导体器件结构包括位于镍层上方的金层。本发明的实施例还涉及半导体器件结构的形成方法。

Description

半导体器件结构及其形成方法
相关申请的交叉引用
本申请要求2015年8月14日提交的美国临时申请第62/205,526号的权益，其全部内容结合于此作为参考。
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及半导体器件结构及其形成方法。
背景技术
半导体集成电路(IC)工业已经经历了快速增长。IC材料和设计中的技术进步已经产生了多代IC。每一代都比上一代具有更小和更复杂的电路。然而，这些进步已经增加了处理和制造IC的复杂性。
在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，可以使用制造工艺产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。
然而，由于部件尺寸不断减小，制造工艺不断地变得更加难以实施。因此，形成尺寸越来越小的可靠的半导体器件是一个挑战。
发明内容
本发明的实施例提供了一种半导体器件结构，包括：第一半导体衬底，具有第一表面、第二表面和凹槽，其中，所述第二表面与所述第一表面相对，并且所述凹槽穿过所述第一半导体衬底；第一布线层，位于所述第二表面上方；第一接合焊盘，位于所述凹槽中并且延伸至所述第一布线层以电连接至所述第一布线层；镍层，位于所述第一接合焊盘上方；以及金层，位于所述镍层上方。
本发明的另一实施例提供了一种半导体器件结构，包括：第一半导体衬底，具有表面和凹槽，其中，所述凹槽穿过所述第一半导体衬底；第一布线层，位于所述表面上方；镍层，位于所述凹槽中并且延伸至所述第一布线层以电连接至所述第一布线层；以及金层，位于所述镍层上方。
本发明的又一实施例提供了一种用于形成半导体器件结构的方法，包括：提供具有表面的第一半导体衬底；在所述表面上方形成第一布线层；在所述第一半导体衬底中形成凹槽，其中，所述凹槽穿过所述第一半导体衬底以暴露所述第一布线层；在所述凹槽中形成第一接合焊盘，其中，所述第一接合焊盘延伸至所述第一布线层以电连接至所述第一布线层；在所述第一接合焊盘上方形成镍层；以及在所述镍层上方形成金层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1L是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图1L-1是根据一些实施例的图1L的接合焊盘、镍层和金层的顶视图。
图1L-2是根据一些实施例的图1L的接合焊盘、镍层和金层的顶视图。
图1L-3是根据一些实施例的图1L的接合焊盘、镍层和金层的顶视图。
图2是根据一些实施例的半导体器件结构的截面图。
图3是根据一些实施例的半导体器件结构的截面图。
图4是根据一些实施例的半导体器件结构的截面图。
图5A至图5B是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图6是根据一些实施例的半导体器件结构的截面图。
图7是根据一些实施例的半导体器件结构的截面图。
图8是根据一些实施例的半导体器件结构的截面图。
图9是根据一些实施例的半导体器件结构的截面图。
图10是根据一些实施例的半导体器件结构的截面图。
图11是根据一些实施例的半导体器件结构的截面图。
图12是根据一些实施例的半导体器件结构的截面图。
图13是根据一些实施例的半导体器件结构的截面图。
图14是根据一些实施例的半导体器件结构的截面图。
图15是根据一些实施例的半导体器件结构的截面图。
图16是根据一些实施例的半导体器件结构的截面图。
图17是根据一些实施例的半导体器件结构的截面图。
图18A是根据一些实施例的半导体器件结构的截面图。
图18B是根据一些实施例的图18A的半导体器件结构的镍层、导电环结构以及部分布线层的顶视图。
图19是根据一些实施例的半导体器件结构的截面图。
图20是根据一些实施例的半导体器件结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。应该理解，可以在方法之前、期间和之后提供额外的操作，并且对于方法的其它实施例，可以替换或消除所描述的一些操作。
图1A至图1L是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
如图1A所示，根据一些实施例，提供了半导体衬底110。根据一些实施例，半导体衬底110具有彼此相对的表面112和114。根据一些实施例，半导体衬底110是半导体晶圆(诸如硅晶圆)或部分半导体晶圆。
在一些实施例中，半导体衬底110由包括单晶、多晶或非晶结构的硅或锗的元素半导体材料制成。在一些其它实施例中，半导体衬底110由诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟的化合物半导体；诸如SiGe或GaAsP的合金半导体；或它们的组合制成。半导体衬底110也可以包括多层半导体、绝缘体上半导体(SOI)(诸如绝缘体上硅或绝缘体上锗)或它们的组合。
如图1A所示，根据一些实施例，表面114具有凹槽114a。如图1A所示，根据一些实施例，在凹槽114a中形成绝缘层10。根据一些实施例，绝缘层10填充在凹槽114a中。
根据一些实施例，绝缘层10由诸如氢化碳氧化硅(SiCO:H)、氮氧化硅、氧化硅、硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化的硅酸盐玻璃(FSG)、低k材料、多孔介电材料或它们的组合的任何合适的绝缘材料制成。
如图1A所示，根据一些实施例，在表面114和绝缘层10上方沉积介电层120。根据一些实施例，介电层120是多层结构。根据一些实施例，介电层120包括彼此堆叠的介电层(未示出)。
根据一些实施例，介电层120由诸如氢化碳氧化硅(SiCO:H)、氮氧化硅、氧化硅、硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化的硅酸盐玻璃(FSG)、低k材料、多孔介电材料或它们的组合的任何合适的介电材料制成。根据一些实施例，通过诸如CVD工艺、HDPCVD工艺、旋涂工艺、溅射工艺或它们的组合的任何合适的工艺沉积介电层120。
如图1A所示，根据一些实施例，在介电层120中形成布线层132和134。在一些实施例中，布线层136嵌入在介电层120内。根据一些实施例，布线层136由介电层120暴露。布线层132、134和136由诸如铜、铜合金、银、金、铝或它们的组合的任何合适的导电材料制成。
如图1A所示，根据一些实施例，在介电层120中形成导电通孔结构142和144。根据一些实施例，导电通孔结构142将布线层132电连接至布线层134。根据一些实施例，导电通孔结构144将布线层134电连接至布线层136。
如图1B所示，根据一些实施例，翻转半导体衬底110。如图1B所示，根据一些实施例，提供了半导体衬底250。根据一些实施例，半导体衬底250是半导体晶圆(诸如硅晶圆)或部分半导体晶圆。在一些实施例中，半导体衬底250由包括单晶、多晶或非晶结构的硅或锗的元素半导体材料制成。
在一些其它实施例中，半导体衬底250由诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟的化合物半导体；诸如SiGe或GaAsP的合金半导体；或它们的组合制成。半导体衬底250也可以包括多层半导体、绝缘体上半导体(SOI)(诸如绝缘体上硅或绝缘体上锗)或它们的组合。
如图1B所示，根据一些实施例，在半导体衬底250上方沉积介电层260。根据一些实施例，介电层260是多层结构。根据一些实施例，介电层260包括彼此堆叠的介电层(未示出)。
根据一些实施例，介电层260由诸如氢化碳氧化硅(SiCO:H)、氮氧化硅、氧化硅、硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化的硅酸盐玻璃(FSG)、低k材料、多孔介电材料或它们的组合的任何合适的介电材料制成。根据一些实施例，通过诸如CVD工艺、HDPCVD工艺、旋涂工艺、溅射工艺或它们的组合的任何合适的工艺沉积介电层260。
如图1B所示，根据一些实施例，在介电层260中形成布线层272、274和276。在一些实施例中，布线层278嵌入在介电层260内。根据一些实施例，布线层278由介电层260暴露。布线层272、274、276和278由诸如铜、铜合金、银、金、铝或它们的组合的任何合适的导电材料制成。
如图1B所示，根据一些实施例，在介电层260中形成导电通孔结构282、284和286。根据一些实施例，导电通孔结构282将布线层272电连接至布线层274。根据一些实施例，导电通孔结构284将布线层274电连接至布线层276。
根据一些实施例，导电通孔结构286将布线层276电连接至布线层278。根据一些实施例，半导体衬底250、介电层260、布线层272、274、276和278以及导电通孔结构282、284和286一起形成布线衬底S。
如图1B所示，根据一些实施例，介电层260和120彼此接合。根据一些实施例，布线层278和136彼此接合。根据一些实施例，布线层278和136彼此电连接。
如图1B所示，根据一些实施例，在表面112上方形成介电层150。根据一些实施例，介电层150是透明层。根据一些实施例，介电层150包括高k材料。根据一些实施例，介电层150包括氧化物和/或氮化物。
根据一些实施例，介电层150包括氧化硅、氮化硅和/或氮氧化硅。根据一些实施例，通过诸如CVD工艺、HDPCVD工艺、旋涂工艺、溅射工艺或它们的组合的任何合适的工艺形成介电层150。
如图1C所示，根据一些实施例，去除部分介电层150和半导体衬底110。根据一些实施例，在去除工艺之后，形成了开口152和凹槽116。根据一些实施例，开口152穿过介电层150。
根据一些实施例，凹槽116形成在半导体衬底110中并且从表面112凹进。根据一些实施例，凹槽116穿过半导体衬底110。根据一些实施例，凹槽116暴露了部分绝缘层10。在一些实施例中，去除工艺包括光刻工艺和蚀刻工艺。
如图1C所示，根据一些实施例，在介电层150上方形成绝缘层160以覆盖开口152的侧壁152a以及凹槽116的侧壁116a和底面116b。根据一些实施例，绝缘层160与绝缘层10直接接触。根据一些实施例，绝缘层160包括诸如氧化硅的氧化物。
如图1D所示，根据一些实施例，去除部分绝缘层160、部分绝缘层10和部分介电层120。根据一些实施例，在去除工艺之后，形成了开口162和通孔10a。根据一些实施例，开口162穿过绝缘层160。根据一些实施例，通孔10a穿过绝缘层10并且穿透至介电层120以暴露布线层132。去除工艺包括光刻工艺和蚀刻工艺。
如图1E所示，根据一些实施例，接合焊盘180形成在凹槽116的底面116b上方并且延伸至通孔10a以电连接至布线层132。根据一些实施例，接合焊盘180包括导电材料。根据一些实施例，接合焊盘180包括铝或铜。根据一些实施例，使用物理汽相沉积工艺、光刻工艺和蚀刻工艺形成接合焊盘180。
如图1F所示，根据一些实施例，去除介电层150的顶面154上方的绝缘层160。根据一些实施例，削薄位于凹槽116和开口152中并且由接合焊盘180暴露的绝缘层160。根据一些实施例，绝缘层160的去除和削薄包括各向异性蚀刻工艺。根据一些实施例，各向异性蚀刻工艺包括干蚀刻工艺。
如图1G所示，根据一些实施例，在凹槽116、开口152和通孔10a中形成介电填充层190。根据一些实施例，介电填充层190填充至凹槽116、开口152和通孔10a。根据一些实施例，介电填充层190的形成包括沉积工艺和化学机械抛光工艺。介电填充层190包括氧化物(例如，氧化硅)或另一合适的介电材料。
如图1H所示，根据一些实施例，在介电层150的顶面154上方形成不透明层210。根据一些实施例，不透明层210具有光阻断部分212和网格部分214。根据一些实施例，光阻断部分212配置为阻止光到达半导体衬底110上方或中的感光元件(例如，光电二极管)。根据一些实施例，网格部分214配置为引导光朝向半导体衬底110上方或中的感光元件(例如，光电二极管)。
如图1I所示，根据一些实施例，去除位于网格部分214之间或位于网格部分214和光阻断部分212之间的部分介电层150。根据一些实施例，去除工艺在介电层150中并且在网格部分214之间或在网格部分214和光阻断部分212之间形成凹槽156。
在一些实施例中，根据一些实施例，在不透明层210、介电层150、绝缘层160和介电填充层190上方形成钝化层(未示出)。根据一些实施例，钝化层包括绝缘材料。
如图1J所示，根据一些实施例，去除部分介电填充层190。根据一些实施例，去除工艺在介电填充层190中形成开口192。根据一些实施例，开口192暴露了底面116b(或绝缘层10)上方的接合焊盘180。
如图1K所示，根据一些实施例，在接合焊盘180上方形成镍层230。根据一些实施例，镍层230包含主要成分镍。根据一些实施例，镍层230包含重量分数至少60％的镍。根据一些实施例，镍层230包含重量分数至少80％的镍。
根据一些实施例，镍层230位于开口192中。根据一些实施例，全部的镍层230位于开口192中。根据一些实施例，镍层230没有在开口192的外侧延伸。根据一些实施例，镍层230是基本平坦的层。
根据一些实施例，使用化学镀工艺形成镍层230。根据一些实施例，化学镀工艺能够选择性地在金属层(即，接合焊盘180)上方沉积镍层230。因此，根据一些实施例，没有使用光刻工艺和蚀刻工艺形成镍层230。
如图1L所示，根据一些实施例，在镍层230上方形成金层240。根据一些实施例，金层240包含主要成分金。根据一些实施例，金层240包含重量分数至少60％的金。根据一些实施例，金层240包含重量分数至少80％的金。
根据一些实施例，使用浸镀工艺形成金层240。根据一些实施例，金层240和镍层230没有延伸至表面112。根据一些实施例，全部的金层240和全部的镍层230位于开口192中。根据一些实施例，镍层230的厚度T1大于金层240的厚度T2。
根据一些实施例，接合焊盘180的材料与镍层230和金层240的材料不同。由于镍的杨氏模量大于接合焊盘180的材料(例如，铜或铝)的杨氏模量，因此在相同的正应力下，镍的正应变小于接合焊盘180的材料(例如，铜或铝)的正应变。
因此，在随后实施的引线拉力试验或球剪切试验期间，镍层230的形成防止接合焊盘180的剥离。由于金的硬度小于镍的硬度，因此，金层240缓冲了由随后实施的引线接合工艺或球接合工艺产生的接合应力。在这个步骤中，根据一些实施例，基本形成了半导体器件结构100。
在顶视图中，接合焊盘180可以具有不同的形状，并且仅在由开口192暴露的接合焊盘180上方形成镍层230和金层240。图1L-1、图1L-2和图1L-3示出了具有不同形状的接合焊盘180的实例。
图1L-1是根据一些实施例的图1L的接合焊盘180、镍层230和金层240的顶视图。图1L是根据一些实施例的示出沿着图1L-1中的剖面线I-I的接合焊盘180、镍层230和金层240的截面图。如图1L和图1L-1所示，接合焊盘180具有岛状形状，并且在接合焊盘180上方形成镍层230和金层240。
图1L-2是根据其它实施例的图1L的接合焊盘180、镍层230和金层240的顶视图。图1L是根据一些实施例的示出沿着图1L-2中的剖面线I-I的接合焊盘180、镍层230和金层240的截面图。如图1L和图1L-2所示，根据一些实施例，接合焊盘180具有彼此间隔开的条状部分182。根据一些实施例，在条状部分182上方形成镍层230和金层240。
图1L-3是根据又其它实施例的图1L的接合焊盘180、镍层230和金层240的顶视图。图1L是根据一些实施例的示出沿着图1L-3中的剖面线I-I的接合焊盘180、镍层230和金层240的截面图。如图1L和图1L-3所示，根据一些实施例，接合焊盘180具有环状。根据一些实施例，在接合焊盘180上方形成镍层230和金层240。
图2是根据一些实施例的半导体器件结构的截面图。如图2所示，根据一些实施例，半导体器件结构100还包括钯层290。根据一些实施例，在镍层230和金层240之间形成钯层290。根据一些实施例，使用化学镀工艺形成钯层290。
在一些实施例中，钯具有类似于金的物理性质并且比金便宜。因此，根据一些实施例，钯层290的形成减小了用于形成金层240的金的量。因此，根据一些实施例，钯层290的形成减小了半导体器件结构100的制造成本。
图3是根据一些实施例的半导体器件结构的截面图。如图3所示，根据一些实施例，半导体器件结构100还包括将金层240连接至接合焊盘320的导线310。导线310包括金、铝或另一合适的导电材料。在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。
衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
图4是根据一些实施例的半导体器件结构的截面图。如图4所示，根据一些实施例，半导体器件结构100还包括位于金层240上方的导电凸块410。根据一些实施例，导电凸块410电连接至金层240。根据一些实施例，导电凸块410包括导电材料。根据一些实施例，导电凸块410包括诸如锡(Sn)和铜(Cu)的焊接材料。
在一些实施例中，半导体器件结构100没有结合焊盘180，并且以下示例性地示出了详细地描述。
图5A至图5B是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。如图5A所示，根据一些实施例，在图1B的步骤之后，去除部分介电层150和部分半导体衬底110。根据一些实施例，在去除工艺之后，形成了开口152和凹槽116。
根据一些实施例，开口152穿过介电层150。根据一些实施例，凹槽116形成在半导体衬底110中并且从表面112凹进。根据一些实施例，凹槽116穿过半导体衬底110。根据一些实施例，凹槽116暴露了部分绝缘层10。在一些实施例中，去除工艺包括光刻工艺和蚀刻工艺。
如图5A所示，根据一些实施例，在开口152和凹槽116中形成绝缘层160。根据一些实施例，绝缘层160与绝缘层10直接接触。根据一些实施例，绝缘层160包括诸如氧化硅的氧化物。
如图5A所示，根据一些实施例，实施图1H至图1I的步骤以形成不透明层210和凹槽156。根据一些实施例，在介电层150的顶面154上方形成不透明层210。
根据一些实施例，不透明层210具有光阻断部分212和网格部分214。如图5A所示，根据一些实施例，在介电层150中和在网格部分214之间或在网格部分214和光阻断部分212之间形成凹槽156。
如图5B所示，根据一些实施例，去除部分绝缘层160和10以及部分介电层120。根据一些实施例，在去除工艺之后，形成了孔H和开口122。根据一些实施例，孔H穿过绝缘层160和10。
根据一些实施例，开口122位于介电层120中和凹槽116下方。根据一些实施例，开口122连接至孔H。根据一些实施例，开口122和孔H一起暴露了部分布线层132。去除工艺包括光刻工艺和蚀刻工艺。
如图5B所示，根据一些实施例，在孔H和开口122中形成镍层230。根据一些实施例，开口122填充有镍层230。根据一些实施例，孔H部分地填充有镍层230。在一些其它实施例中，根据一些实施例，孔H填充有镍层230。
根据一些实施例，镍层230电连接至布线层132。根据一些实施例，镍层230与布线层132直接接触。根据一些实施例，镍层230与绝缘层160和10以及介电层120直接接触。
根据一些实施例，使用化学镀工艺形成镍层230。根据一些实施例，镍层230包含主要成分镍。根据一些实施例，镍层230包含质量分数至少60％的镍。根据一些实施例，镍层230包含质量分数至少80％的镍。
如图5B所示，根据一些实施例，在镍层230上方形成金层240。根据一些实施例，金层240包含主要成分金。根据一些实施例，金层240包含质量分数至少60％的金。
根据一些实施例，金层240包含质量分数至少80％的金。根据一些实施例，使用浸镀工艺形成金层240。根据一些实施例，金层240和镍层230没有延伸至表面112。根据一些实施例，在这个步骤中，基本形成了半导体器件结构500。
图6是根据一些实施例的半导体器件结构的截面图。如图6所示，根据一些实施例，半导体器件结构500还包括钯层290。根据一些实施例，在镍层230和金层240之间形成钯层290。根据一些实施例，钯层290与绝缘层160直接接触。根据一些实施例，使用化学镀工艺形成钯层290。
图7是根据一些实施例的半导体器件结构的截面图。如图7所示，根据一些实施例，半导体器件结构500还包括将金层240连接至接合焊盘320的导线310。根据一些实施例，导线310与金层240和接合焊盘320直接接触。在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。
衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
图8是根据一些实施例的半导体器件结构的截面图。如图8所示，根据一些实施例，半导体器件结构500还包括位于金层240上方的导电凸块410。根据一些实施例，导电凸块410电连接至金层240。
根据一些实施例，导电凸块410与金层240直接接触。根据一些实施例，导电凸块410包括导电材料。根据一些实施例，导电凸块包括诸如锡(Sn)和铜(Cu)的焊接材料。
图9是根据一些实施例的半导体器件结构的截面图。如图9所示，根据一些实施例，除了半导体器件结构900还包括介电层910、钝化层920、介电层930、钝化层940、绝缘层950和导电通孔结构960之外，半导体器件结构900类似于图1L的半导体器件结构100。
根据一些实施例，在介电层120和布线层136上方形成介电层910。根据一些实施例，介电层910和120具有相同的材料。根据一些实施例，在介电层910上方形成钝化层920。根据一些实施例，钝化层920包括氧化物(例如，氧化硅)或氮化物。
根据一些实施例，布线衬底S还包括介电层930和钝化层940。根据一些实施例，在布线层278和介电层260上方形成介电层930。
根据一些实施例，介电层930和260具有相同的材料。根据一些实施例，在介电层930上方形成钝化层940。根据一些实施例，钝化层940包括氧化物(例如，氧化硅)或氮化物。根据一些实施例，钝化层920和940彼此接合。
如图9所示，根据一些实施例，孔H1穿过介电层150、半导体衬底110和绝缘层10。根据一些实施例，孔H1暴露了部分介电层120。如图9所示，根据一些实施例，在孔H1的内壁W1上方形成绝缘层950。根据一些实施例，绝缘层950包括诸如氧化硅的氧化物。
如图9所示，根据一些实施例，孔H2穿过介电层120。如图9所示，根据一些实施例，布线层136具有位于孔H1和布线层278之间的开口136a。
如图9所示，根据一些实施例，孔H3穿过介电层910、钝化层920、介电层930和钝化层940。根据一些实施例，孔H1、H2和H3以及开口136a一起暴露了部分布线层278。根据一些实施例，孔H1、H2和H3以及开口136a彼此连通(或连接)。
根据一些实施例，在孔H1、H2和H3以及开口136a中形成导电通孔结构960。根据一些实施例，孔H1、H2和H3以及开口136a填充有导电通孔结构960。根据一些实施例，导电通孔结构960依次穿过介电层150、半导体衬底110、绝缘层10、介电层120、介电层910、钝化层920、钝化层940和介电层930。
根据一些实施例，导电通孔结构960将布线层136电连接至布线层278。根据一些实施例，导电通孔结构960包括导电材料。导电材料包括钨、铝、铜或另一合适的导电材料。
图10是根据一些实施例的半导体器件结构的截面图。如图10所示，根据一些实施例，半导体器件结构900还包括钯层290。根据一些实施例，在镍层230和金层240之间形成钯层290。根据一些实施例，使用化学镀工艺形成钯层290。
图11是根据一些实施例的半导体器件结构的截面图。如图11所示，根据一些实施例，半导体器件结构900还包括将金层240连接至接合焊盘320的导线310。在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。
衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
图12是根据一些实施例的半导体器件结构的截面图。如图12所示，根据一些实施例，半导体器件结构900还包括位于金层240上方的导电凸块410。根据一些实施例，导电凸块410电连接至金层240。
根据一些实施例，导电凸块410与金层240直接接触。根据一些实施例，导电凸块410包括导电材料。根据一些实施例，导电凸块410包括诸如锡(Sn)和铜(Cu)的焊接材料。
图13是根据一些实施例的半导体器件结构的截面图。如图13所示，根据一些实施例，除了半导体器件结构1300还包括介电层910、钝化层920、介电层930、钝化层940、绝缘层950和导电通孔结构960之外，半导体器件结构1300类似于图5B的半导体器件结构500。
根据一些实施例，在介电层120和布线层136上方形成介电层910。根据一些实施例，介电层910和120具有相同的材料。根据一些实施例，在介电层910上方形成钝化层920。根据一些实施例，钝化层920包括氧化物(例如，氧化硅)或氮化物。
如图13所示，根据一些实施例，布线衬底S还包括介电层930和钝化层940。根据一些实施例，在布线层278和介电层260上方形成介电层930。
根据一些实施例，介电层930和260具有相同的材料。根据一些实施例，在介电层930上方形成钝化层940。根据一些实施例，钝化层940包括氧化物(例如，氧化硅)或氮化物。根据一些实施例，钝化层920和940彼此接合。
如图13所示，根据一些实施例，孔H1穿过介电层150、半导体衬底110和绝缘层10。根据一些实施例，孔H1暴露了部分介电层120。如图13所示，根据一些实施例，在孔H1的内壁W1上方形成绝缘层950。根据一些实施例，绝缘层950包括诸如氧化硅的氧化物。
如图13所示，根据一些实施例，孔H2穿过介电层120。如图13所示，根据一些实施例，布线层136具有位于孔H1和布线层278之间的开口136a。
如图13所示，根据一些实施例，孔H3穿过介电层910、钝化层920、介电层930和钝化层940。根据一些实施例，孔H1、H2和H3以及开口136a一起暴露了部分布线层278。根据一些实施例，孔H1、H2和H3以及开口136a彼此连通(或连接)。
根据一些实施例，在孔H1、H2和H3以及开口136a中形成导电通孔结构960。根据一些实施例，孔H1、H2和H3以及开口136a填充有导电通孔结构960。
根据一些实施例，导电通孔结构960依次穿过介电层150、半导体衬底110、绝缘层10、介电层120、介电层910、钝化层920、钝化层940和介电层930。
根据一些实施例，导电通孔结构960将布线层136电连接至布线层278。根据一些实施例，导电通孔结构960包括导电材料。导电材料包括钨、铝、铜或另一合适的导电材料。
图14是根据一些实施例的半导体器件结构的截面图。如图14所示，根据一些实施例，半导体器件结构1300还包括钯层290。根据一些实施例，在镍层230和金层240之间形成钯层290。根据一些实施例，使用化学镀工艺形成钯层290。
图15是根据一些实施例的半导体器件结构的截面图。如图15所示，根据一些实施例，半导体器件结构1300还包括将金层240连接至接合焊盘320的导线310。在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。
衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
图16是根据一些实施例的半导体器件结构的截面图。如图16所示，根据一些实施例，半导体器件结构1300还包括位于金层240上方的导电凸块410。根据一些实施例，导电凸块410电连接至金层240。根据一些实施例，导电凸块410与金层240直接接触。根据一些实施例，导电凸块410包括导电材料。根据一些实施例，导电凸块410包括诸如锡(Sn)和铜(Cu)的焊接材料。
图17是根据一些实施例的半导体器件结构的截面图。如图17所示，根据一些实施例，除了半导体器件结构1700还具有位于镍层230下方的厚布线层1710之外，半导体器件结构1700类似于图16的半导体器件结构1300。
根据一些实施例，镍层230与厚布线层1710直接接触。根据一些实施例，镍层230电连接至厚布线层1710。根据一些实施例，厚布线层1710邻近于布线层132和134以及导电通孔结构142。
根据一些实施例，厚布线层1710具有厚度T1。根据一些实施例，布线层132具有厚度T2。根据一些实施例，导电通孔结构142具有厚度T3。根据一些实施例，布线层134具有厚度T4。根据一些实施例，厚度T1大于厚度T2、T3或T4。根据一些实施例，厚度T1大于或等于厚度T2、T3和T4的和。
由于过蚀刻，孔H可以延伸至厚布线层1710内。由于厚布线层1710具有大的厚度T1，防止了孔H穿过厚布线层1710。因此，厚布线层1710的形成提高了半导体器件结构1700的产量。
图18A是根据一些实施例的半导体器件结构1800的截面图。图18B是根据一些实施例的半导体器件结构1800的镍层230、导电环结构R1和部分布线层132的顶视图。
如图18A和图18B所示，根据一些实施例，除了半导体器件结构1800还具有导电环结构R1、R2和R3之外，半导体器件结构1800类似于图16的半导体器件结构1300。
根据一些实施例，在介电层120中和布线层132上方形成导电环结构R1。根据一些实施例，导电环结构R1与布线层132连接。根据一些实施例，在介电层120中以及在布线层132和134之间形成导电环结构R2。
根据一些实施例，导电环结构R2与布线层132和134连接。根据一些实施例，在介电层120中以及在布线层134和136之间形成导电环结构R3。根据一些实施例，导电环结构R3与布线层134和136连接。根据一些实施例，导电环结构R1、R2和R3以及布线层132和134由相同的材料制成。
根据一些实施例，导电环结构R1、R2和R3以及布线层132和134分别具有开口P1、P2、P3、132a和134a。根据一些实施例，开口P1、P2、P3、132a和134a彼此连接。根据一些实施例，镍层230还延伸至开口P1、P2、P3、132a和134a内。根据一些实施例，导电环结构R1、R2和R3以及布线层132和134围绕镍层230。
根据一些实施例，导电环结构R1、R2和R3以及布线层132和134一起防止了电镀溶液(用于形成镍层230)扩散至介电层120。因此，根据一些实施例，提高了半导体器件结构1800的产量。
图19是根据一些实施例的半导体器件结构的截面图。如图19所示，根据一些实施例，除了半导体器件结构1900还包括将金层240连接至接合焊盘320的导线310，并且半导体器件结构1900不具有导电凸块410之外，半导体器件结构1900类似于图17的半导体器件结构1700。
在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。
在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
图20是根据一些实施例的半导体器件结构的截面图。如图20所示，根据一些实施例，除了半导体器件结构2000还包括将金层240连接至接合焊盘320的导线310，并且半导体器件结构2000不具有导电凸块410之外，半导体器件结构2000类似于图18A的半导体器件结构1800。
在一些实施例中，接合焊盘320放置在衬底330上方。根据一些实施例，接合焊盘320包括诸如铜或铝的导电材料。衬底330包括半导体材料、塑料材料、金属材料、玻璃材料、陶瓷材料或另一合适的材料。
在一些实施例中，在半导体衬底250和衬底330之间形成粘合层340。根据一些实施例，粘合层340包括聚合物材料。在一些其它实施例中，半导体衬底250没有位于衬底330上方。
根据一些实施例，提供了半导体器件结构及其形成方法。该方法(用于形成半导体器件结构)在接合焊盘上方形成镍层以防止接合焊盘剥离。该方法在镍层上方形成金层，以缓冲由引线接合工艺或球接合工艺产生的接合应力。因此，镍层和金层的形成提高了半导体器件结构的可靠性。
根据一些实施例，提供了半导体器件结构。该半导体器件结构包括具有第一表面、第二表面和凹槽的第一半导体衬底。第二表面与第一表面相对。该凹槽穿过第一半导体衬底。该半导体器件结构包括位于第二表面上方的第一布线层。该半导体器件结构包括第一接合焊盘，该第一接合焊盘位于凹槽中并且延伸至第一布线层以电连接至第一布线层。该半导体器件结构包括位于第一接合焊盘上方的镍层。该半导体器件结构包括位于镍层上方的金层。
在上述半导体器件结构中，还包括：导线，将所述金层连接至第二接合焊盘。
在上述半导体器件结构中，还包括：导电凸块，位于所述金层上方。
在上述半导体器件结构中，还包括：第一介电层，位于所述第二表面上方，其中，所述第一布线层位于所述第一介电层中；第二布线层，嵌入在所述第一介电层内；第二半导体衬底；第二介电层，位于所述第二半导体衬底上方并且与所述第一介电层接合；以及第三布线层，嵌入在所述第二介电层内并且与所述第二布线层接合。
在上述半导体器件结构中，还包括：第一介电层，位于所述第二表面上方，其中，所述第一布线层位于所述第一介电层中；第二布线层，嵌入在所述第一介电层内；第二半导体衬底；第二介电层，位于所述第二半导体衬底上方并且与所述第一介电层接合；第三布线层，嵌入在所述第二介电层内；以及导电通孔结构，穿过所述第一半导体衬底和所述第一介电层以将所述第二布线层电连接至所述第三布线层。
在上述半导体器件结构中，还包括：钯层，位于所述镍层和所述金层之间。
在上述半导体器件结构中，其中，所述镍层和所述金层没有延伸至所述第一表面。
在上述半导体器件结构中，还包括：介电填充层，填充至所述凹槽，其中，所述介电填充层具有暴露部分所述第一接合焊盘的开口，并且所述镍层和所述金层位于所述开口中。
根据一些实施例，提供了半导体器件结构。该半导体器件结构包括具有表面和凹槽的第一半导体衬底。该凹槽穿过第一半导体衬底。该半导体器件结构包括位于表面上方的第一布线层。该半导体器件结构包括镍层，该镍层位于凹槽中并且延伸至第一布线层以电连接至第一布线层。该半导体器件结构包括位于镍层上方的金层。
在上述半导体器件结构中，还包括：介电层，位于所述表面上方，其中，所述第一布线层位于所述介电层中，所述介电层具有开口，所述开口位于所述凹槽下方并且暴露部分所述第一布线层，并且所述开口填充有所述镍层。
在上述半导体器件结构中，其中，所述镍层与所述第一布线层直接接触。
在上述半导体器件结构中，还包括：钯层，位于所述镍层和所述金层之间。
在上述半导体器件结构中，还包括：第二布线层，位于所述表面上方，其中，所述第一布线层厚于所述第二布线层。
在上述半导体器件结构中，还包括：导电环结构，位于所述第一布线层和所述第一半导体衬底之间，其中，所述导电环结构围绕所述镍层并且与所述第一布线层连接。
在上述半导体器件结构中，还包括：绝缘层，位于所述凹槽中并且围绕所述镍层。
根据一些实施例，提供了用于形成半导体器件结构的方法。该方法包括提供具有表面的第一半导体衬底。该方法包括在表面上方形成第一布线层。该方法包括在第一半导体衬底中形成凹槽。该凹槽穿过第一半导体衬底以暴露第一布线层。该方法包括在凹槽中形成第一接合焊盘。第一接合焊盘延伸至第一布线层以电连接至第一布线层。该方法包括在第一接合焊盘上方形成镍层。该方法包括在镍层上方形成金层。
在上述方法中，其中，所述镍层的形成包括：对所述第一接合焊盘实施化学镀工艺以形成所述镍层。
在上述方法中，还包括：形成将所述金层连接至第二接合焊盘的导线。
在上述方法中，还包括：在所述金层上方形成导电凸块。
在上述方法中，还包括：在所述表面上方形成第一介电层，其中，所述第一布线层位于所述第一介电层中；提供第二半导体衬底、第二介电层和第二布线层，其中，所述第二介电层位于所述第二半导体衬底上方，并且所述第二布线层嵌入在所述第二介电层内；以及将所述第一介电层接合至所述第二介电层，其中，所述第一布线层电连接至所述第二布线层。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件结构，包括：
第一半导体衬底，具有第一表面、第二表面和凹槽，其中，所述第二表面与所述第一表面相对，并且所述凹槽穿过所述第一半导体衬底；
第一布线层，位于所述第二表面上方；
第一接合焊盘，位于所述凹槽中并且延伸至所述第一布线层以电连接至所述第一布线层；
镍层，位于所述第一接合焊盘上方；以及
金层，位于所述镍层上方。
2.根据权利要求1所述的半导体器件结构，还包括：
导线，将所述金层连接至第二接合焊盘。
3.根据权利要求1所述的半导体器件结构，还包括：
导电凸块，位于所述金层上方。
4.根据权利要求1所述的半导体器件结构，还包括：
第一介电层，位于所述第二表面上方，其中，所述第一布线层位于所述第一介电层中；
第二布线层，嵌入在所述第一介电层内；
第二半导体衬底；
第二介电层，位于所述第二半导体衬底上方并且与所述第一介电层接合；以及
第三布线层，嵌入在所述第二介电层内并且与所述第二布线层接合。
5.根据权利要求1所述的半导体器件结构，还包括：
第一介电层，位于所述第二表面上方，其中，所述第一布线层位于所述第一介电层中；
第二布线层，嵌入在所述第一介电层内；
第二半导体衬底；
第二介电层，位于所述第二半导体衬底上方并且与所述第一介电层接合；
第三布线层，嵌入在所述第二介电层内；以及
导电通孔结构，穿过所述第一半导体衬底和所述第一介电层以将所述第二布线层电连接至所述第三布线层。
6.根据权利要求1所述的半导体器件结构，还包括：
钯层，位于所述镍层和所述金层之间。
7.根据权利要求1所述的半导体器件结构，其中，所述镍层和所述金层没有延伸至所述第一表面。
8.根据权利要求1所述的半导体器件结构，还包括：
介电填充层，填充至所述凹槽，其中，所述介电填充层具有暴露部分所述第一接合焊盘的开口，并且所述镍层和所述金层位于所述开口中。
9.一种半导体器件结构，包括：
第一半导体衬底，具有表面和凹槽，其中，所述凹槽穿过所述第一半导体衬底；
第一布线层，位于所述表面上方；
镍层，位于所述凹槽中并且延伸至所述第一布线层以电连接至所述第一布线层；以及
金层，位于所述镍层上方。
绝缘层，位于所述凹槽中并且围绕所述镍层。
10.一种用于形成半导体器件结构的方法，包括：
提供具有表面的第一半导体衬底；
在所述表面上方形成第一布线层；
在所述第一半导体衬底中形成凹槽，其中，所述凹槽穿过所述第一半导体衬底以暴露所述第一布线层；
在所述凹槽中形成第一接合焊盘，其中，所述第一接合焊盘延伸至所述第一布线层以电连接至所述第一布线层；
在所述第一接合焊盘上方形成镍层；以及
在所述镍层上方形成金层。
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