CN112736066B - 半导体元件及其制备方法 - Google Patents

半导体元件及其制备方法 Download PDF

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CN112736066B
CN112736066B CN202010862799.0A CN202010862799A CN112736066B CN 112736066 B CN112736066 B CN 112736066B CN 202010862799 A CN202010862799 A CN 202010862799A CN 112736066 B CN112736066 B CN 112736066B
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layer
conductive
isolation
forming
isolation film
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CN112736066A (zh
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黄则尧
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体元件及其制备方法。该半导体元件具有一基底、一本质导电垫、一应力释放结构以及一外部接合结构；该本质导电垫位于该基底上；该应力释放结构位于该基底上，并远离该本质导电垫设置；该外部接合结构直接位于该应力释放结构上。

Description

半导体元件及其制备方法
技术领域
本公开主张2019年10月28日申请的美国正式申请案第16/665,813号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
背景技术
半导体元件是使用在不同的电子应用，例如个人电脑、手机、数码相机，或其他电子设备。半导体元件的尺寸是逐渐地变小，以符合计算能力所逐渐增加的需求。然而，在尺寸变小的工艺期间，是增加不同的问题，且影响到最终电子特性、品质以及良率。因此，仍然持续着在达到改善品质、良率以及可靠度方面的挑战。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体元件，包括：一基底；一本质导电垫，位于该基底上；一应力释放结构，位于该基底上，并远离该本质导电垫设置；以及一外部接合结构，直接位于该应力释放结构上。
在本公开的一些实施例中，该应力释放结构包括一导电架以及多个隔离区段，该多个隔离区段位于该导电架内。
在本公开的一些实施例中，每一隔离区段具有一正方形形状，且所述多个隔离区段相互间隔设置。
在本公开的一些实施例中，该半导体元件还包括多个字元线，位于该基底中并沿一第一方向延伸，其中每一隔离区段具有一矩形形状，并沿一第二方向延伸，该第二方向垂直于该第一方向。
在本公开的一些实施例中，该半导体元件还包括多个字元线，位于该基底中并沿一第一方向延伸，其中每一隔离区段具有一矩形形状，并沿一第二方向延伸，该第二方向相对于该第一方向成对角线。
在本公开的一些实施例中，该半导体元件还包括一重分布导电层，位于该应力释放结构与该本质导电垫上。
在本公开的一些实施例中，该半导体元件还包括一应力缓冲层，位于该外部接合结构下，其中该应力缓冲层由一材料所制，该材料具有一热膨胀系数以及一杨氏模量，该热膨胀系数小于约20ppm/℃，而该杨氏模量小于约15GPa。
在本公开的一些实施例中，该外部接合结构包括一下接合层以及一上接合层，该下接合层直接位于该应力释放结构上，该上接合层位于该下接合层上。
在本公开的一些实施例中，该外部接合结构包括一下接合层、一中间接合层以及一上接合层，该下接合层直接位于该应力释放结构上，该中间接合层位于该下接合层上，而该上接合层位于该中间接合层上。
在本公开的一些实施例中，该外部接合结构的一宽度小于该应力释放结构的一宽度。
在本公开的一些实施例中，该半导体元件还包括一导线层(wiring layer)，位于该外部接合结构上。
在本公开的一些实施例中，该导线层的一宽度小于该外部接合结构的一宽度。
在本公开的一些实施例中，该半导体元件还包括二间隙子，邻近该外部接合结构的两侧设置。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括：提供一基底；形成一本质导电垫在该基底上；以及形成一应力释放结构在该基底上，并远离该本质导电垫设置。
在本公开的一些实施例中，形成该应力释放结构在该基底上，并远离该本质导电垫设置的步骤，包括：形成一导电架在该基底上；以及形成多个隔离区段在该导电架内。
在本公开的一些实施例中，该半导体元件的制备方法还包括：形成一重分布导电层在该本质导电垫与该应力释放结构上。
在本公开的一些实施例中，该半导体元件的制备方法还包括：形成多个钝化层在该重分布导电层上，以及形成一第一垫开口在该多个钝化层中。
在本公开的一些实施例中，该半导体元件的制备方法还包括：执行一钝化工艺，包括以一前驱物浸渍该第一垫开口，其中该前驱物为三甲硅基二甲胺(dimethylaminotrimethylsilane)或四甲基硅烷(tetramethylsilane)。
在本公开的一些实施例中，该半导体元件的制备方法还包括：执行一清洗工艺，其中该清洗工艺包括涂敷一远端等离子体到该第一垫开口。
在本公开的一些实施例中，该半导体元件的制备方法还包括：形成一外部接合结构在该重分布导电层上；其中该外部接合结构包括一下接合层以及一上接合层，该下接合层形成在该重分布导电层上，该上接合层形成在该下接合层上。
由于本公开该半导体元件的设计，该应力释放结构可分布导线(wiring)的应力；因此，可降低该多个隔离膜的分层(delamination)。结果，可改善该半导体元件的良率。此外，一钝化工艺可减少该多个钝化层的非预期的侧壁生长(undesirable sidewallgrowth)。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时，可得以更全面了解本公开的内容，附图中相同的元件符号是指相同的元件。
图1为依据本公开一实施例中一种半导体元件的剖视示意图。
图2为依据本公开图1中该半导体元件的顶视示意图。
图3至图5为依据本公开一些实施例中半导体元件的顶视示意图。
图6至图8为依据本公开一些实施例中半导体元件的剖视示意图。
图9为依据本公开一实施例中一种半导体元件的制备方法的流程示意图。
图10为依据本公开一实施例中一种半导体元件的顶视示意图。
图11为依据本公开图10沿剖线A-A’中制备该半导体元件流程的某部分的剖视示意图。
图12至图15为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
图16为依据本公开一实施例中一种半导体元件的顶视示意图。
图17为依据本公开图16沿剖线A-A’中制备该半导体元件流程的某部分的剖视示意图。
图18至图21为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
图22为依据本公开一实施例中一种半导体元件的顶视示意图。
图23为依据本公开图22沿剖线A-A’中制备该半导体元件流程的某部分的剖视示意图。
图24至图30为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
图31至图35为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
附图标记说明：
100A：半导体元件
100B：半导体元件
100C：半导体元件
100D：半导体元件
100E：半导体元件
100F：半导体元件
100G：半导体元件
101：基底
103：绝缘层
105：主动区
107：第一掺杂区
109：第二掺杂区
111：第一接触点
113：第二接触点
115：位元线接触点
117：位元线
119：电容栓塞
121：第一导电通孔
123：第一导电层
125：本质导电垫
127：重分布导电通孔
129：重分布导电层
131：应力缓冲层
201：字元线
203：字元线隔离层
205：字元线导电层
207：字元线盖层
209：字元线沟槽
301：电容结构
303：电容底电极
305：电容隔离层
307：电容顶电极
309：电容沟槽
401：应力释放结构
403：导电架
405：隔离区段
501：第一钝化层
503：第二钝化层
505：第三钝化层
507：第一垫开口
509：第二垫开口
601：外部接合结构
603：下接合层
605：上接合层
607：导线层
609：间隙子
611：中间接合层
613：间隙子层
701：第一隔离膜
703：第二隔离膜
705：第三隔离膜
707：第四隔离膜
709：第五隔离膜
711：第六隔离膜
713：第七隔离膜
715：第八隔离膜
717：第九隔离膜
801：清洗工艺
803：钝化工艺
W1：宽度
W2：宽度
W3：宽度
W：方向
X：方向
Y：方向
10：制备方法
S11：步骤
S13：步骤
S15：步骤
S17：步骤
S19：步骤
S21：步骤
S23：步骤
S25：步骤
S27：步骤
S29：步骤
具体实施方式
以下描述了组件和配置的具体范例，以简化本公开的实施例。当然，这些实施例仅用以例示，并非意图限制本公开的范围。举例而言，在叙述中第一部件形成于第二部件之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不会直接接触的实施例。另外，本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚，除非内文中特别说明，其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
理应理解，当形成一个部件在另一个部件之上(on)、与另一个部件相连(connected to)、及/或与另一个部件耦合(coupled to)，其可能包含形成这些部件直接接触的实施例，并且也可能包含形成额外的部件介于这些部件之间，使得这些部件不会直接接触的实施例。
应当理解，尽管这里可以使用术语第一，第二，第三等来描述各种元件、部件、区域、层或区段(sections)，但是这些元件、部件、区域、层或区段不受这些术语的限制。相反，这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此，在不脱离本发明进部性构思的教导的情况下，下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
除非内容中另有所指，否则当代表定向(orientation)、布局(layout)、位置(location)、形状(shapes)、尺寸(sizes)、数量(amounts)，或其他测量(measures)时，则如在本文中所使用的例如“同样的(same)”、“相等的(equal)”、“平坦的(planar)”，或是“共面的(coplanar)”等术语(terms)并非必要意指一精确地完全相同的定向、布局、位置、形状、尺寸、数量，或其他测量，但其意指在可接受的差异内，是包含差不多完全相同的定向、布局、位置、形状、尺寸、数量，或其他测量，而举例来说，所述可接受的差异是可因为制造流程(manufacturing processes)而发生。术语“大致地(substantially)”是可被使用在本文中，以表现出此意思。举例来说，如大致地相同的(substantially the same)、大致地相等的(substantially equal)，或是大致地平坦的(substantially planar)，为精确地相同的、相等的，或是平坦的，或者是其是可为在可接受的差异内的相同的、相等的，或是平坦的，而举例来说，所述可接受的差异是可因为制造流程而发生。
在本公开中，一半导体元件通常意指可通过利用半导体特性(semiconductorcharacteristics)运行的一元件，而一光电元件(electro-optic device)、一发光显示元件(light-emitting display device)、一半导体线路(semiconductor circuit)以及一电子元件(electronic device)，是均包括在半导体元件的范围中。
应当理解，在本公开的描述中，上方(above)(或之上(up))是对应Z方向箭头的该方向，而下方(below)(或之下(down))是对应Z方向箭头的相对方向。
图1为依据本公开一实施例中一种半导体元件100A的剖视示意图。图2为依据本公开图1中该半导体元件100A的顶视示意图。图3至图5为依据本公开一些实施例中半导体元件100B、100C、100D的顶视示意图。为了清楚表示，本公开的半导体元件的一些部件并未显示在图2至图5中。
请参考图1及图2，在所述的实施例中，半导体元件100A可包括一基底101、一绝缘层103、多个掺杂区、多个隔离膜、多个接触点、多个位元线接触点115、多个位元线117、多个电容栓塞119、一第一导电通孔121、一第一导电层123、一本质导电垫125、一重分布导电通孔127、一重分布导电层129、多个字元线201、多个电容结构301、一应力释放结构401、多个钝化层、一外部接合结构，以及一导线层(wiring layer)607。
请参考图1及图2，在所述的实施例中，举例来说，基底101可由下列材料所形成：硅、锗、硅锗(silicon germanium)、碳化硅(silicon carbon)、碳化锗硅(silicongermanium carbon)、镓、砷化镓(gallium arsenide)、砷化铟(indium arsenic)、磷化铟(indium phosphorus)或其他IV-IV族、III-V族或II-VI族半导体材料。或者是，在其他实施例中，基底101可包含一有机半导体或一层式半导体(layered semiconductor)，例如硅/硅锗、绝缘层上覆硅(silicon-on-insulator)或绝缘层上覆硅锗(silicon germanium-on-insulator)。当基底101由绝缘层上覆硅所制时，基底101可包含由硅所制的一上半导体层与一下半导体层，以及一埋入隔离层，而埋入隔离层可将上半导体层与下半导体层分隔开。举例来说，埋入隔离层可包含一多晶硅或非晶硅氧化物、氮化物或其组合。
请参考图1及图2，在所述的实施例中，绝缘层103可设置在基底101的一上部中。(在图1的剖视图中显示二绝缘层103，但其他数量的绝缘层可使用在其他实施例中。)举例来说，绝缘层103可由一隔离材料所制，例如氧化硅、氮化硅、氮氧化硅、氧化氮化硅、氟掺杂硅(fluoride-doped silicate)。绝缘层103可界定出基底101的多个主动区105。
应当理解，在本公开中，氮氧化硅是表示一物质，此物质是含有硅、氮以及氧，而其中氧的一比例大于氮的比例。而氧化氮化硅是表示一物质，此物质是含有硅、氮以及氧，而其中氮的一比例大于氧的比例。
请参考图1及图2，在所述的实施例中，多个字元线201可设置在基底101的上部中，且相互间隔设置。每一主动区105可贯穿其中二字元线201。多个字元线201可包括多个字元线隔离层203、多个字元线导电层205以及多个字元线盖层207。
请参考图1及图2，在所述的实施例中，多个字元线隔离层203可分别地对应朝内设置在基底101的上部中。多个字元线隔离层203的一厚度可约为0.5nm到10nm。多个字元线隔离层203的底部可为平坦的。多个字元线隔离层203可由一隔离材料所制，该隔离材料具有一介电常数，该介电常数约4.0或更大。(除非另有说明，否则所有在文中所提及的所有介电常数是相对于一真空。)具有约4.0或更大的介电常数的该隔离材料，可为氧化铪(hafniumoxide)、氧化锆(zirconium oxide)、氧化铝(aluminum oxide)、氧化钛(titanium oxide)、氧化镧(lanthanum oxide)、锶酸钛(strontium titanate)、铝酸镧(lanthanumaluminate)、氧化钇(yttrium oxide)、三氧化锗(gallium(III)trioxide)、钆镓氧化物(gadolinium gallium oxide)、锆钛酸铅(lead zirconium titanate)、锶钛酸钡(bariumstrontium titanate)或其混合物。或者是，隔离材料可为氧化硅、氮化硅、氮氧化硅、氧化氮化硅，或其类似物。
请参考图1及图2，在所述的实施例中，多个字元线导电层205可分别地对应设置在多个字元线隔离层203上。举例来说，多个字元线电极可由一导电材料所制，例如掺杂多晶硅、硅锗、金属、金属合金、硅化金属、氮化金属、碳化金属或含有多层的其组合。金属可为铝、铜、钨或钴。硅化金属可为硅化镍、硅化铂、硅化钛、硅化钼、硅化钴、硅化钽、硅化钨或其类似物。多个字元线导电层205的厚度可在50nm到500nm之间。
请参考图1及图2，在所述的实施例中，多个字元线盖层207可分别地对应设置在多个字元线导电层205上。多个字元线盖层207的顶表面可与基底101的一顶表面齐平。举例来说，多个字元线盖层207可由一隔离材料所制，该隔离材料具有一介电常数，该介电常数约为4.0或更大。
请参考图1及图2，在所述的实施例中，多个掺杂区可设置在基底101的一上部中。多个掺杂区可掺杂有一掺杂物(dopant)，例如磷、砷或锑(antimony)。多个掺杂区可包括一第一掺杂区107与二第二掺杂区109。第一掺杂区107可设置在其中二字元线201之间。二第二掺杂区109可分别对应设置在多个字元线201与绝缘层103之间。
请参考图1及图2，在所述的实施例中，多个隔离膜可设置在基底101上。举例来说，多个隔离膜可由下列材料所制：氮化硅、氧化硅、氮氧化硅、流动氧化物(flowable oxide)、东燃硅氮烷(tonen tilazen)、未经掺杂硅玻璃(undoped silica glass)、硼硅玻璃(borosilica glass)、磷硅玻璃(phosphosilica glass)、硼磷硅玻璃(borophosphosilicaglass)、等离子体增强四乙氧基硅烷(plasma enhanced tetra ethyl orthosilicate)、硅氟玻璃(fluoride silicate glass)、碳掺杂氧化硅(carbon doped silicon oxide)、干凝胶(xerogel)、气凝胶(aerogel)、非晶氟化碳(amorphous fluorinated carbon)、有机硅玻璃(organo silicate glass)、聚对二甲苯(parylene)、双苯并环丁烯(bis-benzocyclobutenes)、聚酰亚胺(polyimide)、多孔聚合材料(porous polymericmaterial)或其组合，但并不以此为限。多个隔离膜均可由相同材料所制，但并不以此为限。多个隔离膜可包括一第一隔离膜701、一第二隔离膜703、一第三隔离膜705、一第四隔离膜707、一第五隔离膜709、一第六隔离膜711、一第七隔离膜713、一第八隔离膜715以及一第九隔离膜717。
参考图1及图2，在所述的实施例中，第一隔离膜701可设置在基底101上。多个接触点可设置在第一隔离膜701中。对于每一主动区105，多个接触点可包括一第一接触点111以及二第二接触点113。第一接触点1111可设置在第一掺杂区107上并电性连接到第一掺杂区107。该二第二接触点113可分别对应设置在所述多个第二掺杂区109上并电性连接到所述多个第二掺杂区109。第一接触点111与该二第二接触点113可由一导电材料所制，例如掺杂多晶硅、金属、氮化金属或硅化金属。
请参考图1及图2，在所述的实施例中，第二隔离膜703可设置在第一隔离膜701上。多个位元线接触点115可设置在第二隔离膜703中以及设置在多个主动区105中。(图1的剖视图中仅显示一个位元线接触点115。)对于每一主动区105，位元线接触点115可设置在第一接触点111上并电性连接到第一接触点111。多个位元线接触点115可由与第一接触点111相同的材料所制，但并不以此为限。
请参考图1及图2，在所述的实施例中，第三隔离膜705可设置在第二隔离膜703上。多个位元线117可设置在第三隔离膜705中。(图1的剖视图中仅显示一个位元线117。)对于每一主动区105，位元线117可设置在相对应的位元线接触点115上并电性连接到相对应的位元线接触点115。多个位元线117可由一导电材料所制，例如钨、铝、镍或钴。
请参考图1及图2，在所述的实施例中，第四隔离膜707可设置在第三隔离膜705上。可设置多个电容栓塞119以穿经第四隔离膜707、第三隔离膜705以及第二隔离膜703。对于每一主动区105，其中二电容栓塞119可分别对应设置在该二第二接触点113上并电性连接到该二第二接触点113。多个电容栓塞119可由以下材料所制：掺杂多晶硅，钛、氮化钛、钽、氮化钽、钨、铜、铝或铝合金。
请参考图1及图2，在所述的实施例中，第五隔离膜709可设置在第四隔离膜707上。多个电容栓塞301可设置在第五隔离膜709中并分别对应设置在多个电容栓塞119上。多个电容结构301可电性连接到多个电容栓塞119。多个电容结构301可包括多个电容底电极303、一电容隔离层305以及一电容顶电极307。多个电容底电极303可朝内设置在第五隔离膜709上。多个电容底电极303的底部可直接接触多个电容栓塞119的顶表面。多个电容底电极303可由掺杂多晶硅、金属或硅化金属所制。
请参考图1及图2，在所述的实施例中，电容隔离层305可设置在多个电容底电极303上。电容隔离层305可由一单一层所形成，该单一层含有一隔离材料，该隔离材料具有一介电常数，该介电常数约为4.0或更大。电容隔离层305的一厚度可在到/>之间。或者是，在另一实施例中，电容隔离层305可由一堆叠层所形成，该堆叠层由氧化硅、氮化硅以及氧化硅所组成。电容顶电极307可设置在电容隔离层305上。电容顶电极307可由掺杂多晶硅或金属所制。
请参考图1及图2，在所述的实施例中，第六隔离膜711可设置在电容顶电极307上。第七隔离膜713可设置在第六隔离膜711上。第八隔离膜715可设置在第七隔离膜713上。第九隔离膜717可设置在第八隔离膜715上。第一导电通孔121可设置在第六隔离膜711中，并位于电容顶电极307上。第一导电通孔121可电性连接到电容顶电极307。举例来说，第一导电通孔121可由金属、金属合金、硅酸盐、硅化物、多晶硅、非晶硅(amorphous silicon)或其他半导体相容导电材料所制。第一导电层123可设置在第七隔离膜713中，并位于第一导电通孔121上。第一导电层123可电性连接到第一导电通孔121。举例来说，第一导电层123可由一导电材料所制，例如掺杂多晶硅、金属、氮化金属或硅化金属。
请参考图1及图2，在所述的实施例中，一本质导电垫(intrinsically conductivepad)125可设置在第八隔离膜715中，并位于第一导电层123上。本质导电垫125可电性连接到第一导电层123，并电性耦接到多个电容结构301。举例来说，本质导电垫125可由铝或铜所制。或者是，在其他实施例中，本质导电垫125可由一堆叠层所形成，该堆叠层由金、镍或铜所组成。
应当理解，在实施例中的第一导电通孔121与第一导电层123仅表示用于图例说明为目的，并不以此为限。导电通孔与导线可为其他数量，例如一第二导电通孔或一第二导线，设置在其他数量的多个隔离膜之间，以电性耦接到本质导电垫125，而亦有可能是其他数量的电容结构301。
请参考图1及图2，在所述的实施例中，应力释放结构(stress relief structure)401可设置在第八隔离膜715中，并远离本质导电垫125设置。应力释放结构401可包括一导电架(conductive frame)403以及多个隔离区段(insulating segments)405。导电架403可设置在远离本质导电垫125处，并可具有一网形(mesh shape)。意即，导电架403的组件可相互连接。举例来说，导电架403可由一导电材料所制，例如金属、氮化金属，或硅化金属。多个隔离区段405可设置在导电架403内，并可具有一正方形形状。多个隔离区段405可由与第八隔离膜715相同材料所制，但并不以此为限。或者是，在其他实施例中，多个隔离区段405可由一材料所制，该材料包含聚酰亚胺(polyimide)或环氧基(epoxy-based)材料。
请参考图1及图2，在所述的实施例中，重分布导电通孔(redistributionconductive via)127可设置在第九隔离膜717中，并位于本质导电垫125上。重分布导电通孔127可电性连接到本质导电垫125。重分布导电通孔127可由与第一导电通孔121相同材料所制，但并不以此为限。重分布导电层(redistribution conductive layer)129可设置在第九隔离膜717上。重分布导电层129可设置在本质导电垫125与应力释放结构401上。举例来说，重分布导电层129可由锡、镍、铜、金、铝或其合金所制。重分布导电层129可电性连接到重分布导电通孔127，并电性耦接到本质导电垫125。
请参考图1及图2，在所述的实施例中，多个钝化层可设置在重分布导电层129上以及第九隔离膜717上。多个钝化层可包括一第一钝化层501、一第二钝化层503以及一第三钝化层505。第一钝化层501可设置在第九隔离膜717与重分布导电层129上。举例来说，第一钝化层501可由氧化硅或磷硅玻璃所制。第二钝化层503可设置在第一钝化层501上，举例来说，可由氮化硅、氮氧化硅或氮化氧化硅所制。第一钝化层501可当作是在第二钝化层503与第九隔离膜717之间的一应力缓冲(stress buffer)。为了避免湿气从上进入，则第二钝化层503可当作是一高气相阻障(high vapor barrier)。第三钝化层505可设置在第二钝化层503上，举例来说，可由聚酰亚胺(polyimide)或聚酰胺(polyamide)所制。第三钝化层505可保护位于第三钝化层505下的各层，避免机械刮伤(mechanical scratch)或背景辐射(background radiation)。
请参考图1及图2，在所述的实施例中，外部接合结构601可设置在第二钝化层503与第一钝化层501中。外部接合结构601可设置在重分布导电层129上。外部接合结构601可直接设置在应力释放结构401上，并高于本质导电垫125。外部接合结构601可电性连接到重分布导电层129，并电性耦接到本质导电垫125。外部接合结构601可包括一下接合层603以及一上接合层605。
请参考图1及图2，在所述的实施例中，下接合层603可设置在第一钝化层501中，并位于重分布导电层129上。下接合层603可电性连接到重分布导电层129。下接合层603的一厚度可小于第一钝化层501的一厚度。下接合层603可包含镍。上接合层605可设置在第一钝化层501与第二钝化层503中。上接合层605可设置在下接合层603上，并电性连接到下接合层603。上接合层605的一顶表面可与第二钝化层503的一顶表面齐平。上接合层605可包含钯(palladium)、钴或其组合。应力释放结构401的一宽度W1可大于外部接合结构601的一宽度W2。
请参考图1及图2，在所述的实施例中，一导线层(wiring layer)607可设置在第三钝化层505中，并位于上接合层605上。举例来说，导线层607可由金、铜、铝或其合金所制。导线层607的一宽度可小于外部接合结构601的宽度W2。一导线(wire)或焊料凸块(solderbump)(图未示)可设置在导线层607上，并可将半导体元件电性连接到一外部电路。
在一布线工艺(wiring process)或形成一锡料凸块的一工艺期间，会施加一应力(stress)在半导体元件，且该应力可造成多个隔离膜的分层(delamination)。为了降低导线应力的影响，重分布导线层129可将应力从本质导电垫125重新导向到导线层607。应力释放结构401直接位于导线层607下，而外部接合结构601可当作一减震垫(cushion)，以降低导线的应力，并避免在应力释放结构401下的多层被分层(delaminating)。此外，导电架403的各组件相互连接，并可分布应力遍及整个导电架403；因此，相较于一独立的抗应力结构(standalone anti-stress structure)而言，导电架403可提供一优选的应力缓冲(stress-buffering)能力。再者，由包含聚酰亚胺或环氧基材料所制的多个隔离区段405，可能够吸收与分布应力以进一步改善应力释放结构401的应力缓冲能力。
请参考图3，导电架403可具有一矩形形状，该矩形形状具有平行及水平的横梁(crossmembers)。多个隔离区段405可具有一矩形形状，并可相互间隔设置。多个隔离区段405可沿着一方向Y延伸。请参考图4，导电架403可具有一矩形形状，该矩形形状具有平行及垂直的横梁(crossmembers)。多个隔离区段405可具有一矩形形状，并可相互间隔设置。多个隔离区段405可沿着一方向X延伸，方向X垂直于方向Y。请参考图5，导电架403可具有一矩形形状，该矩形形状具有平行及对角线的横梁(crossmembers)。多个隔离区段405可具有一矩形形状，并可相互间隔设置。多个隔离区段405可沿着一方向W延伸，方向W相对于方向X与方向Y倾斜(或成对角线)。
图6至图8为依据本公开一些实施例中半导体元件100E、100F、100G的剖视示意图。
请参考图6，多个间隙子609可贴合到外部接合结构601的两侧。换言之，二间隙子609可设置在外部接合结构601与第一钝化层501及第二钝化层503之间。举例来说，该二间隙子609可由氧化硅所制。
如图7所示，外部接合结构601可包括下接合层603、一中间接合层611以及上接合层605。中间接合层611可设置在下接合层603上。上接合层605可设置在中间接合层611上。举例来说，下接合层603可由金所制。举例来说，中间接合层611可由镍所制。举例来说，上接合层605可由铜所制。
请参考图8，一应力缓冲(stress-buffering)层131可设置在第九隔离膜717中，并位于重分布导电层129与应力释放结构401之间。应力缓冲层131可直接设置在外部接合结构601下。应力缓冲层131可用于吸收及分布从下层来的应力集中(stressconcentration)，其是由剪应力(shear stresses)所产生，而剪应力是由于布线工艺的热膨胀不匹配(thermal expansion mismatch)以及一般应力而来。举例来说，应力缓冲层131可由一材料所制，该材料具有一热膨胀系数以及一杨氏模量(Young’s Modulus)，而膨胀系数小于约20ppm/℃，而杨氏模量小于约15GPa。特别是，应力缓冲层131可由一材料所制，该材料包含聚酰亚胺(polyimide)或环氧基(epoxy-based)材料。应力缓冲层131可具有一厚度，约在及/>之间。优选者，应力缓冲层131的厚度可在/>与之间。
图9为依据本公开一实施例中一种半导体元件100A的制备方法10的流程示意图。图10为依据本公开一实施例中一种半导体元件100A的顶视示意图。图11为依据本公开图10沿剖线A-A’中制备该半导体元件100A流程的某部分的剖视示意图。为了清楚表示，本公开的半导体元件的一些部件并未显示在图10中。
请参考图9至图11，在步骤S11，在所述的实施例中，可提供一基底101，且一绝缘层103、多个字元线沟槽209以及多个掺杂区可形成在基底101中。绝缘层103可界定出多个主动区105。多个主动区105可相互间隔设置，并沿在一顶视图中的一方向W延伸。多个字元线沟槽209可朝内形成在基底101中。多个字元线沟槽209可沿一方向X延伸，而方向X相对于方向W倾斜(或成对角线)。每一主动区105可贯穿其中二多个字元线沟槽209。多个掺杂区可包括一第一掺杂区107以及二第二掺杂区109。第一掺杂区107可形成在多个字元线沟槽209之间。该二第二掺杂区109可形成在绝缘层103与多个字元线沟槽209之间。
图12及图15为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。图16为依据本公开一实施例中一种半导体元件的顶视示意图。图17为依据本公开图16沿剖线A-A’中制备该半导体元件流程的某部分的剖视示意图。为了清楚表示，本公开的半导体元件的一些部件并未显示在图16中。
请参考图9以及图12至图14，在步骤S13，在所述的实施例中，多个字元线201可形成在基底101中。多个字元线201可包括多个字元线隔离层203、多个字元线导电层205以及多个字元线盖层207。请参考图12，多个字元线隔离层203可形成在多个字元线沟槽209中。请参考图13，多个字元线导电层205可分别对应形成在多个字元线隔离层203上。请参考图14，多个字元线盖层207可形成在多个字元线导电层205上。可执行例如化学机械研磨的一平坦化工艺，已提供一大致平坦表面给接下来的处理步骤。
请参考图9以及图15至图17，在步骤S15，在所述的实施例中，多个位元线117可形成在基底101上。请参考图15，一第一隔离膜701可形成在基底101上。对于每一主动区105而言，一第一接触点111以及二第二接触点113可形成在第一隔离膜701中。第一接触点111可形成在第一掺杂区107上。该二第二接触点113可分别对应形成在该二第二掺杂区109上。
请参考图16及图17，一第二隔离膜703可形成在第一隔离膜701上。一第三隔离膜705可形成在第二隔离膜703上。多个位元线接触点115可形成在第二隔离膜703中。多个位元线接触点115可分别对应设置在多个第一接触点111上。多个位元线117可形成在第三隔离膜705中。多个位元线117可沿一方向Y延伸，而方向Y相对于方向W倾斜(或成对角线)，并垂直于方向X。多个位元线117可以波形线(wavy lines)实施。多个位元线117可相互间隔设置。在顶视图中，每一位元线117可贯穿其中一主动区105。多个位元线117可电性连接到多个位元线接触点115。
图18及图20为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。图22为依据本公开一实施例中一种半导体元件的顶视示意图。图23为依据本公开图22沿剖线A-A’中制备该半导体元件流程的某部分的剖视示意图。为了清楚表示，本公开的半导体元件的一些部件并未显示在图23中。
请参考图9以及图18至图21，在步骤S17，在所述的实施例中，多个电容结构301可形成在基底101上。多个电容结构301可包括多个电容底电极303、一电容隔离层305以及一电容顶电极307。请参考图18，一第四隔离膜707可形成在第三隔离膜705上。可形成多个电容栓塞119以延伸经过第四隔离膜707、第三隔离膜705以及第二隔离膜703。对于每一主动区105而言，多个电容栓塞119可分别对应设置在该二第二接触点113上。
请参考图19，一第五隔离膜709可形成在第四隔离膜707上。多个电容沟槽309可朝内形成在第五隔离膜709中。多个电容底电极303可分别对应形成在多个电容沟槽309中。请参考图20，电容隔离层305可形成在多个电容底电极303上。请参考图21，一电容顶电极307可形成在电容隔离层305上，并可充填多个电容沟槽309。
请参考图9、图22以及图23，在步骤S19，在所述的实施例中，一本质导电垫125与一应力释放结构401可形成在基底101上。应力释放结构401可包括一导电架403以及多个隔离区段405。请参考图22及图23，一第六隔离膜700以及一第七隔离膜713可按序形成在电容顶电极307上。一第一导电通孔121可形成在第六隔离膜711中，并位于电容顶电极307上。一第一导电层123可形成在第七隔离膜713中，并位于第一导电通孔121上。本质导电垫125与应力释放结构401可同时形成在第八隔离膜715中，但并不以此为限。
请参考图22及图23，在所述的实施例中，一导电层可通过一第一沉积工艺而形成在第七隔离膜713上，而第一沉积工艺是例如化学气相沉积、物理气相沉积、溅镀(sputtering)沉积、电镀、无电电镀。可执行一光刻工艺，以界定出本质导电垫125以及导电架403的位置。在光刻工艺之后，可执行一蚀刻工艺，例如一非等向性干蚀刻工艺，以形成本质导电垫125与导电架403在第七隔离膜713上。接下来，可执行一第二沉积工艺，以沉积一隔离层在第七隔离膜713上，并覆盖本质导电垫125与应力释放结构401。在第二沉积工艺之后，可执行一平坦化工艺，例如化学机械研磨，直到本质导电垫125与导电架403的顶表面暴露，并同时形成第八隔离膜715与多个隔离区段405在导电架403内。
图24及图30为依据本公开一实施例中制备半导体元件100A流程的某部分的剖视示意图。
请参考图9及图24，在步骤S21，在所述实施例中，一重分布导电层129可形成在本质导电垫125与应力释放结构401上。一第九隔离膜717可形成在第八隔离膜715上。一重分布导电通孔127可形成在第九隔离膜717中，并位于本质导电垫125上。一导电层可通过一沉积工艺而形成在第九隔离膜717上，而沉积工艺是例如化学气相沉积、物理气相沉积、溅镀沉积、电镀或无电电镀。可执行一光刻工艺以界定出重分布导电层129的位置。在光刻工艺之后，可执行一蚀刻工艺，例如一非等向性干蚀刻工艺，以形成重分布导电层129。
请参考图9以及图25，在步骤S23，在所述实施例中，一第一钝化层501以及一第二钝化层503可按序形成在第九隔离膜717与重分布导电层129上，而可形成一第一垫开口507以穿经第一钝化层501与第二钝化层503，并可在第二钝化层503与第一垫开口507上执行一清洗工艺。第一钝化层501可通过一沉积工艺而形成在第九隔离膜717以及重分布导电层129上。可执行一平坦化工艺，例如化学机械研磨，以提供一平坦表面给接下来的处理步骤。第二钝化层503可形成在第一钝化层501上。可执行一光刻工艺以界定出第一垫开口507的位置。在光刻工艺之后，可执行一蚀刻工艺，例如一非等向性干蚀刻工艺，以形成第一垫开口507。重分布导电层129的顶表面的一部分可经由第一垫开口507而暴露。
请参考图25，在蚀刻工艺的后可执行清洗工艺801。清洗工艺801包括把氢与氩的一混合物当作一远距离等离子体(remote plasma)，在工艺温度介于250℃至350℃之间，一工艺压力介于1Torr至10T之间，以及供应给设备执行清洗工艺801的一偏压能量(biasenergy)的存在条件下。偏压能量可介于0W至200W之间。清洗工艺801可移除在重分布导电层129的顶表面上的氧化物，而不会损害到重分布导电层129的导电效能，而该氧化物是始源于在空气中的氧气的氧化。
请参考图9以及图26，在步骤S25，在所述的实施例中，可在第二钝化层503与第一垫开口507上执行一钝化工艺(passivation process)803。钝化工艺803可包括浸渍半导体元件在一前驱物中，其中该前驱物为三甲硅基二甲胺、四甲基硅烷，或其类似物，是在一工艺温度介于200℃至400℃之间。可使用一紫外线能量以促进钝化工艺803。钝化工艺803可钝化第二钝化层503以及第一钝化层501经由第一垫开口507暴露的各侧壁，其是通过密封其表面毛孔以降低不合适的侧壁生长，其是在接下来的处理步骤期间，可影响半导体元件的电子效能。因此，可提升半导体元件的效能与可靠度。
请参考图9、图27及图28，在步骤S27，在所述的实施例中，一外部接合结构601可形成在第一垫开口507中。外部接合结构601可包括一下接合层603以及一上接合层605。请参考图27，下接合层603可通过电镀或无电电镀而形成位于第一垫开口507中的重分布导电层129上。下接合层603可包含镍，并可当成在由铜所制的重分布导电层129与上接合层605之间的一阻障(barrier)。请参考图28，上接合层605可通过电镀或无电电镀而形成位于第一垫开口507中的下接合层603上。上接合层605可由钯、钴或其组合所制。上接合层605的一顶表面可包括多个非均质成核部分(heterogeneous nucleation sites)，例如形貌特征(topographical features)、晶格不连续/定向(lattice discontinuities/orientations)、表面缺陷(surface defects)、纹理(textures)或其他表面特征。在上接合层605的顶表面上的多个非均质成核部分可促进接下来的一布线/接合(wiring/bonding)工艺。
请参考图9、图29以及图30，在步骤S29，在所述实施例中，一第三钝化层505与一导线层607可形成在第二钝化层503上。请参考图29，第三钝化层505可形成在第二钝化层503上。第三钝化层505可包含聚酰亚胺(polyimide)或聚酰胺(polyamide)。可执行一光刻工艺以界定出导线层607在第三钝化层505中的位置。在光刻工艺之后，可执行一蚀刻工艺，例如一非等向性干蚀刻工艺，以形成一第二垫开口509。上接合层605的顶表面的一部分可经由第二垫开口509而暴露。请参考图30，导线层607可形成在电二垫开口509中，并位于上接合层605上。
图31及图35为依据本公开一实施例中制备半导体元件100E流程的某部分的剖视示意图。
请参考图31，一间隙子层613可形成在第二钝化层503的一顶表面上，并位于第一垫开口507中。举例来说，间隙子层613可由氧化硅所制。请参考图32，可执行一蚀刻工艺，例如一非等向性干蚀刻工艺，以移除间隙子层613形成在第二钝化层503的顶表面上与第一垫开口507的一底部上的部分，且同时形成贴合到第一垫开口507的各侧壁的二间隙子609。请参考图33及图34，外部接合结构601可通过一程序(procedure)所形成，该程序类似于图27与图28所图例示出者。下接合层603可形成在重分布导电层129上，并位于二间隙子609之间。上接合层605可形成在下接合层603上，并位于二间隙子609之间。请参考图35，第三钝化层505与导线层607可通过一程序(procedure)所形成，该程序类似于图29与图30所图例示出者。
由于本公开该半导体元件的设计，应力释放结构401可分布导线(wiring)的应力；因此，可降低该多个隔离膜的分层(delamination)。结果，可改善该半导体元件的良率。此外，一钝化工艺可减少该多个钝化层的非预期的侧壁生长。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (5)

1.一种半导体元件的制备方法，包括：
提供一基底；
形成多个隔离膜在该基底上，其中所述隔离膜相互重叠，其中所述隔离膜中的一者被构造为公共隔离膜；
形成一本质导电垫在该基底上并且设置在该公共隔离膜中，其中该本质导电垫的高度等于该公共隔离膜的厚度；以及
形成一应力释放结构在该公共隔离膜中并远离该本质导电垫设置，其中该应力释放结构的高度等于该公共隔离膜的厚度，使得该本质导电垫的高度为该应力释放结构的高度，其中形成该应力释放结构在该公共隔离膜中并远离该本质导电垫设置的步骤，包括：
形成一导电架在该基底上，其中该导电架由一导电材料所制并具有一网形结构以增强应力缓冲能力；以及
形成多个隔离区段在该导电架内，其中所述隔离区段在该导电架内相互间隔设置并能够吸收与分布应力；
在所述隔离膜中的一者中形成一重分布导电通孔在最上面的位置，并将该重分布导电通孔电性连接到该本质导电垫；
形成一重分布导电层在所述隔离膜的顶部并在该本质导电垫与该应力释放结构上，并且通过该重分布导电通孔将该重分布导电层电性耦接到该本质导电垫；
形成多个钝化层在所述隔离膜的顶部并形成一第一垫开口在该多个钝化层中，其中该重分布导电层设置在所述钝化层中的一者中并在最上面的位置与所述隔离膜中的一者接触，以便电性耦接到该重分布导电通孔；并且
执行一钝化工艺，包括以一前驱物浸渍该第一垫开口，其中该前驱物为三甲硅基二甲胺或四甲基硅烷。
2.如权利要求1所述的半导体元件的制备方法，还包括：执行一清洗工艺，其中该清洗工艺包括涂敷一远端等离子体到该第一垫开口。
3.如权利要求1所述的半导体元件的制备方法，还包括：
形成一外部接合结构在该重分布导电层上；
其中该外部接合结构包括一下接合层以及一上接合层，该下接合层形成在该重分布导电层上，该上接合层形成在该下接合层上。
4.如权利要求3所述的半导体元件的制备方法，还包括形成一应力缓冲层，位于该外部接合结构下，其中该应力缓冲层由一材料所制，该材料具有一热膨胀系数以及一杨氏模量，该热膨胀系数小于20ppm/℃，而该杨氏模量小于15GPa。
5.如权利要求1所述的半导体元件的制备方法，其中所述多个隔离区段中的每一隔离区段具有一矩形形状，并且所述多个隔离区段由与该公共隔离膜相同的材料所制。
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Publication number Priority date Publication date Assignee Title
US11610835B2 (en) * 2020-10-30 2023-03-21 Taiwan Semiconductor Manufacturing Company Limited Organic interposer including intra-die structural reinforcement structures and methods of forming the same
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106469701A (zh) * 2015-08-14 2017-03-01 台湾积体电路制造股份有限公司 半导体器件结构及其形成方法
CN107039478A (zh) * 2015-12-29 2017-08-11 台湾积体电路制造股份有限公司 集成芯片与其形成方法
CN108807318A (zh) * 2017-04-28 2018-11-13 三星电子株式会社 半导体器件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
US7208837B2 (en) * 2004-02-10 2007-04-24 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits
US7714448B2 (en) * 2004-11-16 2010-05-11 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US7646087B2 (en) * 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
JP4764668B2 (ja) * 2005-07-05 2011-09-07 セイコーエプソン株式会社 電子基板の製造方法および電子基板
JP4289335B2 (ja) * 2005-08-10 2009-07-01 セイコーエプソン株式会社 電子部品、回路基板及び電子機器
JP5111878B2 (ja) * 2007-01-31 2013-01-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI364804B (en) * 2007-11-14 2012-05-21 Ind Tech Res Inst Wafer level sensor package structure and method therefor
DE102008054054A1 (de) * 2008-10-31 2010-05-12 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Aufbau für reduzierte Verspannung von Metallsäulen
US8227916B2 (en) * 2009-07-22 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for reducing dielectric layer delamination
KR102079283B1 (ko) * 2013-10-15 2020-02-19 삼성전자 주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
US9812414B1 (en) 2016-06-17 2017-11-07 Nanya Technology Corporation Chip package and a manufacturing method thereof
US11011413B2 (en) * 2017-11-30 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming the same
US10573602B2 (en) * 2018-06-22 2020-02-25 Nanya Technology Corporation Semiconductor device and method of forming the same
US11069630B2 (en) * 2018-09-21 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for reducing thermal expansion mismatch during integrated circuit packaging

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106469701A (zh) * 2015-08-14 2017-03-01 台湾积体电路制造股份有限公司 半导体器件结构及其形成方法
CN107039478A (zh) * 2015-12-29 2017-08-11 台湾积体电路制造股份有限公司 集成芯片与其形成方法
CN108807318A (zh) * 2017-04-28 2018-11-13 三星电子株式会社 半导体器件及其制造方法

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