CN112908964B - 具有应力释放特征的半导体元件及其制备方法 - Google Patents
具有应力释放特征的半导体元件及其制备方法 Download PDFInfo
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- CN112908964B CN112908964B CN202011238661.XA CN202011238661A CN112908964B CN 112908964 B CN112908964 B CN 112908964B CN 202011238661 A CN202011238661 A CN 202011238661A CN 112908964 B CN112908964 B CN 112908964B
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- conductive
- passivation film
- semiconductor device
- bond pad
- stress
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Abstract
本公开提供一种半导体元件及该半导体元件的制备方法。该半导体元件具有一半导体基底、一应力释放结构以及一导电结构,该应力释放结构具有一导电架与多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内,该导电结构具有一支撑部、一导电部以及多个间隙子,该支撑部位于该应力释放结构上,该导电部邻近该支撑部设置,该多个间隙子贴合到该导电部的两侧。该导电架的一宽度等于该导电部的一底部的一宽度。
Description
技术领域
本公开主张2019年11月19日申请的美国正式申请案第16/688,014号的优先权及益处,该美国正式申请案的内容以全文引用的方式并入本文中。
背景技术
半导体元件是使用在不同的电子应用,例如个人电脑、手机、数码相机,或其他电子设备。半导体元件的尺寸是逐渐地变小,以符合计算能力所逐渐增加的需求。然而,在尺寸变小的工艺期间,是增加不同的问题,且影响到最终电子特性、品质以及良率。因此,仍然持续着在达到改善品质、良率以及可靠度方面的挑战。
上文的“现有技术”说明仅是提供背景技术,并未承认上文的“现有技术”说明公开本公开的标的,不构成本公开的现有技术,且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体元件,包括一半导体基底;一应力释放结构,包括一导电架以及多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内;以及一导电结构,包括一支撑部、一导电部以及多个间隙子,该支撑部位于该应力释放结构上,该导电部邻近该支撑部设置,该多个间隙子贴合到该导电部的两侧。该导电架的一宽度等于该导电部的一底部的一宽度。
在本公开的一些实施例中,该导电部位于该导电架上。
在本公开的一些实施例中,该导电结构的一底部的一宽度大于该应力释放结构的一宽度。
在本公开的一些实施例中,该半导体元件还包括一接合垫结构,位于该导电结构与该应力释放结构之间,其中该接合垫结构的一顶表面接触该导电部的该底部。
在本公开的一些实施例中,该接合垫结构包括一下接合垫以及一上接合垫,该下接合垫位于该导电结构与该应力释放结构之间,该上接合垫位于该下接合垫上,其中该上接合垫的一顶表面接触该导电部的该底部。
在本公开的一些实施例中,该接合垫结构的一宽度大于该导电部的该底部的该宽度。
在本公开的一些实施例中,该导电结构包括一上导电部,位于该支撑部与该导电部上。
在本公开的一些实施例中,该半导体元件还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该接合垫结构位于该下钝化膜与该上钝化膜中。
在本公开的一些实施例中,该半导体元件还包括一对垫间隙子,贴合到该接合垫结构的两侧。
在本公开的一些实施例中,该半导体元件还包括一导电覆盖膜,覆盖该多个间隙子、该上接合垫的该顶表面的一部分以及该支撑部的一顶表面。
在本公开的一些实施例中,该半导体元件还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该支撑部与该导电部位于该下钝化膜与该上钝化膜中。
在本公开的一些实施例中,该半导体元件还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该支撑部与该导电部位于该下钝化膜与该上钝化膜中,且该支撑部包括一下区段以及一上区段,该下区段位于与该下钝化膜相同的一垂直水平面处,该上区段位于该下区段上,并位于与该上钝化膜相同的一垂直水平面处。
在本公开的一些实施例中,该导电架的一水平剖面轮廓为网状、同心环或类似方向盘的形状。
在本公开的一些实施例中,该支撑部的一水平剖面轮廓为网状、有规律对准的柱体或同心环。
在本公开的一些实施例中,该半导体元件还包括一重分布层,位于该半导体基底上,并电性耦接到该接合垫结构。
在本公开的一些实施例中,该半导体元件还包括一应力吸收层,位于该应力释放结构与该接合垫结构之间,其中该应力吸收层由一材料所制,该材料具有一热膨胀系数以及一杨氏模量,该热膨胀系数小于约20ppm/℃,而该杨氏模量小于约15GPa。
在本公开的一些实施例中,该半导体元件还包括一重分布层,位于该应力吸收层上,并电性耦接到该接合垫结构。
在本公开的一些实施例中,该导体元件还包括一重分布层,位于该半导体基底上,其中该重分布层包括一下交错区段以及一上交错区段,该下交错区段位于与该应力吸收层相同的一垂直水平面处,该上交错区段位于该下交错区段上,并邻近该接合垫结构设置。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括:提供一半导体基底;形成一应力释放结构,包括一导电架以及多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内;以及形成一导电结构,该导电结构包括一支撑部、一导电部以及多个间隙子,该支撑部位于该应力释放结构上,该导电部邻近该支撑部设置,该多个间隙子贴合到该导电部的两侧。
在本公开的一些实施例中,形成该应力释放结构,包括该导电架以及该多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内的步骤包括:形成一第一钝化膜在该半导体基底上;执行一光刻工艺以界定出该应力释放结构位于该第一钝化膜上的一位置;执行一蚀刻工艺以形成一导电架开孔在该第一钝化膜中;沉积一导电材料在该导电架开孔中;以及执行一平坦化工艺以同时形成该导电架与多个隔离柱。
由于本公开该半导体元件的设计,可通过该导电结构的该支撑部以及该应力释放结构,以减少源自于一布线工艺(wiring process)、形成一焊料凸块(solder bump)的工艺或是一封装工艺(package process)的应力。结果,可避免该半导体元件的破裂(cracking)或是内连接膜的分层(delamination)。因此,可改善该半导体元件的良率或可靠度。
上文已相当广泛地概述本公开的技术特征及优点,从而使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解,可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解,这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时,可得以更全面了解本公开的公开内容,附图中相同的元件符号是指相同的元件。
图1为依据本公开一实施例中一种半导体元件的垂直剖视示意图。
图2为依据本公开图1中沿剖线A-A’的一实施例半导体元件的一部分的剖视示意图。
图3为依据本公开图1中沿剖线B-B’的一实施例半导体元件的一部分的剖视示意图。
图4到图6为依据本公开图1中沿剖线A-A’的另一实施例半导体元件的一部分的剖视示意图。
图7到图8为依据本公开图1中沿剖线B-B’的另一实施例半导体元件的一部分的剖视示意图。
图9到图15为依据本公开一实施例中各半导体元件的垂直剖视示意图。
图16为依据本公开一实施例中一种半导体元件的制备方法的流程示意图。
图17到图20为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
图21为依据本公开图20中沿剖线A-A’的制备半导体元件流程的某部分的剖视示意图。
图22到图30为依据本公开一实施例中制备半导体元件流程的某部分的剖视示意图。
图31到图45为依据本公开另一实施例中制备半导体元件流程的某部分的剖视示意图。
附图标记说明:
10:制备方法
100A:半导体元件
100B:半导体元件
100C:半导体元件
100D:半导体元件
100E:半导体元件
100F:半导体元件
100G:半导体元件
100I:半导体元件
100J:半导体元件
100K:半导体元件
100L:半导体元件
101:半导体基底
103:内连接膜
105:第一钝化膜
107:第二钝化膜
109:第三钝化膜
109-1:第三下钝化膜
109-2:第三上钝化膜
111:第四钝化膜
111-1:第四下钝化膜
111-2:第四上钝化膜
115:导电栓塞
201:应力释放结构
203:导电架
203-1:连接组件
205:隔离柱
207:导电架开孔
301:接合垫结构
303:下接合垫
305:上接合垫
307:垫间隙子
309:接合垫开孔
311:垫间隙子层
401:导电结构
403:上导电部
405:支撑部
405-1:下区段
405-2:上区段
407:导电部
409:间隙子
411:导电覆盖膜
413:导电部凹陷
415:间隙子层
417:导电结构开孔
419:导电覆盖层
501:重分布层
501-1:下交错区段
501-2:上交错区段
503:应力吸收层
505:重分布层开孔
601:第一遮罩层
603:第二遮罩层
605:第三遮罩层
607:第四遮罩层
609:第五遮罩层
611:第六遮罩层
613:第七遮罩层
701:清洗工艺
703:钝化工艺
S11:步骤
S13:步骤
S15:步骤
S17:步骤
W1:宽度
W2:宽度
W3:宽度
W4:宽度
W5:宽度
具体实施方式
以下描述了组件和配置的具体范例,以简化本公开的实施例。当然,这些实施例仅用以例示,并非意图限制本公开的范围。举例而言,在叙述中第一部件形成于第二部件之上,可能包含形成第一和第二部件直接接触的实施例,也可能包含额外的部件形成于第一和第二部件之间,使得第一和第二部件不会直接接触的实施例。另外,本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚,除非内文中特别说明,其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
理应理解,当形成一个部件在另一个部件之上(on)、与另一个部件相连(connected to)、及/或与另一个部件耦合(coupled to),其可能包含形成这些部件直接接触的实施例,并且也可能包含形成额外的部件介于这些部件之间,使得这些部件不会直接接触的实施例。
应当理解,尽管这里可以使用术语第一,第二,第三等来描述各种元件、部件、区域、层或区段(sections),但是这些元件、部件、区域、层或区段不受这些术语的限制。相反,这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此,在不脱离本发明进部性构思的教导的情况下,下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
除非内容中另有所指,否则当代表定向(orientation)、布局(layout)、位置(location)、形状(shapes)、尺寸(sizes)、数量(amounts),或其他测量(measures)时,则如在本文中所使用的例如“同样的(same)”、“相等的(equal)”、“平坦的(planar)”,或是“共面的(coplanar)”等术语(terms)并非必要意指一精确地完全相同的定向、布局、位置、形状、尺寸、数量,或其他测量,但其意指在可接受的差异内,是包含差不多完全相同的定向、布局、位置、形状、尺寸、数量,或其他测量,而举例来说,所述可接受的差异是可因为制造流程(manufacturing processes)而发生。术语“大致地(substantially)”是可被使用在本文中,以表现出此意思。举例来说,如大致地相同的(substantially the same)、大致地相等的(substantially equal),或是大致地平坦的(substantially planar),为精确地相同的、相等的,或是平坦的,或者是其是可为在可接受的差异内的相同的、相等的,或是平坦的,而举例来说,所述可接受的差异是可因为制造流程而发生。
在本公开中,一半导体元件通常意指可通过利用半导体特性(semiconductorcharacteristics)运行的一元件,而一光电元件(electro-optic device)、一发光显示元件(light-emitting display device)、一半导体线路(semiconductor circuit)以及一电子元件(electronic device),是均包括在半导体元件的范围中。
应当理解,在本公开的描述中,上方(above)(或之上(up))是对应Z方向箭头的该方向,而下方(below)(或之下(down))是对应Z方向箭头的相对方向。
图1为依据本公开一实施例中一种半导体元件100A的垂直剖视示意图。图2为依据本公开图1中沿剖线A-A’的一实施例该半导体元件100A的一部分的剖视示意图。图3为依据本公开图1中沿剖线B-B’的一实施例半导体元件100A的一部分的剖视示意图。为了清楚表示,本公开的半导体元件100A的一些部件并未显示在图1到图3中。
请参考图1到图3,在所述的实施例中,半导体元件100A可包括一半导体基底101、多个内连接膜(interconnection films)103、一第一钝化膜105、一第二钝化膜107、一第三钝化膜109、一第四钝化膜111、一应力释放结构201、一接合垫结构301以及一导电结构401。
请参考图1到图3,在所述的实施例中,举例来说,半导体基底101可由下列材料所形成:硅、锗、硅锗(silicon germanium)、碳化硅(silicon carbon)、碳化锗硅(silicongermanium carbon)、镓、砷化镓(gallium arsenide)、砷化铟(indium arsenic)、磷化铟(indium phosphorus)或其他IV-IV族、III-V族或II-VI族半导体材料。或者是,在其他实施例中,半导体基底101可包含一有机半导体或一层式半导体(layered semiconductor),例如硅/硅锗、绝缘层上覆硅(silicon-on-insulator)或绝缘层上覆硅锗(silicongermanium-on-insulator)。当半导体基底101由绝缘层上覆硅所制时,半导体基底101可包含由硅所制的一上半导体层与一下半导体层,以及一埋入隔离层,而埋入隔离层可将上半导体层与下半导体层分隔开。举例来说,埋入隔离层可包含一多晶硅或非晶硅氧化物、氮化物或其组合。例如晶体管、电容器以及内连接(interconnects)的部件(图未示)可设置在半导体基底101内。
请参考图1到图3,在所述的实施例中,多个内连接膜103可设置在半导体基底101上。多个内连接膜103可进一步当作是设置在半导体基底101内的不同部件的内连接。多个内连接膜103可包括多个隔离膜以及多个导电层,而多个导电层则设置在该多个隔离膜内。举例来说,该多个隔离膜可由氮化硅、氧化硅、氮氧化硅、流动氧化物(flowable oxide)、东燃硅氮烷(tonen tilazen)、未经掺杂硅玻璃(undoped silica glass)、硼硅玻璃(borosilica glass)、磷硅玻璃(phosphosilica glass)、硼磷硅玻璃(borophosphosilicaglass)、等离子体增强四乙氧基硅烷(plasma enhanced tetra ethyl orthosilicate)、硅氟玻璃(fluoride silicate glass)、碳掺杂氧化硅(carbon doped silicon oxide)、干凝胶(xerogel)、气凝胶(aerogel)、非晶氟化碳(amorphous fluorinated carbon)、有机硅玻璃(organo silicate glass)、聚对二甲苯(parylene)、双苯并环丁烯(bis-benzocyclobutenes)、聚酰亚胺(polyimide)、多孔聚合材料(porous polymericmaterial)或其组合所制,但并不以此为限。举例来说,该多个导电层可由一导电材料所制,例如掺杂多晶硅、金属、氮化金属或硅化金属。
应当理解,在本公开中,氮氧化硅是表示一物质,此物质是含有硅、氮以及氧,而其中氧的一比例大于氮的比例。而氧化氮化硅是表示一物质,此物质是含有硅、氮以及氧,而其中氮的一比例大于氧的比例。
请参考图1到图3,在所述的实施例中,第一钝化膜105可设置在多个内连接膜103上。第一钝化膜105可密封并保护多个内连接膜103以及设置在半导体基底101内的所述多个部件,避免损伤与污染(contamination)。举例来说,第一钝化膜105可由氧化硅、氮化硅、氮氧化硅、氧化氮化硅、聚酰亚胺(polyimide)、磷硅玻璃(phosphosilica glass)、未经掺杂硅玻璃(undoped silica glass)或硅氟玻璃(fluoride silicate glass)所制。
请参考图1到图3,在所述的实施例中,应力释放结构201可设置在半导体基底101上方,并位于第一钝化膜105中。应力释放结构201可具有一第一宽度W1。应力释放结构201可包括一导电架203以及多个隔离柱205。导电架203可设置在半导体基底101上方,并位于第一钝化膜105中。导电架203可具有与第一钝化膜105相同的一厚度。导电架203的一底部可设置在多个内连接膜103的一最上层膜的一顶表面上。导电架203的一水平剖面轮廓可为网状(mesh)。意即,导电架203的各组件可相互连接。在图1中的垂直剖面图中,可显示出导电架203的四个剖面组件。导电架203的每一剖面组件可具有一第四宽度W4。举例来说,导电架203可由一导电材料所制,例如金属、氮化金属或硅化金属。
请参考图1到图3,在所述的实施例中,多个隔离柱205可设置在导电架203内。多个隔离柱205可具有与第一钝化膜105相同的一厚度。多个隔离柱205的底部可设置在多个内连接膜103的最上层膜的顶表面上。多个隔离柱205的一水平剖面轮廓可为有规律对准的柱体(regularly-aligned pillars)。而多个隔离柱205的有规律对准的柱体可为矩形。或者是,在其他的实施例中,多个隔离柱205的有规律对准的柱体可为正方形、多边形或是椭圆形。多边形的形状可为三角形、矩形、梯形、平行四边形、菱形、五边形或六边形,但并不以此为限。多个隔离柱205可由与第一钝化膜105相同的一材料所制,但并不以此为限。或者是,在其他的实施例中,多个隔离柱205可由一材料所制,该材料包含聚酰亚胺(polyimide)或环氧基(epoxy-based)材料。应力释放结构201可当作是一减震垫(cushion),以减少一凸块工艺(bumping process)或一布线工艺(wiring process)的一应力(stress)。
请参考图1到图3,在所述的实施例中,第二钝化膜107可设置在第一钝化膜105上。第二钝化膜107的一底部可设置在应力释放结构201的一顶表面上。尤其是,第二钝化膜107的底部可设置在导电架201与多个隔离柱205的顶表面上。第二钝化膜107可由与第一钝化膜105相同的一材料所制,但并不以此为限。
请参考图1到图3,在所述的实施例中,第三钝化层109可设置在第二钝化层107上。第三钝化层109可具有一第三下钝化膜109-1以及一第三上钝化膜109-2。第三下钝化膜109-1可设置在第二钝化膜107上。第三下钝化膜109-1可由与第一钝化膜105相同的一材料所制,但并不以此为限。第三上钝化膜109-2可设置在第三下钝化膜109-1上。第三上钝化膜109-2可由与第一钝化膜105相同且与第三下钝化膜109-1不同的一材料所制,但并不以此为限。在所述的实施例中,举例来说,第三下钝化膜109-1可由氧化硅或磷硅玻璃(phosphosilica glass)所制。举例来说,第三上钝化层109-2可由氮化硅、氮氧化硅或氧化氮化硅所制。第三上钝化膜109-2可当作是一高气相阻障(high vapor barrier),以避免水气从上方进入。
请参考图1到图3,在所述的实施例中,接合垫结构301可设置在半导体基底101上方,并位于第三钝化膜109中。接合垫结构301可具有一第二宽度W2。接合垫结构301的第二宽度W2可大于应力释放结构201的第一宽度W1。接合垫结构301可包括一下接合垫303以及一上接合垫305。下接合垫303可设置在第二钝化膜107上,并位于第三下钝化膜109-1中。下接合垫303的一厚度可小于第三下钝化膜109-1的一厚度。下接合垫303可由含有镍的一材料所制。上接合垫305可设置在下接合垫303上,并位于第三下钝化膜109-1与第三上钝化膜109-2中。上接合垫305的一顶表面可齐平于第三上钝化膜109-2的一顶表面。上接合垫305可含有铂、钴或其组合。接合垫结构301可电性耦接到多个内连接膜103的各导电层(图未示)。
请参考图1到图3,在所述的实施例中,第四钝化膜111可设置在第三上钝化膜109-2上与上接合垫305的顶表面上。举例来说,第四钝化膜111可由氧化硅、氮化硅、氮氧化硅、氧化氮化硅、聚酰亚胺(polyimide)、磷硅玻璃(phosphosilica glass)、未经掺杂硅玻璃(undoped silica glass)、硅氟玻璃(fluoride silicate glass)、氧化钛、氧化铝、聚酰亚胺(polyimide)、聚苯并恶唑(polybenzoxazole)所制。
请参考图1到图3,在所述的实施例中,导电结构401的下部可设置在第四钝化膜111中,而导电结构401的上部可设置在第四钝化膜111的一顶表面上。导电结构401的下部可包括一图案化结构。图案化结构可设置在上接合垫305的顶表面上,并位于第四钝化膜111中。图案化结构的一顶表面可齐平于第四钝化层111的顶表面。图案化结构的一底部可具有一第三宽度W3。图案化结构的底部的第三宽度W3可小于接合垫结构301的第二宽度W2。图案化结构的底部的第三宽度W3可大于应力释放结构201的第一宽度W1。在所述的实施例中,图案化结构的一边界(boundary)可为圆形(circle)。或者是,在其他的实施例中,图案化结构的边界可为多边形或椭圆形。多边形可为三角形、矩形、梯形、平行四边形、菱形、五边形或六边形,但并不以此为限。
请参考图1到图3,在所述的实施例中,图案化结构包括一支撑部405、一导电部407以及多个间隙子409。支撑部405可设置在上接合垫305的顶表面上。支撑部405可具有与第四钝化膜111相同的一厚度。支撑部405的一顶表面可齐平于第四钝化膜111的顶表面。在所述的实施例中,支撑部405的一水平剖面轮廓可为网状。在图1中的垂直剖面图中,可显示出支撑部405的三个剖面部分。支撑部405的三个剖面部分可相隔地设置在上接合垫305上。支撑部405可由与第四钝化膜111相同的一材料所制,但并不以此为限。支撑部405可减少在封装工艺期间的应力,进而减少半导体元件100A的翘曲(warpage)。
请参考图1到图3,在所述的实施例中,导电部407可具有与第四钝化膜111相同的一厚度。举例来说,导电部407可由一材料所制,该材料包含锡、银、铜、金、合金或其组合。在所述的实施例中,导电部407的一水平剖面轮廓可为有规律对准的柱体。而有规律对准的柱体可为正方形。在图2中的顶视图中,支撑部405可围绕导电部407设置。
在图1中的垂直剖视图中,可显示出导电部407的四个剖面部分。导电部407的四个剖面部分可邻近支撑部405的三个剖面部分设置。尤其是,导电部407的四个剖面部分与支撑部405的三个剖面部分可交错地设置在上接合垫305上。导电部407的四个剖面部分的各底部可具有一第五宽度W5。导电部407的四个剖面部分的各底部的第五宽度W5可等于导电架203的各剖面组件的第四宽度W4。
请参考图1到图3,在所述的实施例中,导电部407可设置在导电架203上方。尤其是,导电部407的四个剖面部分可直接位于导电架203的四个剖面组件上方。据此,支撑部405可设置在多个隔离柱205上方。应当理解,导电架203的所述多个部分并没有与位于其上的导电部407相对应的部分。因此,支撑部405的所述多个部分并没有与位于其下的多个隔离柱205相对应的部分。
请参考图2,多个间隙子409可围绕导电部407设置,且支撑部405围绕多个间隙子409设置。在图1的垂直剖视图中,多个间隙子409可贴合到导电部407的四个剖面部分的两侧。多个间隙子409的底部可设置在上接合垫305的顶表面上。举例来说,多个间隙子409可由氧化硅、氮化硅、氮氧化硅或氧化氮化硅所制。
请参考图1到图3,在所述的实施例中,导电结构401的上部可具有一上导电部403。上导电部403可设置在支撑部405与导电部407的顶表面上。上导电部403可由与导电部407相同的一材料所制,但并不以此为限。导电结构401可当作是一剂体(agent),以将半导体元件100A机械地及电性地连接到用于封装的一基底。
在一布线工艺(wiring process)、形成一锡料凸块的一工艺或一封装工艺期间,会施加一应力(stress)在半导体元件,且该应力可造成多个内连接膜103的分层(delamination)。为了降低前述工艺的应力,导电结构401的支撑部405与直接位于导电结构401与接合垫结构301下方的应力释放结构201,可当作是一减震垫(cushion),以降低前述工艺的应力,减少半导体元件100A的翘曲(warpage),并避免在应力释放结构201下的多层被分层(delaminating)。
此外,应力释放结构201的导电架203的各组件相互连接,并可分散遍及整个导电架203的应力;因此,相较于一独立的抗应力结构(standalone anti-stress structure)而言,导电架203可提供一优选的应力缓冲(stress-buffering)能力。再者,由包含聚酰亚胺或环氧基材料所制的多个隔离柱205,可能够吸收与分散应力以进一步改善应力释放结构201的应力缓冲能力。此外,前述工艺的应力主要可沿着Z方向蔓延,而直接位于导电部407下方的导电架203可提供一更有效的方法,以释放前述工艺的应力。
图4到图6为依据本公开图1中沿剖线A-A’的另一实施例半导体元件100B、100C、100D的一部分的剖视示意图。图7到图8为依据本公开图1中沿剖线B-B’的另一实施例半导体元件100D、100E的一部分的剖视示意图。为了清楚表示,本公开的半导体元件100B、100C、100D、100E的一些部件并未显示在图4到图8中。
请参考图4,在半导体元件100B的一实施例中,支撑部405的一水平剖面轮廓可为有标准对准的柱体。而有标准对准的柱体可为矩形。导电部407的水平剖面轮廓可为网状。导电部407可围绕支撑部405设置。换言之,支撑部405可设置在导电部407内。多个间隙子409可分别对应围绕支撑部405设置。
请参考图5,在半导体元件100C的一实施例中,导电部407的水平剖面轮廓可为有标准对准的柱体。而有标准对准的柱体可为圆形。支撑部405的水平剖面轮廓可为网状。支撑部405可围绕导电部407设置。换言之,导电部407可设置在支撑部405内。而多个间隙子409可分别对应围绕导电部407设置。
请参考图6及图7,在半导体元件100D的一实施例中,导电部407的水平剖面轮廓可为同心环。支撑部405的水平剖面轮廓可为同心环。支撑部405与导电部407可交错设置在上接合垫305上。多个间隙子409可分别对应围绕导电部407与支撑部405设置。导电架230的水平剖面轮廓可为同心环。导电架203可直接位于导电部407的下方。多个隔离柱205的水平剖面轮廓可为同心环。导电架203与多个隔离柱205可交错设置在多个内连接结构103上。
请参考图8,在半导体元件100E的一实施例中,导电架203的水平剖面轮廓可为类似方向盘(steering wheel)的形状。意即,导电架203的一外圆与导电架203的一内圆可通过至少一连接组件203-1而连接。因此,可改善导电架203的应力释放能力。
图9到图15为依据本公开一实施例中各半导体元件100F、100G、100H、100I、100J、100K、100L的垂直剖视示意图。
请参考图9,半导体元件100F可包括一对(pair)垫间隙子307。该对垫间隙子307可贴合到接合垫结构301的两侧。换言之,该对垫间隙子307可贴合到上接合垫305与下接合垫303的各侧壁。该对垫间隙子307可绝缘第三下钝化膜109-1与第三上钝化膜109-2的各侧壁,以避免不良的侧壁生长。
请参考图10,半导体元件100G可包括一导电覆盖膜411。导电覆盖膜411可覆盖多个间隙子409、上接合垫305的顶表面的一些部分以及支撑部405的一顶表面。导电覆盖膜411可设置在多个间隙子409与导电部407之间,以及设置在上导电部403与支撑部405之间。导电覆盖膜411可当作是一阻障(barrier),以在布线工艺、形成一焊料凸块的一工艺或一封装工艺期间保护接合垫结构301。举例来说,导电覆盖膜411可由一导电材料所制,例如铜、铝、镍、钛、氮化钛、氮化钨、锡,银、金、铬、合金或其组合。
请参考图11,在半导体元件100H的一实施例中,第四钝化膜111可为一堆叠膜,包括一第四下钝化膜111-1以及一第四上钝化膜111-2。第四下钝化膜111-1可设置在第三上钝化膜109-2与上接合垫305上。第四上钝化膜111-2可设置在第四下钝化膜111-1上。该第四下钝化膜111-1与第四上钝化膜111-2可由与第一钝化膜105相同的一材料所制,但并不以此为限。然而,第四下钝化膜111-1可由与第四上钝化膜111-2不同的一材料所制。
请参考图12并相较于图11,在半导体元件100I的一实施例中,支撑部405可包括一下区段405-1以及一上区段405-2。下区段405-1可设置在上接合垫305上,并在与第四下钝化层111-1相同的一垂直水平面处。上区段405-2可设置在下区段405-1上,并在与第四上钝化膜111-2相同的一垂直水平面处。下区段405-1可由与下区段405-2不同的一材料所制,并可与第四下钝化膜111-1相同的一材料所制。上区段405-2可由与第四上钝化膜111-2相同的一材料所制。下区段405-1与上区段405-2可分别对应从第四下钝化膜111-1与第四上钝化膜111-2形成。
请参考图13,半导体元件100J可包括一重分布层501。重分布层501可设置在第三钝化膜109中,并通过一导电栓塞(conductive plug)115而电性耦接到设置在多个内连接结构103中的一最上层的导电层113。重分布层501的一端可接触接合垫结构301。重分布层501的一相对端可延伸一距离以水平远离接合垫结构301。举例来说,重分布层501可由锡、镍、铜、金、铝或其合金所制。
请参考图14,半导体元件100K可包括一应力吸收层503。应力吸收层503可设置在第三钝化膜109与第一钝化膜105之间。应力吸收层503的一顶表面可接触第三下钝化膜109-1的一底部。应力吸收层503的一底部可接触第一钝化膜105与应力释放结构201的顶表面。应力吸收层503可用于吸收并分散应力,该应力是集中在多个下层,并由剪应力(shearstresses)所产生,而所述多个剪应力是由于一布线工艺、形成一焊料凸块的一工艺或一封装工艺的热膨胀错置(thermal expansion mismatches)与一般应力(normal stresses)所产生。举例来说,应力吸收层503可由一材料所制,该材料具有一热膨胀系数以及一杨氏模量(Young’s Modulus),而热膨胀系数小于约20ppm/℃,而杨氏模量小于约15GPa。尤其是,应力吸收层503可由一材料所制,该材料包含聚酰亚胺(polyimide)或环氧基(epoxy-based)材料。应力吸收层503可具有一厚度,介于0.5μm到1.0μm之间。优选者,应力吸收层503的厚度可介于到/>之间。
请参考图15,在半导体元件100L的一实施例中,应力吸收层503可设置在第二钝化膜107中,并位于接合垫结构301与应力释放结构201之间。重分布层501可包括一下交错区段(lower staggered segment)501-1以及一上交错区段501-2。下交错区段501-1可设置在第二钝化膜107中,并可远离应力吸收层503设置。上交错区段501-2可设置在第三钝化膜109中。上交错区段501-2的一端可接触接合垫结构301。上交错区段501-2的一相对端可水平延伸一距离以远离接合垫结构301,并接触下交错区段501-1的一顶表面的一部分。
图16为依据本公开一实施例中一种半导体元件100A的制备方法10的流程示意图。图17到图20为依据本公开一实施例中制备半导体元件100A流程的某部分的剖视示意图。图21为依据本公开图20中沿剖线A-A’的制备半导体元件100A流程的某部分的剖视示意图。图22到图30为依据本公开一实施例中制备半导体元件100A流程的某部分的剖视示意图。
请参考图16与图17,在步骤S11,在所述的实施例中,可提供一半导体基底101,且多个内连接膜103与一第一钝化膜105可按序形成在半导体基底101上。例如晶体管、电容器以及内连接的部件(图未示)可设置在半导体基底101内。多个内连接膜103可适于进一步内连接设置在半导体基底101内的不同部件(elements)。
请参考图16以及图18到图21,在步骤S13,在所述的实施例中,一应力释放结构201可形成在半导体基底101上,并位于第一钝化膜105中。应力释放结构201可包括一导电架203与多个隔离柱205。请参考图18,可执行一光刻工艺,该光刻工艺使用一第一遮罩层601当作一遮罩,以界定出位于第一钝化膜105上的应力释放结构201的位置。请参考图19,在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成一导电架开孔207在第一钝化膜105中。多个内连接膜103的一最上层膜的一顶表面的一些部分可通过导电架通孔207而暴露。应当理解,并没有导电层通过导电架通孔207而暴露。
请参考图20与图21,举例来说,金属、氮化金属或硅化金属的一导电材料可通过一金属化工艺而沉积在导电架开孔207中。在金属化工艺之后,可执行一平坦化工艺,该平坦化工艺例如化学机械研磨,以移除多余的材料,提供一大致平坦表面给接下来的处理步骤,并同时形成导电架203与多个隔离柱205。导电架203与多个隔离柱205一起形成应力释放结构201。应力释放结构201可具有一第一宽度W1。
请参考图16以及图22到图25,在步骤S15,在所述的实施例中,一接合垫结构301可形成在应力释放结构201上方。接合垫结构301可包括一下接合垫303以及一上接合垫305。请参考图22,一第三下钝化膜109-1以及一第三上钝化膜109-2可通过沉积工艺而按序形成在第二钝化膜107上。第三下钝化膜109-1与第三上钝化膜109-2一起形成第三钝化膜109。可执行一光刻工艺,该光刻工艺使用一第二遮罩层603当作是一遮罩,以界定出接合垫结构301位于第三上钝化膜109-2上的一位置。在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成一接合垫开孔309,以便穿透第三上钝化膜109-2与第三下钝化膜109-1。第二钝化膜107的一顶表面的一部分可通过接合垫开孔309而暴露。接合垫开孔309可形成在应力释放结构201上方,并具有一第二宽度W2。接合垫开孔309的第二宽度W2可大于应力释放结构201的第一宽度W1。
请参考图23,在前述蚀刻工艺之后,可执行一清洗工艺701。清洗工艺701可包括把氢与氩的一混合物当作一远距离等离子体源(remote plasma siurce),在工艺温度介于250℃至350℃之间,一工艺压力介于1Torr至10Torr之间,以及供应给设备执行清洗工艺701的一偏压能量(bias energy)的存在条件下。偏压能量可介于0W至200W之间。清洗工艺701可移除在一导电层通过接合垫开孔309而暴露的顶表面上的氧化物,而不会损害到前述导电层的导电特征,而该氧化物是始源于在空气中的氧气的氧化。
请参考图24,一钝化工艺703可执行在第三上钝化膜109-2与接合垫开孔309上方。钝化工艺703可包括浸渍半导体元件在一前驱物中,其中该前驱物为三甲硅基二甲胺(dimethylaminotrimethylsilane)、四甲基硅烷(tetramethylsilane),或其类似物,是在一工艺温度介于200℃至400℃之间。可使用一紫外线辐射以促进钝化工艺703。钝化工艺703可钝化第三下钝化层109-1以及第三上钝化层109-2经由接合垫开孔309而暴露的各侧壁,其是通过密封其表面毛孔以降低不合适的侧壁生长,其是在接下来的处理步骤期间,可影响半导体元件100A的电子效能。因此,可提升半导体元件100A的效能与可靠度。请参考图25,下接合垫303与上接合垫305可通过电镀或无电电镀而按序形成在接合垫开孔309中。可选择地执行一平坦化工艺,该平坦化工艺例如化学机下研磨,以提供一大致平坦表面给接下来的处理步骤。
请参考图16以及图26到图30,在步骤S17,在所述的实施例中,一导电结构401可形成在接合垫结构301上。导电结构401可包括一上导电部403以及一图案化结构。图案化结构可包括一支撑部405、一导电部407以及多个间隙子409。请参考图26,一第四钝化膜111可形成在第三上钝化膜109-2与接合垫结构301上。可执行一光刻工艺,该光刻工艺使用一第三遮罩层605当作一遮罩,以皆订出图案化结构位于第四钝化膜111上的一位置。
请参考图27,在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成多个导电部凹陷413在第四钝化膜111中。上接合垫305的一顶表面的一些部分可通过多个导电部凹陷413而暴露。在蚀刻工艺之后,第四钝化膜111的一些部分可转换成支撑部405。请参考图28,可形成一间隙子层415以覆盖第四钝化膜111的一顶表面、支撑部405的一顶表面以及多个导电部凹陷413的各侧壁与各底部。举例来说,间隙子层415可由氧化硅、氮化硅、氮氧化硅或氧化氮化硅所制。
请参考图29,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以移除间隙子层415的一些部分,并同时形成多个间隙子409。形成多个间隙子408以便贴合到多个导电部凹陷413的侧壁。请参考图30,导电部407与上导电部403可通过一工艺而同时形成,该工艺例如化学气相沉积、物理气相沉积、原子层沉积、等离子体加强化学气相沉积、电镀或无电电镀。可形成导电部407以充填多个导电部凹陷413。上导电部403可形成在支撑部405与导电部407上。
图31到图33为依据本公开另一实施例中制备半导体元件流程的某部分的剖视示意图。
请参考图31,一中间阶段的半导体元件可通过类似于图17到图26所图例的一工艺所制造。可执行一光刻工艺,该光刻工艺使用一第四遮罩层607当作遮罩,以界定出图案化结构的位置。请参考图32,在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成一导电结构开孔417。导电结构开孔407可具有一第三宽度W3。一水平剖面轮廓可为多边形、圆形或椭圆形。请参考图33,支撑部405可形成在导电结构开孔417中。而半导体元件的其他部分可通过类似于图28到图30所图例的一工艺而按序形成。
图34到图36为依据本公开另一实施例中制备半导体元件流程的某部分的剖视示意图。
请参考图34,一中间阶段的半导体元件可通过类似于图17到图23所图例的一工艺所制造。可形成一垫间隙子层311以覆盖第三上钝化膜109-2的顶表面以及接合垫开孔309的侧壁与一底部。请参考图35,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以移除垫间隙子层311的一些部分,并同时形成贴合到接合垫开孔309的侧壁的该对(pair)垫间隙子307。请参考图36,下接合垫303与上接合垫305可按序形成在接合垫开孔309中,并位于该对垫间隙子307之间。半导体元件的其他部分可通过类似于图25到图30所图例的一工艺而按序形成。
图37及图38为依据本公开另一实施例中制备半导体元件流程的某部分的剖视示意图。
请参考图37,一中间阶段的半导体元件可通过类似于图17到图29所图例的一工艺所制造。可形成一导电覆盖层419以覆盖第四钝化膜111的顶表面、多个间隙子409、支撑部405的顶表面以及上接合垫305的顶表面的所述多个部分。可执行一光刻工艺,该光刻工艺使用一第五遮罩层609当作遮罩,以界定出导电覆盖膜411的一位置。请参考图38,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以移除导电覆盖层419的一些部分,并同时形成导电覆盖膜411。半导体元件的其他部分可通过类似于图30所图例的一工艺而按序形成。
图39到图45为依据本公开另一实施例中制备半导体元件流程的某部分的剖视示意图。
请参考图39,一中间阶段的半导体元件可通过类似于图17到图21所图例的一工艺所制造。应力吸收层503可通过一沉积工艺而形成在第一钝化膜105上,该沉积工艺例如化学气相沉积。请参考图40,可形成导电栓塞115以便穿透应力吸收层503与第一钝化膜105,并电性连接到最上层的导电层113。请参考图41,第三下钝化膜109-1与第三上钝化膜109-2可按序形成在应力吸收层503上。可执行一光刻工艺,该光刻工艺使用一第六遮罩层611当作遮罩,以界定出重分布层501在第三上钝化膜109-2上的一位置。请参考图42,在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成一重分布层开孔505,以便穿透第三上钝化膜109-2与第三下钝化膜109-1。
请参考图43,一导电材料可通过一金属化工艺而沉积到重分布层开孔505中。在金属化工艺之后,可执行一平坦化工艺,该平坦化工艺例如化学机械研磨,以移除多于材料,提供一大致平坦表面给接下来的处理步骤,并同时形成重分布层501。可执行一光刻工艺,该光刻工艺使用一第七遮罩层613当作遮罩,以界定出接合垫结构301位于第三上钝化膜109-2上的位置。
请参考图44,在光刻工艺之后,可执行一蚀刻工艺,该蚀刻工艺例如一非等向性干蚀刻工艺,以形成接合垫开孔309,以便穿透第三上钝化膜109-2与第三下钝化膜109-1。请参考图45,下接合垫303与上接合垫305可按序形成在接合垫开孔309中,并电性连接到重分布层501。半导体元件的其他部分可通过类似于图26到图30所图例的一工艺而按序形成。
由于本公开该半导体元件的设计,可通过导电结构401的支撑部405以及应力释放结构201,以减少源自于一布线工艺(wiring process)、形成一焊料凸块(solder bump)的工艺或是一封装工艺(package process)的应力。结果,可避免该半导体元件的破裂(cracking)或是多个内连接膜103的分层(delamination)。因此,可改善半导体元件的良率或可靠度。
虽然已详述本公开及其优点,然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如,可用不同的方法实施上述的许多工艺,并且以其他工艺或其组合替代上述的许多工艺。
再者,本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此,这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。
Claims (20)
1.一种半导体元件,包括:
一半导体基底;
一应力释放结构,包括一导电架以及多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内;以及
一导电结构,包括一支撑部、一导电部以及多个间隙子,该支撑部位于该应力释放结构上,该导电部邻近该支撑部设置,该多个间隙子贴合到该导电部的两侧;
其中该导电架的一宽度等于该导电部的一底部的一宽度。
2.如权利要求1所述的半导体元件,其中该导电部位于该导电架上。
3.如权利要求2所述的半导体元件,其中该导电结构的一底部的一宽度大于该应力释放结构的一宽度。
4.如权利要求3所述的半导体元件,还包括一接合垫结构,位于该导电结构与该应力释放结构之间,其中该接合垫结构的一顶表面接触该导电部的该底部。
5.如权利要求4所述的半导体元件,其中该接合垫结构包括一下接合垫以及一上接合垫,该下接合垫位于该导电结构与该应力释放结构之间,该上接合垫位于该下接合垫上,其中该上接合垫的一顶表面接触该导电部的该底部。
6.如权利要求5所述的半导体元件,其中该接合垫结构的一宽度大于该导电部的该底部的该宽度。
7.如权利要求6所述的半导体元件,其中该导电结构包括一上导电部,位于该支撑部与该导电部上。
8.如权利要求7所述的半导体元件,还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该接合垫结构位于该下钝化膜与该上钝化膜中。
9.如权利要求7所述的半导体元件,还包括一对垫间隙子,贴合到该接合垫结构的两侧。
10.如权利要求7所述的半导体元件,还包括一导电覆盖膜,覆盖该多个间隙子、该上接合垫的该顶表面的一部分以及该支撑部的一顶表面。
11.如权利要求7所述的半导体元件,还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该支撑部与该导电部位于该下钝化膜与该上钝化膜中。
12.如权利要求7所述的半导体元件,还包括一下钝化膜以及一上钝化膜,该下钝化膜位于该半导体基底上,该上钝化膜位于该下钝化膜上,其中该支撑部与该导电部位于该下钝化膜与该上钝化膜中,且该支撑部包括一下区段以及一上区段,该下区段位于与该下钝化膜相同的一垂直水平面处,该上区段位于该下区段上,并位于与该上钝化膜相同的一垂直水平面处。
13.如权利要求7所述的半导体元件,其中该导电架的一水平剖面轮廓为网状、同心环或方向盘的形状。
14.如权利要求7所述的半导体元件,其中该支撑部的一水平剖面轮廓为网状、有规律对准的柱体或同心环。
15.如权利要求7所述的半导体元件,还包括一重分布层,位于该半导体基底上,并电性耦接到该接合垫结构。
16.如权利要求7所述的半导体元件,还包括一应力吸收层,位于该应力释放结构与该接合垫结构之间,其中该应力吸收层由一材料所制,该材料具有一热膨胀系数以及一杨氏模量,该热膨胀系数小于20ppm/℃,而该杨氏模量小于15GPa。
17.如权利要求16所述的半导体元件,还包括一重分布层,位于该应力吸收层上,并电性耦接到该接合垫结构。
18.如权利要求16所述的半导体元件,还包括一重分布层,位于该半导体基底上,其中该重分布层包括一下交错区段以及一上交错区段,该下交错区段位于与该应力吸收层相同的一垂直水平面处,该上交错区段位于该下交错区段上,并邻近该接合垫结构设置。
19.一种半导体元件的制备方法,包括:
提供一半导体基底;
形成一应力释放结构,包括一导电架以及多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内;以及
形成一导电结构,该导电结构包括一支撑部、一导电部以及多个间隙子,该支撑部位于该应力释放结构上,该导电部邻近该支撑部设置,该多个间隙子贴合到该导电部的两侧。
20.如权利要求19所述的半导体元件的制备方法,其中该应力释放结构包括该导电架以及该多个隔离柱,该导电架位于该半导体基底上,该多个隔离柱位于该导电架内,形成该应力释放结构的步骤包括:
形成一第一钝化膜在该半导体基底上;
执行一光刻工艺以界定出该应力释放结构位于该第一钝化膜上的一位置;
执行一蚀刻工艺以形成一导电架开孔在该第一钝化膜中;
沉积一导电材料在该导电架开孔中;以及
执行一平坦化工艺以同时形成该导电架与多个隔离柱。
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