CN102576699A - 包含形成于低k金属化系统上的应力缓冲材料的半导体装置 - Google Patents

包含形成于低k金属化系统上的应力缓冲材料的半导体装置 Download PDF

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CN102576699A
CN102576699A CN2010800386505A CN201080038650A CN102576699A CN 102576699 A CN102576699 A CN 102576699A CN 2010800386505 A CN2010800386505 A CN 2010800386505A CN 201080038650 A CN201080038650 A CN 201080038650A CN 102576699 A CN102576699 A CN 102576699A
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semiconductor device
layer
metal
opening
buffer area
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A·沃尔特
M·列
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GlobalFoundries Inc
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GlobalFoundries Inc
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Abstract

形成在复杂的半导体装置的金属化系统上的凸块结构或柱状结构可以包含应力缓冲层(260)，该应力缓冲层可以有效地分散典型可能在芯片封装件交互作用期间因为上述组件之热失配所产生的机械应力。应力缓冲层(260)包括覆盖整体表面中显著部份的铜基缓冲区域(265)，其中亦可以使用约3至10μm的厚度。此外，该缓冲区域(265)可以有效地取代铝而做为终端金属主动区域。

Description

包含形成于低K金属化系统上的应力缓冲材料的半导体装置
技术领域
一般而言，本发明是关于集成电路，尤其是关于减低因芯片与封装件间的热失配所引起的芯片-封装件交互作用的技术。
背景技术
半导体装置典型形成于使用任何适当材料所制成的大致碟形基板上。目前(及可预见的未来)大多数包含高度复杂电子电路的半导体装置以硅为基础制造，从而使得硅基板及含硅基板(譬如绝缘体上覆硅(SOI)的基板)成为形成半导体装置(譬如微处理器、静态随机存取内存(SRAM)、特殊应用集成电路(ASIC)、系统单芯片(SoC)等等)的可行的基础材料。个别的集成电路被配置于晶片上的阵列中，其中，除了光学微影制程、量测制程与切割基板后个别装置的封装外，大部分的制造步骤(可能包含在精密的集成电路中数百道或更多的独立制程步骤)是同时实施于基板上全部的芯片区域。因此，经济的限制驱使半导体制造者不断地增加基板尺寸，从而亦增加了制造实际半导体装置的可用面积，并因此增加生产良率。
除增加基板面积之外，对于给定的基板尺寸最佳化基板面积的利用亦很重要，以便实际上尽可能多将基板面积用于半导体装置及/或可以用于制程控制的测试结构。在试图最大化既定基板尺寸下的有效表面面积上，电路组件的特征尺寸被不断地按比例缩小。由于此持续缩小高精密半导体装置中特征尺寸的需求，所以铜结合低k介电材料已经变成形成所谓的互连结构(包括金属线层及中间贯孔层)所经常使用之替代方案，其中，金属线做为层内连接线而贯孔做为层间连接线，该层内连接线与层间连接线共同地连接个别的电路组件以提供集成电路所需之功能性。典型地，堆栈在彼此顶部上的多个金属线层与贯孔层必须执行所有内部电路组件与I/O(输入/输出)，电路设计中所考虑的电源及接地垫片之间的连接。
对极度微缩之集成电路而言，讯号传递延迟不再受限于电路组件(譬如场效应晶体管等)，而是由于甚至需要增加更多电性连接数量的电路组件的密度增加，而受限于紧密相邻的金属线，这是因为线间电容(line-to-line capacitance)增加以及剖面面积减小导致线的导电性降低的缘故。为了此原因，传统之介电质(譬如二氧化硅(k＞4)和氮化硅(k＞7))被具有较低介电系数之介电材料取代，因其具有3或更小的相对介电系数亦被称为低k介电质。然而，低k材料的密度及机械稳定性或强度相较于充分验证过的介电质二氧化硅和氮化硅明显地较低。结果，在形成金属化系统及集成电路的任何后续制程期间，生产良率可视这些敏感的介电材料及其与其它材料间之粘着力而定。
除具有介电常数3和明显较小的先进介电材料的机械稳定性减低的问题外，在精密半导体装置运作之期间，装置可靠度可以被这些材料所影响，这是因为芯片和封装件间的交互作用被不同材料所对应之热膨胀间的热失配所引发的缘故。举例而言，于制造复杂的集成电路时，逐渐地，接触技术(contact technology)可用在连接封装件载体和芯片，其已知为覆晶封装技术。相反于广为接受的导线接合技术中，其适当之接触垫片可能被放置在芯片周边的最后一层金属层，透过导线与封装件上对应之端子连接，在覆晶技术中，可以在最后一层金属化层上形成各自的凸块结构，譬如，使用铝作为终端金属并结合能与封装件的各接触垫片接触的焊接材料。因此，凸块材料经过回焊后，即可以在形成于最后金属化层上的终端金属和封装件载体的接触垫片间建立可靠的电性和机械连接。以此方法，可以在最后金属化层上遍及整片芯片面积地设置非常大量的电性连接并具有减小的接触电阻与寄生电容，因而提供复杂的集成电路(譬如中央处理器(CPU)、储存内存等等)可能所需之IO(输入/输出)能力。在连接凸块结构和封装件载体之对应制程顺序期间，某种程度的压力和/或热可能会施加于该复合装置上，以便于芯片上所形成的每一个凸块和可以配置在封装件基板上的凸块或垫片间建立可靠的连接。然而，热或机械引发的应力亦可以作用在位于下方的金属化层，该下方金属化层典型可以包含低k介电质或甚至超低k(ultra low-k，ULK)介电材料，由于机械稳定性及与其它材料的粘着力降低，因而明显地增加了产生微裂、脱层等形式之缺陷的机率。
此外，于将已完成的半导体装置粘附至相对应的封装件基板的操作期间，由于硅基半导体芯片与封装件基板间的热膨胀行为明显的不匹配，而可能产生显著的机械应力，因为于精密集成电路之大量生产中，经济的限制对于封装件典型地要求使用特定的基板材料(譬如有机材料)，该材料相较于硅芯片典型可能呈现不同的热传导率及热膨胀系数。
参照图1a至1b，现在将更详尽说明包含焊料凸块结构的半导体装置的典型习知配置。
图1a示意地阐示了半导体装置100的配置或布局的上视图，于半导体装置100中，根据焊料凸块结构，将于封装件与装置100(亦即，特定的芯片或晶粒101)间建立机械与电性连接。为了此目的，可适当地分布接触组件110遍及于晶粒101的整个面积，其中，如先前所讨论者，几乎整个晶粒101的面积可有效地用于适切地放置接触组件110。以此方法，可以完成非常复杂的接触结构，其中每一接触组件110于单一制程期间可以连接至对应封装件基板上相对的接触垫片或凸块，与可能必须以实质连续之方法将接合导线连接至芯片与封装件上之接合垫片的相对应导线接合技术相反。
图1b示意地例示根据图1a中线Ib的装置100的剖面图。如所例示，装置100包括晶粒或芯片101，该晶粒或芯片101可以理解为用以在其上形成电路组件等的基础基板。基板101典型以绝缘基板、半导体材料等等形式设置。应该了解到，在基板101之中或之上，典型有多个电路组件(譬如晶体管、电容器、电阻器等等)以符合于装置100中待执行的电路功能设置。为了方便起见，于图1b中不会显示任何在精密装置中所可能包含具有关键尺寸为50纳米或更小的任何电路组件。如上述所讨论，由于半导体装置100中所实施之电子电路的复杂布局，典型需要复杂的金属化系统120，该金属化系统120包括多个堆栈于彼此顶部之金属化层，其中，为了方便起见，描绘了金属化层130和金属化层140。举例而言，金属化层130可包括介电材料131(例如低k材料、超低k材料等等)，典型包括铜并结合适当导电阻障材料以提供可靠的铜限制(copper confinement)之金属线和贯孔132则内嵌于该介电材料131中。应该理解到，于系统120中之各金属化层可以不需要包括敏感的低k介电材料，因为不同的金属化层可能需要不同的效能特性，例如驱动电流之能力和讯号传递延迟者。然而，无论如何，典型可能有多个金属化层包括敏感的低k介电材料，从而降低了整体的机械稳定性，如上述讨论。再者，金属化层140表示“最后”金属化层并包括含有金属区域142的任何适当的介电材料141，该金属区域142可以表示连接至接触结构或凸块结构150之接触垫片，该接触或凸块结构150可以实际表示连接装置100与封装件基板(未图标)的接口。接触或凸块结构150典型包括钝化层151，该钝化层151因此可以“钝化”该金属化系统120，其中，典型有多种介电材料(例如二氧化硅、氮氧化硅、氮化硅)鉴于其化学及机械稳定性，被使用来提供所希望的特性。而且，譬如聚亚醯胺152，有另外的介电材料形成在钝化层151上。该材料151和152会以譬如将150A之开口对准最后金属化层140中之接触垫片142的至少一部分的方式图案化。如先前所说明，铜倾向被使用于例如系统120之精密金属化系统，然而，铜可能不兼容于广为接受之制程技术与材料，其中，该制程技术与材料已经用根据铝形成的复杂金属化系统中。为了此原因，通常，其它的金属材料153，亦称为终端金属，会以铝之形式做为垫片142的敏感铜材料与接触组件110间的接口。以此方法，广为接受之材料与技术可以被应用于形成接触组件110，例如藉由提供如基于铬、铜、钨等等之有效的凸块下(underbump)金属化系统154。
另一方面，提供铝做为终端金属153，在实际形成接触组件110之前，可能需要额外的资源来沉积、图案化及清洁装置100。也就是说，依据广为接受的制程技术形成金属化系统120之后，沉积并图案化钝化层材料151，随后沉积铝材料，该铝材料可以与适当的阻障材料之沉积相关联，例如钛、氮化钛等等。之后，可以用例如溴等等为基础之蚀刻化学剂实施复杂的图案化制程。因此，为了提供终端金属153，需要对应的先驱物材料与沉积及蚀刻工具。其后，广为接受的制程顺序用以沉积聚亚醯胺材料152并同样图案化该聚亚醯胺材料152，随后再沉积凸块下材料154。之后，典型地应用沉积掩模并根据电镀技术沉积含铅材料形式之焊料凸块材料，随后移除沉积掩模并图案化凸块下材料154。于分割半导体装置100成个别的芯片101之后，与适当的封装件基板之连接可藉由机械性地耦接装置100和封装基板并且回焊接触组件110来完成，从而得到组件110与封装件基板上相对应的接触垫片间所希望的介金属连接(intermetallic connection)，该介金属连接根据整体制程策略亦可以包括焊料凸块。最后，任何适当的填充材料可以用于芯片101，亦即接触结构150和封装件基板之间，以便增强复合装置的机械、化学及热稳定性。
如上述讨论，于形成装置100期间，在连接装置100与封装基板之制程期间，以及最后在复合半导体装置运作过程中，显著的机械应力可以透过接触结构150(亦即，透过接触组件110)铺设于金属化系统120，其中接触组件110(亦即，含铅焊接材料)某程度的回弹性可能造成某程度的“缓冲效果”。
然而，例如鉴于环保法规等等而引进所谓的无铅焊接材料，以及倾向进一步改善接触结构150之热与电性效能，例如提供铜柱代替接触组件110，金属化系统120中之机械应力可能甚至进一步的加强，这是因为，典型上这些材料可能呈现较低程度的回弹性，从而将显著增加的剪力传递至最后金属化层140中。
因此，于许多已习知的方法中，于金属化系统120中增加的机械应力可能需要使用具有优越机械稳定性的介电材料，然而，从而典型地增加介电常数并因此降低金属化系统120的整体电性效能。
本揭示发明是关于可以避免、或者至少降低上述发现的一个或多个问题的影响的各种方法与装置。
发明内容
下文提出本发明的简单概述，以便提供本文中说明某些态样的基本了解。本概述并非本发明权利要求的详尽综论。其无意用来定义本发明中关键或重要之元件或描绘本发明的权利要求。其唯一目的是以简化形式提出本权利要求标的的某些概念做为后续更详尽说明的引言。
一般而言，本揭示发明提供半导体装置与制造技术，于此装置或技术中，可以通过设置缓冲层，调解或“缓冲”透过根据无铅材料形成的接触结构传递至复杂集成电路的金属化系统的机械应力。该缓冲层包含增加横向尺寸的“厚”缓冲区域，于该区域形成相对应之焊料凸块或金属柱。以此方法，因将半导体芯片连接至封装件基板时以及该复合半导体装置运作时所引起的机械应力，可以有效地实质分布遍及芯片的整个表面面积，而不需要特别修正金属化系统，例如，减少设置于该金属系统中之低k介电材料之量。于本文所揭示之一些例示态样中，该缓冲层可以根据铜而不使用铝来形成，从而避免了使用铝做为终端金属时典型可能必须之任何资源需求。为了此目的，可以形成缓冲区以便与金属化系统中最后金属化层的各自接触垫片连接，其中，铜接触区域所增加之横向与垂直尺寸可以对任何半导体芯片与芯片封装件间的热失配提供所希望之机械反应。
本文所揭示之一个例示的半导体装置包括形成于基板上的金属化系统，其中，该金属化系统包括多个金属化层，而其中至少一部份金属化层包括低k介电材料。该半导体装置进一步包括形成于该金属化系统的最后金属化层上的应力缓冲层，其中该应力缓冲层包括连接至设置在该金属化系统的最后金属化层所提供之含铜连接垫片的含铜缓冲区域。该装置更包括形成在一部分该含铜缓冲区域上的无铅接触组件。而且，该装置包括透过无铅接触组件与金属化系统连接之封装件基板。
本案所揭示的一个例示方法包括于半导体装置的金属化系统上所形成的钝化层中形成第一开口，其中该金属化系统包括具有接触垫片之最后金属化层，该接触垫片对准于第一开口。该方法进一步包括于钝化层上形成沉积掩模，其中，该沉积掩模包括对准于第一开口的第二开口。此外，含铜材料形成于该第一与第二开口中，然后将沉积掩模移除。而且，该方法包括形成接触组件于一部分的该含铜材料上。
本案所揭示之另一种例示方法是关于半导体装置的形成。该方法包括于金属化系统的最后金属化层上形成钝化层，其中，该钝化层包括多个第一开口以便与最后金属化层上所形成之含铜接触垫片连接。该方法进一步包括于该钝化层上形成牺牲的沉积掩模，其中，该牺牲的沉积掩模包括多个第二开口以便暴露多个第一开口。此外，根据该第一与第二开口形成多个横向分离的含铜区域。而且，移除该牺牲的沉积掩模并且于该含铜区域上形成介电材料堆栈。另外，该方法包括于介电材料堆栈中形成多个第三开口以便暴露至少一部份的该第一开口，其中该第三开口的横向尺寸小于该第二开口的横向尺寸。
附图说明
藉由参照以下叙述结合随附图式可以了解本发明，各图中相同之组件编号识别相似之组件，且其中：
图1a示意地显示依照所希望的布局在其上形成具有焊接凸块结构的半导体装置的上视图；
图1b示意地显示习知之半导体装置的剖面图，该装置包含根据铝做为终端金属以及含铅焊接材料的精密的金属化系统与凸块结构；
图2a示意地显示依照例示的实施例包含连接至封装件基板的接触结构的半导体装置的上视图，其中，可提供于横向尺寸增加的含铜缓冲区域内所希望之布局以便降低传递至下覆盖金属化系统的机械应力；以及
图2b至2i示意地显示依照另外的例示实施例，图2a的半导体装置于形成接触结构并且连接该接触结构至封装件基板的各个制造阶段期间的剖面图。
虽然本文中所揭示之标的容许各种修饰与替代形式，但是本发明的特定实施例已经由图式举例之方式显示，并且在本文中做了详细说明。然而，应该了解到本文中对于特定实施例之图标与详细说明并不欲限制本发明于所揭示之特定的形式，反之，本发明将涵盖所有落于由所附的权利要求所界定之精神与范围内之所有的修饰、等效和改变。
具体实施方式
以下叙述本发明的各种例示实施例。为求清楚，本说明书并未描述实际实作的所有特征。当然，必须了解到于任何这类实际实施例的开发中，必须做许多实作限定的决定以达成开发者的特定目标，例如遵守系统相关或商业相关的限制，这些决定将随实作而变化。此外，必须了解到，此种开发工作量可能是复杂且耗时的，不过这对藉助于此揭露内容的该技术领域中具有通常知识者而言是例行工作。
现将参照附图来说明本发明。各种结构、系统与装置示意地被描述于图式中仅为了说明之目的，以便不使熟悉本技术领域者所熟知之细节模糊了本揭示发明。不过，仍包含附图以叙述及说明本揭示发明的例示范例。应以与熟悉该相关技艺者所认定之意义来了解与解释本文中所使用之字汇与词。本文中前后一致使用的术语以及词汇并无暗示特别的定义，特别的定义亦即与熟悉该项技艺者所认定之普通惯用意义所不同的定义。如果一个术语或词汇具有特别定义，亦即不同于熟悉该领域技艺者所了解之意义，本说明书将会明白地对该术语或词汇提供直接且明确的定义。
一般而言，本揭示发明提供半导体装置与技术，该半导体装置与技术中包含敏感低k介电材料的复杂金属化系统可以接受根据无铅材料所形成的凸块结构或柱状结构，其中，可以通过提供包含经横向分离的金属缓冲区域的适当的缓冲层减少机械应力，该缓冲层于“垂直”与横向方向具有适度大的尺寸。因此，可以通过应力缓冲层所提供的大容量调和产生的机械应力，并且该机械应力亦可以实质上分布至遍及整个芯片表面。
在此方面，应该了解到无铅材料被理解为化学计量成分中不包含铅之任何材料合成物，以致于非故意被加入所考虑材料中的任何微量的铅，相对于整个材料合成物可能小于大约0.5原子百分比。举例而言，可以用锡和其它混合物(锡/银/铜混合物等)之形式提供无铅焊接材料，同时其中任何铅杂质可以小于上述指定者。同样地，若关于铅杂质之纯度可以小于上述指定者，铜材料亦可称为无铅材料。
于一些例示实施例中，可以不使用铝而提供结合接触结构的金属化系统，从而提供该金属化系统优越的电性效能同时额外地避开形成与图案化铝材料所需的资源。因此，可以达成整体制程流程的优越效率，同时亦可实现金属化系统所希望的高水平的电性效能，这是因为可以有效的降低于该敏感的金属化系统内由芯片与封装件间的交互作用所引起的机械应力。
参照图2a至2i，现在将更详尽地说明进一步的例示实施例，其中如果需要，亦可能参照图1a至1b。
图2a示意地显示半导体装置200中一部份的上视图，其中为了方便起见，例示了单一晶粒区域201或基板部分结合接触组件(例如焊料凸块组件、金属柱等等)的相对应的配置。为了方便起见，接触组件210之基本布局可以选择与习知装置100相同，如先前参照图1a至1b所说明者。此外，该装置200可包括可以金属区域形式提供多个缓冲区域265的应力缓冲层260，其中该缓冲区域的横向尺寸，亦即该表面面积，可大于接触组件210的横向尺寸。举例而言，于一些例示实施例中，缓冲区域265的表面面积可为至少接触组件210的表面面积的二倍。以此方法，任何透过该接触组件210传递的机械应力分量可有效地被该应力缓冲层260调和并且分布于遍及整个芯片或晶粒201中的大面积。举例而言，对于各接触组件210，该缓冲区域265的横向尺寸可以是规则的，同时，在其它情况中，该缓冲区域265之横向尺寸可依芯片201内的接触组件的特定位置作调整。例如，如缓冲区域265A所示，可以增加一个方向(表示为Y)的横向扩张以便覆盖该晶粒增加的表面部分。另一方面，X方向之横向扩张可以被邻接接触区域265间所希望的最小隔离距离所限制。举例而言，两个邻接接触区域(譬如该区域265，265A)间的横向偏移可选择为约5μm或更小，譬如1μm或更小，因此该缓冲区域265提供了晶粒201之表面面积非常有效率的覆盖。如稍后将被更加详尽解释者，任何隔离凹槽266可以适当的介电材料填满，例如氮化硅，聚醯亚胺等等。
图2b示意地显示装置200沿着图2a之剖线IIb之剖面图。如所例示，该装置200可包括基板，该基板亦可称为基本芯片或晶粒材料201，当需要时可以在该基板中或上方形成任何电路组件。而且，金属化系统220可以形成在该基板201上，并且可以包括多个堆栈的金属化层，例如，如前文所述提到金属化层130和140(见图1b)而参照装置100的金属化系统120所说明者。应该了解到，该金属化系统220可以具有任何适当的配置，然而其中，当根据无铅材料形成接触组件210(图2a)时，关于减少低k介电材料之量可以不需要相对应的调适。为了方便起见，仅金属化系统之最后金属化层240被显示于图2b中，该金属化层可以包括任何适当的介电材料241和包括任何合适的高导电性金属(譬如铜、银等等)并可以合并任何适当的导电阻障材料(譬如钽、氧化钽等等)所构成的金属区域242。应该了解到，该金属区域242显示于第2b图中以便表示用来连接至尚待形成的接触组件210(图2a)相对应的接触垫片。此外，能以包含材料层251A、251B的层堆栈形式设置的钝化层251可以形成在金属化层240上，并且可包括开口251C、251D以便暴露一部分之接触垫片242。可以形成介电材料251A、251B以及任何其它材料层，以便符合鉴于钝化该层240之要求。举例而言，可使用氮化硅于层251A，随后是氧化硅或氮氧化硅材料，而于其它情况可以施加不同组成之层堆栈251。
可以依据用来形成电路组件以及形成具有所希望的减少的讯号传递延迟的金属化系统220的任何适当制造技术而形成如图2b中所示之半导体装置200，亦如前面参照半导体装置100所说明者。因此，于提供最后金属层240之后，可以依据任何适当的沉积技术形成钝化层251，随后藉由微影制程形成蚀刻掩模(未图标)并且使用广为接受的蚀刻配方图案化该层251。
图2c示意地显示于更进一步制造阶段中的半导体装置200，该阶段中可以形成阻障层256于钝化层251上与开口251C、251D内。为了提供与钝化层251上仍待形成的金属所希望的粘着程度，也为了提供所希望的电性特性(例如导电率)给接触垫片242，该层256可以具有任何适当的材料组成。再者，于一些例示实施例中，该层256亦可以于仍待形成之缓冲区域265(图2a)的金属电化学沉积期间扮演电流分布层。举例而言，可以有效地使用铜，并结合其它材料，譬如铬、钽、钨等等。因为任何的这些材料典型地被使用于半导体制造期间，因此相对应的沉积工具和先驱物材料容易获得。视整体装置的需求而定，该阻障层256可以提供约50至数百纳米的厚度。
图2d示意地显示具有沉积掩模202(譬如光刻胶掩模)之装置200，该掩模可以定义缓冲区域265(图2a)的横向尺寸，其亦可以用来覆盖不希望有各自缓冲区域的任何的装置区域。举例而言，如所例示，划线区域(scribe line area)203可以排除于提供应力缓冲层之外，并且因此该区域可以被沉积掩模202所覆盖。因此，该沉积掩模202可以定义对应的开口202C、202D，该开口202C、202D对准开口251C、251D，其中，为了适当的定义图2a中之缓冲区域265的横向尺寸，因此将开口202C、202D的横向尺寸选择成明显较大于开口251C、251D者。可以根据广为接受的微影技术图案化沉积掩模202。
图2e示意地显示于沉积制程204(譬如电化学沉积制程，亦即电镀制程、无电镀制程、或他们的任何组合)期间的半导体装置200，以求沉积所希望的高导电性金属，譬如铜、银等等。如上述说明，使用亦可用于金属化系统220的金属是有利的，因为对应的沉积工具与材料资源易于取得。于一例示实施例中，可以沉积铜材料，从而形成具有所希望的横向尺寸的缓冲区域265，如可以通过沉积掩模202所定义者。再者，金属材料和缓冲区域265的厚度可以是“厚的”，亦即，厚度可以是约3μm和更大。举例而言，于例示实施例中，厚度265T可以选择成在3至10μm的范围。因此，通过于最后金属化层240上方提供增加的厚度，鉴于可能由芯片与仍待连接至的封装件基板间的交互作用所引出的任何机械应力，可以给予金属化系统220优越的机械稳定性。再者，由缓冲区域265所提供的适度大的金属量亦可以提供优越的散热能力，该散热能力可以贡献较不显著的热引发的机械应力。再者，可达成增强的掩模效应，例如，鉴于高能粒子，譬如宇宙射线、微波幅射等等。可以根据任何适当的制程配方实施沉积制程204，如此亦可以应用于形成金属化系统220之金属化层的期间。
图2f示意地显示于移除沉积掩模202(图2d)并且也移除导电阻障层256的暴露部分的制程顺序205过程中的半导体装置200。因此，隔离凹槽266可确实地形成于缓冲区域265间，其中宽度266W可因此定义邻接区域265间的横向偏移。举例而言，宽度266W可选择为约5μm和更小的范围，譬如1μm或更小，从而通过缓冲区域265提供金属化系统220高度的覆盖范围。可以依据任何适当的制程技术来实施该制程顺序205，例如通过根据电浆辅助蚀刻制程、湿式化学蚀刻制程移除光刻胶材料，随后移除层256的暴露部份，除去层256的暴露部份可以依照层256之组成，根据溅镀蚀刻技术、湿式化学蚀刻制程等等来完成。应该了解到，由于适度大的厚度和其横向扩张，区域265的某种程度的材料腐蚀可能不要紧。
图2g示意地显示具有介电层257形成于缓冲区域265上以及隔离凹槽266内的半导体装置200，从而提供该区域265的材料可靠的限制，并且亦提供个别缓冲区域265可靠的电性绝缘。举例而言，可以使用任何适当的介电材料，譬如氮化硅，该介电材料可以根据广为接受的沉积技术(譬如电浆促进化学气相沉积(CVD))等等沉积。
图2h示意地显示于更进一步制造阶段的半导体装置200，于该制造阶段中，另外的介电材料，譬如聚醯亚胺252，可形成于介电材料257上方与隔离凹槽266内。因此，该缓冲区域265结合隔离凹槽266内所提供的介电材料可以形成提供所希望的机械特性的应力缓冲层260。再者，依据于图2a内所示的整体布局，可以形成具有适当横向尺寸的开口250A以便对准于接触垫片242，如可能用于形成凸块结构、金属柱等等所需者。可以根据任何广为接受的制程技术提供该材料252，并可以依据如可以典型用于习知制程技术的制程参数通过微影而完成该材料252之图案化。之后，可用该材料252作为蚀刻掩模以暴露缓冲区域265于开口250A内之一部分。为了此目的，可以应用任何合适的电浆辅助蚀刻配方、湿式化学蚀刻配方等等。
图2i示意地显示于更进一步制造阶段的半导体装置200，该制造阶段可以于开口250A内形成接触组件210，例如以基于无铅焊接材料的焊接凸块形式形成，如前面所说明者。当直接接触被视为不适当时，如果需要，额外的阻障材料211可以设置于接触组件210与缓冲区域265之间。于此情况，可以应用如习知策略的相似制程策略，通过提供材料211，形成沉积掩模，沉积接触组件210的材料，移除该沉积掩模并图案化该材料211。于其它例示实施例中，如以虚线表示之组件210A，可以设置譬如铜柱的金属柱，该金属柱可以通过使用适当的沉积掩模，如果需要的话，可能结合铜基之晶种层而直接形成于区域265上。因此，可以应用多个广为接受的制程技术设置该接触组件210、210A。再者，封装件基板270可设有接触垫片271的适当布局，该接触垫片271可以根据广为接受的接合技术与组件210、210A接触。应该了解到该接触垫片271可以具有任何适当的配置，例如，可以提供焊接材料、铜材料等等，以便与接触组件210形成介金属的连接。
结果，本揭示发明提供半导体装置和制程技术，该装置和技术可以根据无铅材料提供通过设置应力缓冲层而具有优越应力分布特性的接触结构，该应力缓冲层包含多个增加横向尺寸并具有约3至10μm厚度范围的缓冲区域。因此，于连接半导体芯片至封装件基板期间与之后复于合半导体装置运作期间所引发的机械应力可以有效地分布至遍及大的表面面积。因此，可以避免如于习知策略中典型要求之明显的修正，例如而减少敏感的低k材料的量，从而提供金属化系统优越的效能。再者，通过缓冲区域显著地覆盖金属化系统可以提供优越的热以及屏蔽特性，该特性可以允许有效地使用于关键的环境。
以上所揭示之特定实施例仅做例示用，因为对于熟悉该技术领域者而言，藉由此处教示的帮助而能以不同但等效的方式修改以及实施本发明是显而易见的。例如，以上所提出的制程步骤可以不同顺序执行。再者，在此所示的架构或设计细节并非意欲限制，除了以下附加之权利要求所叙述者外。因此，很明显的是，可在本发明之精神和范畴内改辨或修改以上所揭示之特定实施例及所思及之所有此等变化。由此，本发明所要求保护者如附加之权利要求所提出者。

Claims (14)

1.一种半导体装置，包括：
形成在基板(201)上方的金属化系统(220)，该金属化系统包括多个金属化层，至少一些该金属化层包括低k介电材料；
形成在该金属化系统的最后金属化层上的应力缓冲层(260)，该应力缓冲层包括含铜缓冲区域(265)，该含铜缓冲区域导电地耦接至设置于该金属化系统的该最后金属化层的含铜接触垫片(242)；
形成于该含铜缓冲区域(265)的一部分上的无铅接触组件(210)；以及
透过该无铅接触组件(210)连接至该金属化系统之封装件基板(270)。
2.如权利要求1所述的半导体装置，其中，该含铜缓冲区域(265)的厚度约3μm或更多。
3.如权利要求1所述的半导体装置，其中，该无铅接触组件(210)包括无铅焊接材料。
4.如权利要求1所述的半导体装置，其中，该无铅接触组件包括从该缓冲区域(265)延伸的铜柱。
5.如权利要求1所述的半导体装置，其中，该应力缓冲层(260)形成在钝化层(251)上方，该钝化层形成在该最后金属层上方并且暴露该接触垫片(242)。
6.如权利要求5所述的半导体装置，进一步包括形成于该缓冲区域(265)与该钝化层(251)之间的导电阻障层(256)。
7.如权利要求1所述的半导体装置，其中，该应力缓冲层(260)包括多个缓冲区域(265)，并且其中相邻的缓冲区域之间的横向偏移为约5μm或更少。
8.如权利要求1所述的半导体装置，其中，该横向偏移为约1μm或更少。
9.如权利要求1所述的半导体装置，其中，该缓冲区域(265)的横向尺寸为该接触垫片(242)的横向尺寸的至少二倍。
10.如权利要求1所述的半导体装置，其中，该应力缓冲层(260)进一步包括于侧面包围该缓冲区域(265)的介电材料，其中该介电材料包括氮化硅。
11.一种方法，包括：
于形成在半导体装置的金属化系统上方的钝化层(251)中形成第一开口(251D)，该金属化系统包括具有接触垫片(242)的最后金属化层，该接触垫片对准于该第一开口；
于该钝化层(251)上方形成沉积掩模，该沉积掩模包括对准于该第一开口的第二开口；
于该第一与第二开口中形成含铜材料；
移除该沉积掩模；以及
于该含铜材料的一部份上形成接触组件(210)。
12.如权利要求11所述的方法，进一步包括在形成该沉积掩模之前先于该钝化层(251)上方形成导电阻障材料(256)。
13.如权利要求11所述的方法，其中，该第二开口在横向方向的横向扩张为该第一开口在该横向方向的横向扩张的至少二倍。
14.如权利要求11所述的方法，其中，于该含铜材料的一部份上形成接触组件包括形成与该含铜材料侧面邻接并且位于该含铜材料上方的介电材料，于该介电材料中形成第三开口，并且根据该第三开口形成该接触组件。
CN2010800386505A 2009-07-31 2010-07-29 包含形成于低k金属化系统上的应力缓冲材料的半导体装置 Pending CN102576699A (zh)

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