CN112563251A - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
CN112563251A
CN112563251A CN202010999296.8A CN202010999296A CN112563251A CN 112563251 A CN112563251 A CN 112563251A CN 202010999296 A CN202010999296 A CN 202010999296A CN 112563251 A CN112563251 A CN 112563251A
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CN
China
Prior art keywords
semiconductor die
layer
bonding
passivation layer
pattern
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Pending
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CN202010999296.8A
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English (en)
Inventor
郭胜安
杨庆荣
陈宪伟
陈洁
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112563251A publication Critical patent/CN112563251A/zh
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Abstract

提供一种包含第一半导体管芯、第二半导体管芯、钝化层、抗电弧图案以及导电端子的半导体结构。第二半导体管芯堆叠于第一半导体管芯上方。钝化层覆盖第二半导体管芯且包含用于显露第二半导体管芯的衬垫的第一开口。抗电弧图案安置于钝化层上方。导电端子安置于第二半导体管芯的衬垫上方且电连接到第二半导体管芯的衬垫。

Description

半导体结构
技术领域
本发明的实施例是有关于一种半导体结构。
背景技术
半导体行业已经由于多种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历快速增长。主要来说，集成密度的改进是基于最小特征大小的连续减小，这允许将更多组件集成到给定区域中。随着近来对小型化、更高速度和更大带宽以及更低功耗和时延的需求的增长，对半导体管芯的更小和更有创造性的封装技术的需求也在增长。目前，集成电路上系统(System-on-Integrated-Circuit；SoIC)组件因其多功能和紧密性而变得越来越受欢迎。然而，存在与SoIC组件的封装工艺相关的挑战。
发明内容
本发明实施例提供一种半导体结构，包括第一半导体管芯、第二半导体管芯、钝化层、抗电弧图案以及导电端子。第二半导体管芯堆叠于第一半导体管芯上方。钝化层覆盖第二半导体管芯，且包括用于显露第二半导体管芯的衬垫的第一开口。抗电弧图案安置于钝化层上方。导电端子安置于第二半导体管芯的衬垫上方，且电连接到第二半导体管芯的衬垫。
本发明实施例提供一种半导体结构，包括第一半导体管芯、第二半导体管芯、绝缘密封体、钝化层、导电端子以及电荷扩散图案。第一半导体管芯包括第一半导体衬底、第一半导体衬底上方的第一内连线结构以及第一内连线结构上方的第一接合结构。第二半导体管芯堆叠于第一半导体管芯上方。第二半导体管芯包括第二半导体衬底、第二内连线结构以及第二接合结构。第二内连线结构和第二接合结构安置于第二半导体衬底的相对表面上，且第二半导体管芯通过第一接合结构和第二接合结构来电连接第一半导体管芯。绝缘密封体横向地密封第一半导体管芯和第二半导体管芯。钝化层安置于第二半导体管芯的第二内连线结构和绝缘密封体上方，且钝化层包括用于显露第二半导体管芯的衬垫的第一开口。导电端子安置于第二半导体管芯的衬垫上方且电连接到第二半导体管芯的衬垫。电荷扩散图案安置于导电端子与钝化层之间。
本发明实施例提供一种半导体结构的制造方法，包括以下步骤。将上部层半导体管芯接合到底部层半导体管芯，其中上部层半导体管芯包括衬垫。在上部层半导体管芯的顶部表面上方形成钝化层。在钝化层上方形成抗电弧图案，其中钝化层包括用于显露上部层半导体管芯的衬垫的开口。以及，在上部层半导体管芯上方形成导电端子，其中导电端子电连接到上部层半导体管芯的衬垫。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本公开的各方面。应注意，根据业界中的标准惯例，各种特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1到图11是示意性地示出根据本公开的一些实施例的用于制造SoIC组件的工艺流程的横截面图；
图12到图14是示意性地示出根据本公开的一些实施例的用于制造SoIC组件的另一工艺流程的横截面图；
图15到图19是示意性地示出根据本公开的其它实施例的用于制造SoIC组件的又另一工艺流程的横截面图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本公开。当然，这些组件和布置只是实例且并不意欲是限制性的。举例来说，在以下描述中，第一特征在第二特征上方或上的形成可包含第一特征和第二特征直接接触地形成的实施例，且还可包含额外特征可在第一特征与第二特征之间形成使得第一特征和第二特征可不直接接触的实施例。另外，本公开可在各种实例中重复参考标号和/或字母。这种重复是出于简化和清楚的目的且本身并不规定所论述的各种实施例和/或配置之间的关系。
另外，为易于描述，本文中可使用如“在…下方”、“在…之下”、“下部”、“在…之上”、“上部”以及类似术语的空间相对术语，以描述如图中所示出的一个元件或特征相对于另一(一些)元件或特征的关系。除图中所描绘的定向以外，空间相对术语意欲涵盖器件在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词可同样相应地进行解释。
还可包含其它特征和工艺。举例来说，可包含测试结构以辅助校验测试3D 封装或3DIC器件。测试结构可包含例如形成于重布线层中或衬底上的测试衬垫，所述衬底允许对3D封装或3DIC的测试、对探针和/或探针卡的使用以及类似操作。可对中间结构以及最终结构执行校验测试。此外，本文中所公开的结构和方法可与并有已知良好管芯的中间验证的测试方法结合使用以增大良率且降低成本。
图1到图11是示意性地示出根据本公开的一些实施例的用于制造SoIC组件的工艺流程的横截面图。
参考图1，提供包含形成于其顶部表面上的接合层B1的第一载体C1。第一载体C1可以是半导体晶圆(semiconductor wafer)，且接合层B1可以是准备用于融合接合的接合层。在一些实施例中，接合层B1是形成于第一载体C1的顶部表面上方的沉积层。在一些替代实施例中，接合层B1是用于融合接合的第一载体C1的一部分。举例来说，第一载体C1的材料包含硅或其它合适的半导体材料，且接合层B1的材料包含硅(Si)、二氧化硅(SiO2)或其它合适的接合材料。
提供一或多个半导体管芯100(例如，逻辑管芯)且将其放置在接合层B1 的顶部表面上。在图1中，示出仅一个半导体管芯100，然而，半导体管芯100 的数目不受限制。半导体管芯100可包含有源表面(即前表面)和与有源表面相对的背表面。半导体管芯100放置在接合层B1的顶部表面上使得半导体管芯100的有源表面面向由第一载体C1承载的接合层B1。半导体管芯100可包含形成于其有源表面上的接合层B2。在半导体管芯100放置在接合层B1的顶部表面上之后，接合层B2与接合层B1接触。在其中拾取多个半导体管芯且将其放置在接合层B1上的实施例中，半导体管芯可以并排方式放置到接合层B1 上使得半导体管芯以阵列布置且彼此间隔开。在一些实施例中，接合层B2的材料包含硅(Si)、二氧化硅(SiO2)或其它合适的接合材料。
半导体管芯100可包含具有形成于其中的半导体器件的半导体衬底102、安置于半导体衬底102上且电连接到形成于半导体衬底102中的半导体器件的内连线结构104以及覆盖内连线结构104的介电层106。半导体管芯100的介电层106由接合层B2覆盖。半导体管芯100可更包含形成于半导体衬底102 中且电连接到内连线结构104的内连线布线的半导体穿孔(through semiconductor via；TSV)103。如图1中所示出，TSV 103嵌入于半导体衬底102和内连线结构104中，且TSV 103不从半导体衬底102的背表面显露。
在拾取半导体管芯100且将其放置在接合层B1上之后，芯片到晶圆融合接合工艺可执行以使得融合接合界面形成于接合层B1与接合层B2之间。举例来说，在约100摄氏度到约290摄氏度的范围内的温度下执行用于接合接合层 B1和接合层B2的融合接合工艺。接合层B1可直接接合到接合层B2。换句话说，在接合层B1与接合层B2之间形成的中间层不存在。上文所提及的形成于接合层B1与接合层B2之间的融合接合界面可以是Si-Si融合接合界面、Si-SiO2融合接合界面、SiO2-SiO2融合接合界面或其它合适的融合接合界面。
参考图1和图2，在半导体管芯100通过接合层B1和接合层B2接合到第一载体C1之后，形成绝缘材料以覆盖接合层B1、接合层B2以及半导体管芯 100。在一些实施例中，绝缘材料由包覆模制工艺或膜沉积工艺形成以使得接合层B1的顶部表面的一部分、接合层B2的侧表面以及半导体管芯100的背表面和侧表面由绝缘材料密封。在执行包覆模制工艺或膜沉积工艺之后，可执行研磨工艺以减小绝缘材料的厚度和半导体管芯100的厚度，使得具有减小厚度的半导体管芯100'和第一绝缘密封体110形成于接合层B1上方。在一些实施例中，用于减小绝缘材料的厚度和半导体管芯100的厚度的研磨工艺包含机械研磨工艺、化学机械抛光(chemical mechanical polishing；CMP)工艺或其组合。
如图2中所示出，在一些实施例中，半导体管芯100'的厚度等于第一绝缘密封体110的厚度，且半导体管芯100'和接合层B2由第一绝缘密封体110横向地密封。换句话说，第一绝缘密封体110仅与半导体管芯100'和接合层B2的侧表面接触，且半导体衬底102'的背表面从第一绝缘密封体110可接近地显露。在一些替代实施例中，图2中未示出，半导体管芯的厚度由于研磨工艺的抛光选择性而略微小于或大于第一绝缘密封体的厚度。换句话说，第一绝缘密封体的顶部表面可略微高于或略微低于半导体管芯的背表面。
参考图3，接合结构120形成于半导体管芯100'的背表面和第一绝缘密封体110的显露表面上方。换句话说，接合结构120可完全覆盖半导体衬底102' 的背表面和第一绝缘密封体110的显露表面。接合结构120可包含介电层120a 和各自穿透介电层120a的导体120b。介电层120a的材料可以是氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氮氧化硅(SiOxNy，其中x>0且y>0) 或其它合适的介电材料，且导体120b可以是导通孔(例如，铜通孔)、导电衬垫(例如，铜衬垫)或其组合。
参考图4，提供一或多个半导体管芯200(例如，存储器管芯、逻辑管芯或其它合适的管芯)，且将其放置在接合结构120的一部分上。在图4中，示出仅一个半导体管芯200，然而，半导体管芯200的数目不受限制。在一些实施例中，半导体管芯200放置在接合结构120上且堆叠在半导体管芯100'之上。半导体管芯200可包含半导体衬底202、安置于半导体衬底202上的内连线结构 204以及安置于内连线结构204上且电连接到内连线结构204的接合结构220。半导体管芯200的接合结构220与接合结构120的一部分接触。接合结构220 可包含介电层220a和各自穿透介电层220a的导体220b。介电层220a的材料可以是氧化硅(SiOx，其中x>0)、氮化硅(SiNx，其中x>0)、氮氧化硅(SiOxNy，其中x>0且y>0)或其它合适的介电材料，且导体220b可以是导通孔(例如，铜通孔)、导电衬垫(例如，铜衬垫)或其组合。
接合结构220的导体220b与接合结构120的导体120b对准，且半导体管芯200与半导体管芯100'之间的亚微米对准精确度可实现。在接合结构220与接合结构120精确地对准后，执行芯片到晶圆混合接合(chip-to-wafer hybrid bonding)以使得半导体管芯200的接合结构220混合接合到接合结构120。换句话说，半导体管芯200和半导体管芯100'可通过面对背(face-to-back)混合接合工艺来接合。
在一些实施例中，为有助于接合结构120与接合结构220之间的芯片到晶圆混合接合，执行用于接合结构120和接合结构220的接合表面的表面制备。举例来说，表面制备可包含表面清洁和活化。可在接合结构120和接合结构220 的接合表面上执行表面清洁以去除导体120b、介电层120a、导体220b以及介电层220a的接合表面上的颗粒。举例来说，通过湿式清洁来清洁接合结构120 和接合结构220的接合表面。不仅可去除颗粒，且还可去除形成于导体120b 和导体220b的接合表面上的自然氧化物。可通过在湿式清洁中使用的化学品来去除形成于导体120b和导体220b的接合表面上的自然氧化物。
在清洁接合结构120和接合结构220的接合表面之后，可执行介电层120a 和介电层220a的顶部表面的活化以用于产生高接合强度。在一些实施例中，执行等离子活化(plasma activation)以处理且活化介电层120a和介电层220a的接合表面。当介电层120a的活化接合表面与介电层220a的活化接合表面接触时，介电层120a和介电层220a是预接合的。通过介电层120a和介电层220a 的预接合来预接合接合结构220和接合结构120。在介电层120a和介电层220a 的预接合之后，导体120b与导体220b接触。
在介电层120a与介电层220a的预接合之后，执行半导体管芯200与接合结构120的混合接合。半导体管芯200与接合结构120的混合接合可包含用于介电接合的处理和用于导体接合的热退火。执行用于介电接合的处理以加强介电层120a与介电层220a之间的接合。举例来说，可在约100摄氏度到约150 摄氏度的范围内的温度下执行用于介电接合的处理。在执行用于介电接合的处理之后，执行用于导体接合的热退火以有助于导体120b与导体220b之间的接合。举例来说，可在约300摄氏度到约400摄氏度的范围内的温度下执行用于导体接合的热退火。用于导体接合的热退火的处理温度高于用于介电接合的处理的温度。由于在相对较高温度下执行用于导体接合的热退火，金属扩散和晶粒生长可发生于导体120b与导体220b之间的接合界面处。在执行用于导体接合的热退火之后，介电层120a接合到介电层220a，且导体120b接合到导体220b。导体120b与导体220b之间的导体接合可以是通孔到通孔(via-to-via)接合、衬垫到衬垫(pad-to-pad)接合或通孔到衬垫(via-to-pad)接合。
参考图4和图5，在半导体管芯200通过接合结构120和接合结构220接合到半导体管芯100'之后，形成绝缘材料以覆盖接合结构120、接合结构220 以及半导体管芯200。在一些实施例中，绝缘材料由包覆模制工艺或膜沉积工艺形成以使得接合结构120的顶部表面的一部分、接合结构220的侧表面以及半导体管芯200的背表面和侧表面由绝缘材料密封。在执行包覆模制工艺或膜沉积工艺之后，可执行研磨工艺以减小绝缘材料的厚度和半导体管芯200的厚度，使得具有减小厚度的半导体管芯200'和第二绝缘密封体210形成于接合结构120上方。在执行研磨工艺之后，具有减小厚度的半导体衬底202'从第二绝缘密封体210可接近地显露。在一些实施例中，用于减小绝缘材料的厚度和半导体管芯200的厚度的研磨工艺包含机械研磨工艺、化学机械抛光(chemical mechanical polishing；CMP)工艺或其组合。
如图5中所示出，在一些实施例中，半导体管芯200'的厚度等于第二绝缘密封体210的厚度，且半导体管芯200'和接合结构220由第二绝缘密封体210 横向地密封。换句话说，第二绝缘密封体210仅与半导体管芯200'和接合结构 220的侧表面接触，且半导体管芯200'的背表面从第二绝缘密封体210可接近地显露。在一些替代实施例中，图5中未示出，半导体管芯的厚度由于研磨工艺的抛光选择性而略微小于或大于第二绝缘密封体的厚度。换句话说，第二绝缘密封体的顶部表面可略微高于或略微低于半导体管芯的背表面。此外，第一绝缘密封体110通过接合结构120与第二绝缘密封体210间隔开。
形成接合层B3以覆盖半导体衬底202'的背表面和第二绝缘密封体210的显露表面。接合层B3可以是制备用于融合接合的接合层。在一些实施例中，接合层B3是形成于半导体衬底202'的背表面和第二绝缘密封体210的显露表面上方的沉积层。举例来说，接合层B3的材料包含硅(Si)、二氧化硅(SiO2)或其它合适的接合材料。
参考图6，提供包含形成于其顶部表面上的接合层B4的第二载体C2。第二载体C2可以是半导体晶圆，且接合层B4可以是制备用于融合接合的接合层。在一些实施例中，接合层B4是形成于第二载体C2的顶部表面上方的沉积层。在一些替代实施例中，接合层B4是用于融合接合的第二载体C2的一部分。举例来说，第二载体C2的材料包含硅或其它合适的半导体材料，且接合层B4的材料包含硅(Si)、二氧化硅(SiO2)或其它合适的接合材料。
将形成于第一载体C1上的所得结构颠倒翻转且转移接合到由第二载体C2 承载的接合层B4以使得接合层B3与接合层B4接触且接合到接合层B4。在一些实施例中，执行晶圆到晶圆融合接合工艺以使得融合接合界面形成于接合层 B3与接合层B4之间。举例来说，在约100摄氏度到约290摄氏度的范围内的温度下执行用于接合接合层B3和接合层B4的融合接合工艺。接合层B3可直接接合到接合层B4。换句话说，在接合层B3与接合层B4之间形成的中间层不存在。此外，形成于接合层B3与接合层B4之间的融合接合界面可以是Si-Si 融合接合界面、Si-SiO2融合接合界面、SiO2-SiO2融合接合界面或其它合适的融合接合界面。
参考图6和图7，在接合接合层B3与接合层B4之后，可执行剥离工艺以使得从接合层B2和第一绝缘密封体110剥离接合层B1。剥离工艺可以是激光剥离工艺或其它合适的剥离工艺。在去除接合层B1和第一载体C1之后，可执行研磨工艺以使得去除接合层B2从而暴露介电层106的表面。在去除接合层 B2期间，第一绝缘密封体110可变薄。另外，在去除接合层B2之后，第一绝缘密封体110和介电层106可进一步变薄。在一些实施例中，去除接合层B2以及薄化第一绝缘密封体110和介电层106可由相同研磨工艺(例如，CMP工艺)执行。如图7中所示出，在执行研磨工艺之后，半导体管芯100'显露，但半导体管芯100'的衬垫P(例如，铜衬垫)不显露且由介电层106覆盖。
参考图8，形成钝化层230以覆盖第一绝缘密封体110和半导体管芯100' 的介电层106。可通过化学气相沉积(chemical vapor deposition；CVD)或其它合适的沉积来形成钝化层230。在一些实施例中，钝化层230包含氧化硅层、氮化硅层、氮氧化硅层或其它合适的介电层。抗电弧材料层或电荷扩散图案240 形成于钝化层230上。可通过溅镀、化学气相沉积(CVD)或其它合适的沉积来形成抗电弧材料层240。在一些实施例中，抗电弧材料层240包含导电层，如溅镀钛(Ti)层、溅镀Ti-Cu合金层、溅镀钽(Ta)层或其它合适的金属材料。抗电弧材料层240的厚度可在约10埃到约1000埃的范围内。可修改抗电弧材料层240的厚度。
参考图8和图9，执行介电层106、钝化层230以及抗电弧材料层240的图案化工艺以使得形成图案化介电层106'、图案化钝化层230'以及抗电弧图案240'。多个第一开口OP1形成于图案化介电层106'、图案化钝化层230'以及抗电弧图案240'中以使得半导体管芯100'的衬垫P(例如，铜衬垫)的顶部表面由第一开口OP1部分地暴露。在一些实施例中，执行光刻工艺以在抗电弧材料层240 上形成图案化光刻胶层PR1，且执行刻蚀工艺(例如干式刻蚀工艺)以去除介电层106、钝化层230以及抗电弧材料层240的不由图案化光刻胶层PR1覆盖的部分直到部分地暴露半导体管芯100'的衬垫P(例如，铜衬垫)的顶部表面为止。
在其中第一开口OP1由干式刻蚀工艺(例如，等离子干式刻蚀工艺)形成的实施例中，由于围绕第一开口OP1发生的电荷累积通过抗电弧材料层240或抗电弧图案240'而最小化，因此可改进半导体管芯100'的衬垫P(例如，铜衬垫)的电弧损害问题。在一些实施例中，抗电弧图案240'包含导电图案，如溅镀钛(Ti)图案、溅镀Ti-Cu合金图案、溅镀钽(Ta)图案或其它合适的金属图案。抗电弧材料层图案240'的厚度可在约10埃到约1000埃的范围内。可修改抗电弧图案240'的厚度以最小化电荷累积且提供恰当抗电弧功能。
参考图9和图10，在形成第一开口OP1之后，从抗电弧图案240'去除图案化光刻胶层PR1。在去除图案化光刻胶层PR1之后，形成包含第二开口OP2的后钝化层250以覆盖图案化介电层106'、图案化钝化层230'以及抗电弧图案240'。后钝化层250可延伸到第一开口OP1(图9中所示出)中，且半导体管芯100' 的衬垫P的部分由在后钝化层250中所限定的第二开口OP2显露。可执行镀覆工艺以使得多个导电端子260形成于半导体管芯100'的衬垫P的显露部分上。如图10中所示出，导电端子260可落在半导体管芯100'的衬垫P上，填充在后钝化层250中所限定的第二开口OP2，且从后钝化层250的顶部表面突出。此外，导电端子260可通过后钝化层250与抗电弧图案240'间隔开。抗电弧图案 240'可与导电端子260电绝缘。举例来说，抗电弧图案240'是电浮动的。在一些实施例中，如图10中所示出，没有晶种层形成于导电端子260与后钝化层 250之间。
参考图10和图11，在形成导电端子260之后，执行剥离工艺以使得获得从载体C2剥离的SoIC。在其中使用多个半导体管芯100'和多个半导体管芯200' 的一些其它实施例中，进一步执行单体化工艺以使得获得多个单体化SoIC。
如图11中所说明，SoIC可包含半导体管芯(即第一半导体管芯或底部层半导体管芯)200'、半导体管芯(即第二半导体管芯或顶部层半导体管芯)100'、钝化层230'、抗电弧图案240'、后钝化层250以及导电端子260。半导体管芯 100'堆叠在半导体管芯200'上方。半导体管芯100'可通过面对背混合接合工艺来接合到半导体管芯200'。半导体管芯100'可通过接合结构120和接合结构220 接合到半导体管芯200'，且半导体管芯100'通过接合结构120和接合结构220 电连接半导体管芯200'。钝化层230'覆盖半导体管芯100'且包含用于显露半导体管芯100'的衬垫P(例如，铜衬垫)的第一开口OP1。抗电弧图案240'安置于钝化层230'上方，且抗电弧图案240'分散于钝化层230'的第一开口OP1外部。举例来说，抗电弧图案240'安置于钝化层230'的顶部表面上。换句话说，抗电弧图案240'可安置于后钝化层250与钝化层230'之间。后钝化层250可覆盖钝化层230'和抗电弧图案240'。后钝化层250可延伸到第一开口OP1中且包含用于显露半导体管芯100'的衬垫P的部分的第二开口OP2。举例来说，后钝化层 250可沿第一开口OP1的侧壁延伸。导电端子260安置于半导体管芯100'的衬垫P上方且电连接到半导体管芯100'的衬垫P。此外，导电端子260可通过后钝化层250与抗电弧图案240'的侧壁间隔开。
图12到图14是示意性地示出根据本公开的一些实施例的用于制造SoIC组件的另一工艺流程的横截面图。
参考图9和图12，在执行图9中所示出的工艺之后，例如，通过剥除工艺来去除图案化光刻胶层PR1(图9中所示出)。举例来说，通过溅镀保形地形成晶种层270以覆盖抗电弧图案240'和半导体管芯100'的衬垫P。溅镀的晶种层 270不仅覆盖抗电弧图案240'的顶部表面，且还沿图案化介电层106'、图案化钝化层230'以及抗电弧图案240'的侧表面延伸且覆盖所述侧表面。在一些实施例中，晶种层270包含溅镀Ti/Cu晶种层。在形成晶种层270之后，图案化光刻胶层PR2形成于晶种层270上，且图案化光刻胶层PR2包含用于暴露晶种层 270的部分的多个开口。可执行镀覆工艺以在图案化光刻胶层PR2中所限定的开口中形成导电柱280。
参考图12和图13，例如，通过剥除工艺从晶种层270去除图案化光刻胶层PR2。在去除图案化光刻胶层PR2之后，暴露不由传导柱280覆盖的晶种层 270的部分。执行图案化工艺以去除晶种层270和定位于晶种层270下的抗电弧图案240'的暴露部分直到显露图案化钝化层230'为止。在执行上文所提及的图案化工艺之后，可执行回焊工艺以重塑传导柱280，使得抗电弧图案240a和导电凸块280a形成于半导体管芯100'上方，其中导电端子260a中的每一个包含晶种图案270a和晶种图案270a上的导电凸块280a，晶种图案270a覆盖抗电弧图案240'且延伸到第一开口OP1中，且导电凸块280a通过晶种图案270a与抗电弧图案240'间隔开。导电端子260a可电连接到抗电弧图案240a且直接覆盖抗电弧图案240a。在一些实施例中，抗电弧图案240a安置于钝化层230'的顶部表面上且分散于钝化层230'的第一开口OP1外部。此外，抗电弧图案240a 的顶部表面可完全由导电端子260a的晶种图案270a覆盖。
参考图13和图14，在形成导电端子260a之后，执行剥离工艺以使得获得从载体C2剥离的SoIC。在其中使用多个半导体管芯100'和多个半导体管芯200' 的一些其它实施例中，进一步执行单体化工艺以使得可获得多个单体化SoIC。
如图11和图14中所示出，除形成于半导体管芯100'上的导电端子260a的配置以外，图14中所示出的SoIC与图11中所示出的类似。
图15到图19是示意性地示出根据本公开的其它实施例的用于制造SoIC组件的又另一工艺流程的横截面图。
参考图8和图15，在执行图8中所示出的工艺之后，执行介电层106、钝化层230以及抗电弧材料层240的图案化工艺以使得形成图案化介电层106'、图案化钝化层230'以及抗电弧图案240'。多个第一开口OP1形成于图案化介电层106'、图案化钝化层230'以及抗电弧图案240'中以使得通过第一开口OP1部分地暴露半导体管芯100'的衬垫P1(例如，铜衬垫)的顶部表面，且不暴露半导体管芯100'的衬垫P2。半导体管芯100'的衬垫P2由图案化介电层106'、图案化钝化层230'以及抗电弧图案240'覆盖。在一些实施例中，如图15中所示出，执行光刻工艺以在抗电弧材料层240上形成图案化光刻胶层PR3，且执行刻蚀工艺(例如干式刻蚀工艺)以去除介电层106、钝化层230以及抗电弧材料层 240的不由图案化光刻胶层PR3覆盖的部分直到部分地暴露半导体管芯100'的衬垫P1(例如，铜衬垫)的顶部表面为止。衬垫P1的数目和衬垫P2的数目在本申请中不受限制。
在其中第一开口OP1由干式刻蚀工艺(例如，等离子干式刻蚀工艺)形成的实施例中，由于围绕第一开口OP1发生的电荷累积通过抗电弧材料层240或抗电弧图案240'而最小化，因此可改进半导体管芯100'的衬垫P1(例如，铜衬垫)的电弧损害问题。
参考图15和图16，在形成第一开口OP1之后，例如，通过剥除工艺从抗电弧图案240'去除图案化光刻胶层PR3。在去除图案化光刻胶层PR3之后，形成包含第二开口OP2的后钝化层250以覆盖图案化介电层106'、图案化钝化层 230'以及抗电弧图案240'。第一开口OP1比第二开口OP2更宽。后钝化层250 可延伸到第一开口OP1中，且半导体管芯100'的衬垫P1的部分由在后钝化层 250中所限定的第二开口OP2显露。可执行镀覆工艺以使得多个导电端子260 形成于半导体管芯100'的衬垫P1的显露部分上。如图16中所示出，导电端子260可落在半导体管芯100'的衬垫P1上，填充在后钝化层250中所限定的第二开口OP2，且从后钝化层250的顶部表面突出。此外，导电端子260可通过后钝化层250与抗电弧图案240'间隔开。在一些实施例中，如图16中所示出，没有晶种层形成于导电端子260与后钝化层250之间。
参考图17，将后钝化层250和抗电弧图案240'图案化以形成用于暴露图案化钝化层230'的一部分的第三开口OP3。第三开口OP3定位于半导体管芯100' 的衬垫P2上方。此外，第三开口OP3可比第一开口OP1和第二开口OP2更宽。
参考图17和图18，一或多个第四开口OP4形成于图案化介电层106'和图案化钝化层230'中。执行后接刻蚀工艺(例如干式刻蚀工艺)的光刻工艺以去除图案化介电层106'和图案化钝化层230'的部分直到半导体管芯100'的衬垫P2 的顶部表面由第四开口OP4部分地暴露为止。第四开口OP4的数目和衬垫P2 的数目在本申请中不受限制。在其中第四开口OP4由干式刻蚀工艺(例如，等离子干式刻蚀工艺)形成的实施例中，由于围绕第四开口OP4发生的电荷累积通过抗电弧图案240'或抗电弧图案240b而最小化，因此可改进半导体管芯100' 的衬垫P2的电弧损害问题。
形成电连接到半导体管芯100'的衬垫P2的导电端子260a以填充第四开口 OP4。在一些实施例中，导电端子260a各自包含晶种图案270a和覆盖晶种图案270a的导电凸块280a。如图18中所示出，导电端子260a的高度可大体上等于导电端子260的高度，且导电端子260a的横向尺寸(例如，最大宽度)可大于导电端子260的横向尺寸(例如，最大宽度)。图18中所示出的导电端子260a 的制造工艺与图12和图13中所示出的那些制造工艺类似。由此省略关于导电端子260a的制造工艺的详细描述。
如图18中所示出，在形成导电端子260a之后，抗电弧图案240'可包含第一部分240a和第二部分240b，抗电弧图案240'的第一部分240a定位于图案化钝化层230'与导电端子260a之间，且抗电弧图案240'的第二部分240b定位于图案化钝化层230'与后钝化层250之间。抗电弧图案240'的第一部分240a与抗电弧图案240'的第二部分240b间隔开。此外，抗电弧图案240'的第一部分240a 分散于第三开口OP3中。
参考图18和图19，在形成导电端子260a之后，执行剥离工艺以使得获得从载体C2剥离的SoIC。在其中使用多个半导体管芯100'和多个半导体管芯200' 的一些其它实施例中，进一步执行单体化工艺以使得获得多个单体化SoIC。
如图11和图19中所示出，除了图19中所示出的SoIC包含导电端子260 和导电端子260a两者之外，图19中所示出的SoIC与图11中所示出的类似。
在上文所描述的实施例中，抗电弧图案可最小化半导体管芯的衬垫的电弧损害问题。因此，制造良率可增大。
根据本公开的一些实施例，提供一种半导体结构包含第一半导体管芯、第二半导体管芯、钝化层、抗电弧图案以及导电端子。第二半导体管芯堆叠于第一半导体管芯上方。钝化层覆盖第二半导体管芯且包含用于显露第二半导体管芯的衬垫的第一开口。抗电弧图案安置于钝化层上方。导电端子安置于第二半导体管芯的衬垫上方且电连接到第二半导体管芯的衬垫。在一些实施例中，抗电弧图案的顶部表面完全由导电端子覆盖。在一些实施例中，抗电弧图案分散于钝化层的第一开口外部。在一些实施例中，导电端子各自包含晶种图案和晶种图案上的凸块，晶种图案覆盖抗电弧图案且延伸到第一开口中，且凸块通过晶种图案与抗电弧图案间隔开。在一些实施例中，半导体结构进一步包含后钝化层，其中抗电弧图案安置于钝化层的顶部表面上，抗电弧图案包含第一部分和第二部分，抗电弧图案的第一部分定位于钝化层与导电端子当中的第一导电端子之间，且抗电弧图案的第二部分定位于钝化层与后钝化层之间。在一些实施例中，后钝化层延伸到第一开口中且包含用于显露第二半导体管芯的衬垫的部分的第二开口，且导电端子当中的第二导电端子通过后钝化层的第二开口来电连接到第二半导体管芯的衬垫的部分。在一些实施例中，后钝化层包含比钝化层的第一开口更宽的第三开口，且抗电弧图案的第一部分分散于第三开口中。在一些实施例中，半导体进一步包含后钝化层，所述后钝化层覆盖钝化层和抗电弧图案，其中后钝化层延伸到第一开口中且包含用于显露第二半导体管芯的衬垫的部分的第二开口，且抗电弧图案在后钝化层与钝化层之间。在一些实施例中，抗电弧图案通过后钝化层与导电端子间隔开。
根据本公开的一些其它实施例，提供一种半导体结构包含第一半导体管芯、第二半导体管芯、绝缘密封体、钝化层、电荷扩散图案以及导电端子。第一半导体管芯包含第一半导体衬底、第一半导体衬底上方的第一内连线结构以及第一内连线结构上方的第一接合结构。第二半导体管芯堆叠于第一半导体管芯上方。第二半导体管芯包含第二半导体衬底、第二内连线结构以及第二接合结构，其中第二内连线结构和第二接合结构安置于第二半导体衬底的相对表面上，且第二半导体管芯通过第一接合结构和第二接合结构来电连接第一半导体管芯。绝缘密封体横向地密封第一半导体管芯和第二半导体管芯。钝化层安置于第二半导体管芯的第二内连线结构上方且包含用于显露第二半导体管芯的衬垫的第一开口。导电端子安置于第二半导体管芯的衬垫上方且电连接到第二半导体管芯的衬垫。电荷扩散图案安置于导电端子与钝化层之间。在一些实施例中，绝缘密封体包括第一密封体部分和第二密封体部分，第一半导体管芯由第一密封体部分横向地密封，且第二半导体管芯由第二密封体部分横向地密封。在一些实施例中，电荷扩散图案分散于钝化层的第一开口外部，电荷扩散图案的顶部表面完全由导电端子覆盖，导电端子各自包含晶种图案和晶种图案上的凸块，晶种图案覆盖电荷扩散图案且延伸到第一开口中，且凸块通过晶种图案与电荷扩散图案间隔开。在一些实施例中，半导体结构进一步包含后钝化层，其中电荷扩散图案安置于钝化层的顶部表面上且包含第一部分和第二部分，电荷扩散图案的第一部分定位于钝化层与导电端子的部分之间，且电荷扩散图案的第二部分定位于钝化层与后钝化层之间。在一些实施例中，半导体结构进一步包含后钝化层，后钝化层覆盖钝化层和电荷扩散图案，其中后钝化层延伸到第一开口中且包含用于显露第二半导体管芯的衬垫的部分的第二开口，且电荷扩散图案在后钝化层与钝化层之间。在一些实施例中，电荷扩散图案是电浮动的。
根据本公开的一些其它实施例，提供包含以下的一种半导体结构的制造方法。将上部层半导体管芯接合到底部层半导体管芯，其中上部层半导体管芯包括衬垫。钝化层形成于上部层半导体管芯的顶部表面上方。抗电弧图案形成于钝化层上方，其中钝化层包括用于显露上部层半导体管芯的衬垫的开口。导电端子形成于上部层半导体管芯上方，其中导电端子电连接到上部层半导体管芯的衬垫。在一些实施例中，在上部层半导体管芯上方形成导电端子之后，抗电弧图案电连接到导电端子。在一些实施例中，通过在沉积抗电弧材料之后进行图案化工艺来形成抗电弧图案，且通过将导电端子用作掩模来执行图案化工艺。在一些实施例中，方法进一步包含：在钝化层上方形成后钝化层以覆盖抗电弧图案的至少一部分。在一些实施例中，在上部层半导体管芯上方形成导电端子之后，抗电弧图案与导电端子电绝缘。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本公开的方面。本领域的技术人员应了解，他们可轻易地将本公开用作设计或修改用于实现本文中所引入的实施例的相同目的和/或达成相同优点的其它工艺和结构的基础。本领域的技术人员还应认识到，此类等效构造并不脱离本公开的精神和范围，且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代和更改。

Claims (1)

1.一种半导体结构，其特征在于，包括：
第一半导体管芯；
第二半导体管芯，堆叠于所述第一半导体管芯上方；
钝化层，覆盖所述第二半导体管芯且包括用于显露所述第二半导体管芯的衬垫的第一开口；
抗电弧图案，安置于所述钝化层上方；以及
导电端子，安置于所述第二半导体管芯的所述衬垫上方且电连接到所述第二半导体管芯的所述衬垫。
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