CN111293090A - 连接结构及其形成方法 - Google Patents

连接结构及其形成方法 Download PDF

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Publication number
CN111293090A
CN111293090A CN201910962639.0A CN201910962639A CN111293090A CN 111293090 A CN111293090 A CN 111293090A CN 201910962639 A CN201910962639 A CN 201910962639A CN 111293090 A CN111293090 A CN 111293090A
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passivation layer
conductive pattern
conductive
pattern
layer
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CN201910962639.0A
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金钟润
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN111293090A publication Critical patent/CN111293090A/zh
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Abstract

提供了一种用于半导体封装的连接结构，该连接结构包括：具有开口的第一钝化层；穿透第一钝化层并从第一钝化层向上突出的第一导电图案；第一钝化层上覆盖第一导电图案的第二钝化层；第二钝化层上电连接到第一导电图案的第二导电图案；第二钝化层上覆盖第二导电图案的第三钝化层；以及开口中电连接到第一导电图案的外部端子，其中，第一导电图案比第二导电图案厚。

Description

连接结构及其形成方法
相关申请的交叉引用
本申请要求于2018年12月6日在韩国知识产权局递交的韩国专利申请No.10-2018-0155947的优先权，其公开内容通过引用合并于此。
技术领域
本发明构思的示例实施例涉及一种用于半导体封装的连接结构及其形成方法。
背景技术
随着半导体技术的不断发展，半导体芯片越来越小型化。与此相对，各种功能集成到单个半导体芯片中。因此，半导体芯片在小面积上具有大量输入/输出焊盘。
结果，考虑改进的半导体芯片封装。
发明内容
本发明构思的示例实施例提供了一种用于半导体封装的具有改进结构稳定性的连接结构及其形成方法。
示例实施例还提供了一种用于半导体封装的具有增强电特性的连接结构及其形成方法。
示例实施例还提供了一种用于半导体封装的没有图案异常的连接结构及其形成方法。
根据示例实施例的一方面，提供了一种连接结构，该连接结构可以包括：第一钝化层，具有开口；第一导电图案，穿透第一钝化层并从第一钝化层向上突出；第二钝化层，在第一钝化层上并覆盖第一导电图案；第二导电图案，在第二钝化层上并电连接到第一导电图案；第三钝化层，在第二钝化层上并覆盖第二导电图案；以及外部端子，在开口中并电连接到第一导电图案。第一导电图案可以比第二导电图案厚。
根据示例实施例的一方面，提供了一种连接结构，该连接结构可以包括：承载基板；第一钝化层、第二钝化层和第三钝化层，顺序设置在承载基板上；第一导电图案，穿透第一钝化层并从第一钝化层向上突出；以及第二导电图案，在第二钝化层上并电连接到第一导电图案。第一导电图案可以比第二导电图案厚。
根据示例实施例的一方面，提供了一种形成连接结构的方法，该方法可以包括：在承载基板上形成具有多个第一开口的第一钝化层；形成多个第一导电图案，所述多个第一导电图案填充第一开口并从第一钝化层向上突出；在第一钝化层上形成第二钝化层，所述第二钝化层具有暴露第一导电图案的多个第二开口；在第二钝化层上形成多个第二导电图案，所述多个第二导电图案填充第二开口并与第一导电图案电连接；以及在第二钝化层上形成覆盖第二导电图案的第三钝化层。
附图说明
图1A至图1G图示了示出根据示例实施例的形成半导体封装的连接结构的方法的横截面图。
图1H图示了示出根据示例实施例的图1G的一部分的放大横截面图。
图2A至图2C图示了示出根据示例实施例的用于半导体封装的图1G所示的连接结构的示例的横截面图。
图3A至图3D图示了示出根据示例实施例的制造半导体封装的方法的横截面图。
图4A至图4F图示了示出根据示例实施例的图3D所示的半导体封装的示例的横截面图。
具体实施方式
下面将结合附图描述根据本发明构思的示例实施例的半导体封装的连接结构及其形成方法。
通过所附权利要求和参考附图讨论的说明书，本发明构思的优点和方面将是显而易见的。在权利要求中清楚地要求并且具体指出了本发明构思。然而，通过结合附图参考说明书可以最好地理解本发明构思。在说明书中，贯穿附图，相同的附图标记表示相同的部件。
应理解，当一元件或层被称为在另一元件或层“上方”、“之上”、“上”、“连接到”或“耦接到”另一元件或层时，该元件或层可以直接在该另一元件或层上方、之上、上、直接连接到或耦接到该另一元件或层，或者可以存在中间元件或层。相反，当一元件被称为“直接在”另一元件或层“上方”、“之上”、“上”、“直接连接到”或“直接耦接到”另一元件或层时，不存在中间元件或层。贯穿附图，相同标记表示相同元件。
为便于描述，空间相对术语如“在......之下”、“在......下方”、“下”、“在......上方”、“在......之上”、“上”等在本文中可以用来描述如在附图中所示的一个元件或者特征与其他元件或者特征的关系。应理解，空间相对术语除了包括附图中示出的取向之外，还意在包含器件在使用中或操作中的不同取向。例如，如果附图中的器件被翻转，则被描述为在其他元件或者特征“下方”或者“之下”的元件将取向在该其它元件或者特征的“上方”。因此，术语“下方”可以包括上方和下方两种取向。器件可以以其他方式取向(旋转90度或在其他方向)，且可以相应地解释本文中使用的空间相对描述语。
图1A至图1G图示了示出根据示例实施例的形成半导体封装的连接结构的方法的横截面图。图1H图示了示出图1G的一部分的放大横截面图。
参考图1A，可以提供承载基板100。承载基板100可以是包括导电材料、半导体材料或介电材料的刚性基板。例如，承载基板100可以是裸硅晶片或玻璃基板。下钝化层105可以形成在承载基板100上。
下钝化层105可以包括介电材料。例如，可以通过沉积氧化硅、氮化硅或聚合物来形成下钝化层105。可以在下钝化层105上沉积介电材料，然后图案化该介电材料以形成具有一个或多个第一开口111的第一钝化层110。
第一钝化层110可以包括与下钝化层105的材料相同或相似的材料。例如，第一钝化层110可以包括氧化硅、氮化硅或聚合物。每个第一开口111可以部分地露出下钝化层105。当在平面图中观察时，每个第一开口111可以具有圆形形状、椭圆形形状、矩形形状、多边形形状或任意形状。
还可以在承载基板100和下钝化层105之间设置粘合剂层101。粘合剂层101可以是光敏粘合剂。在以下描述中，为了简洁起见，将省略粘合剂层101。
参考图1B，可以在承载基板100上设置具有相对较小厚度的第一籽晶层112a和具有相对较大厚度的第一导电层114a。第一籽晶层112a可以覆盖第一钝化层110，并且还覆盖通过第一开口111部分地暴露的下钝化层105。第一导电层114a可以具有足以覆盖第一籽晶层112a并填充第一开口111的厚度。
与第一导电层114a相同或相似，第一籽晶层112a可以通过镀覆或沉积金属或其合金如铜(Cu)、钛(Ti)、其组合或其合金来形成。可以使用第一籽晶层112a通过电镀工艺来形成第一导电层114a。第一导电层114a可以包括例如铜(Cu)、铝(Al)、镍(Ni)、金(Au)、银(Ag)、铂(Pt)、其组合或其合金。
参考图1C，第一籽晶层112a和第一导电层114a可以分别转换为第一籽晶图案112和第一导电图案114。例如，第一籽晶层112a可以被图案化以形成彼此分离的第一籽晶图案112。同样地，第一导电层114a可以被图案化以形成彼此分离的第一导电图案114。可以同时图案化第一籽晶层112a和第一导电层114a。第一导电图案114可以填充对应的第一开口111，并且从第一钝化层110向上部分地突出。第一籽晶图案112可以设置在对应的第一导电图案114下方。例如，第一籽晶图案112可以覆盖对应的第一导电图案114的底表面。
当在横截面中观察时，每个第一导电图案114可以具有“T”形状。当在横截面中观察时，每个第一籽晶图案112可以具有沿着对应的第一导电图案114的底表面延伸的弯曲形状。当在平面图中观察时，第一籽晶图案112和第一导电图案114中的每一个可以具有圆形形状、椭圆形形状、矩形形状、多边形形状或任意形状。
参考图1D，可以形成第二钝化层120以覆盖第一钝化层110。例如，可以在第一钝化层110上沉积介电材料，然后图案化该介电材料以形成具有一个或多个第二开口121的第二钝化层120。第二钝化层120可以包括与第一钝化层110的材料相同或相似的材料。例如，第二钝化层120可以包括氧化硅、氮化硅或聚合物。每个第二开口121可以部分地露出下方的第一导电图案114。当在平面图中观察时，每个第二开口121可以具有圆形形状、椭圆形形状、矩形形状、多边形形状或任意形状。
参考图1E，可以在第二钝化层120上设置有具有相对较小厚度的第二籽晶层122a和具有相对较大厚度的第二导电层124a。第二籽晶层122a可以覆盖第二钝化层120，并且还覆盖通过第二开口121部分地暴露的第一导电图案114。第二导电层124a可以具有足以覆盖第二籽晶层122a并填充第二开口121的厚度。
第二籽晶层122a和第二导电层124a的形成可以与上面参考图1B所述的第一籽晶层112a和第一导电层114a的形成相同或相似。例如，第二籽晶层122a可以通过镀覆或沉积金属或其合金如铜(Cu)、钛(Ti)、其组合或其合金来形成。第二导电层124a可以通过电镀工艺形成，其中使用第二籽晶层122a来镀覆金属如铜(Cu)或其合金。
参考图1F，可以同时图案化第二籽晶层122a和第二导电层124a。因此，第二籽晶层122a可以形成为彼此分离的第二籽晶图案122。同样地，第二导电层124a可以形成为彼此分离的第二导电图案124。第二导电图案124可以填充对应的第二开口121，并且与对应的第一导电图案114电连接。第二籽晶图案122可以设置在对应的第二导电图案124下方。
每个第二导电图案124可以具有在第二钝化层120上水平延伸的线部分和竖直穿透第二钝化层120的过孔部分。当在横截面中观察时，每个第二籽晶图案122可以具有沿着对应的第二导电图案124的底表面延伸的弯曲形状。
参考图1G，可以执行与上面参考图1A至图1C或图1D至图1F所述的工艺相同或相似的工艺，以在第二钝化层120上形成第三钝化层130、第三籽晶图案132和第三导电图案134。第三导电图案134可以电连接到对应的第二导电图案124。可以在第三钝化层130上形成第四钝化层140、第四籽晶图案142和第四导电图案144。第四导电图案144可以电连接到对应的第三导电图案134。
可以通过上述工艺提供第一连接结构11。第一连接结构11可以形成为晶片级或芯片级。例如，当承载基板100是裸硅晶片或大小(例如，直径)与裸硅晶片的大小(例如，直径)相同或相似的玻璃基板时，可以进一步执行切片工艺以将晶片级承载基板100分离为多个芯片级第一连接结构11。
因为第一连接结构11包括刚性承载基板100，所以第一连接结构11可以具有机械和结构稳定性。因此，可以防止第一连接结构11翘曲和/或损坏，并且还可以在后续工艺中容易地处理。第一连接结构11可以在后续工艺中加工，然后用作用于半导体封装的封装基板或用于任何其他半导体器件的插入基板。下面将参考图3A至图3D和图4A至图4F讨论这些用途。
对于第一连接结构11，第一导电图案114可以用作诸如焊球之类的端子将附接到的凸块下金属(UBM)。相反，第二导电图案124和第三导电图案134中的每一个可以用作电连接到第一导电图案114的再分布层。第四导电图案144可以通过第二导电图案124和第三导电图案134电连接到第一导电图案114，并且第四导电图案144可以用作诸如焊球或焊料凸块之类的端子将附接到的连接焊盘。又如，第四导电图案144可以用作再分布层。
在某些实施例中，可以不形成第三导电图案134和/或第四导电图案144。例如，第一连接结构11可以包括用作凸块下金属(UBM)的第一导电图案114和用作再分布层的第二导电图案124，但是既不包括第三导电图案134也不包括第四导电图案144。再如，第一连接结构11可以包括用作凸块下金属(UBM)的第一导电图案114、用作再分布层的第二导电图案124、以及用作连接焊盘的第四导电图案144，但不包括第三导电图案134。在其他实施例中，第一连接结构11还可以包括第三导电图案134和第四导电图案144之间用作再分布层的导电图案。
第一导电图案114、第二导电图案124、第三导电图案134和第四导电图案144中的每一个可以具有在第一钝化层110、第二钝化层120、第三钝化层130和第四钝化层140中的对应钝化层上水平延伸的头部部分、以及竖直穿透第一钝化层110、第二钝化层120、第三钝化层130和第四钝化层140中的对应钝化层的尾部部分。第一导电图案114的头部部分和尾部部分可以一体地合并以构成单个凸块下金属(UBM)。不同地，第二导电图案124、第三导电图案134和第四导电图案144中的每一个的尾部部分可以用作过孔。第二导电图案124和第三导电图案134中的每一个的头部部分可以是再分布层，并且第四导电图案144的头部部分可以是连接焊盘。
参考图1H，第一导电图案114的厚度可以大于第二导电图案124、第三导电图案134和第四导电图案144的厚度。为了便于描述，第一籽晶图案112可以是包括在第一导电图案114中的构成元件。该说明也适用于第二导电图案124、第三导电图案134和第四导电图案144。
第一导电图案114的第一厚度T1可以分别大于第二导电图案124的第二厚度T2、第三导电图案134的第三厚度T3和第四导电图案144的第四厚度T4。第二厚度T2、第三厚度T3和第四厚度T4可以彼此相同或相似。备选地，第二厚度T2和第三厚度T3可以彼此相同或相似，并且第四厚度T4可以大于或小于第二厚度T2和第三厚度T3中的每一个。第一厚度T1可以指示第一导电图案114的总厚度，并且第二厚度T2、第三厚度T3和第四厚度T4中的每一个可以指示实质部分(即，第二导电图案124、第三导电图案134和第四导电图案144中的相应导电图案的头部部分)的厚度。
第一钝化层110、第二钝化层120、第三钝化层130和第四钝化层140可以具有彼此不同的厚度。例如，第一钝化层110的第一厚度Tp1可以与第三钝化层130的第三厚度Tp3和第四钝化层140的第四厚度Tp4相同或相似。备选地，第一厚度Tp1可以大于或小于第三厚度T3和第四厚度T4中的每一个。第二钝化层120的第二厚度Tp2可以大于第一厚度T1、第三厚度T3和第四厚度T4中的每一个。或者，第一钝化层110、第二钝化层120、第三钝化层130和第四钝化层140可以具有相同或相似的厚度。
返回参考图1G，如上面参考图1A至图1D所述，可以在形成第一钝化层110之后形成第一导电图案114，然后可以在第一钝化层110上形成第二钝化层120以覆盖第一导电图案114。尽管第一导电图案114比第二导电图案124、第三导电图案134和第四导电图案144厚(如上面参考图1H所述)，但是由于第一钝化层110预先形成为包围第一导电图案114的尾部部分，因此第二钝化层120可以形成为仅覆盖第一导电图案114的头部部分，在这种情况下，头部部分的厚度小于第一导电图案114的第一厚度T1。结果，第二钝化层120可以形成为平坦的而没有起伏(或波浪形状)，这将在下面讨论。
与上述不同，当在承载基板100上或在下钝化层105上形成相对厚的第一导电图案114之后形成特定钝化层以覆盖第一导电图案114时，有可能该特定钝化层在相邻的第一导电图案114之间具有起伏。在该特定钝化层上形成第二导电图案124的情况下，第二导电图案124可以沿着该特定钝化层的起伏而弯曲。具有起伏的该特定钝化层可以给形成在该特定钝化层上的第二导电图案124带来图案异常，并且还可以导致形成在第二导电图案124上的任何其他导电图案的图案异常。导电图案的这种图案异常可能导致导电图案之间的电短路或开路。
根据示例实施例，因为第一钝化层110在第一导电图案114之前形成，然后形成第二钝化层120来覆盖第一导电图案114，所以第二钝化层120可以具有平坦形状而没有起伏。因此，可以防止导电图案出现诸如由钝化层的起伏而引起的图案异常等问题。
图2A至图2C图示了示出根据示例实施例的用于半导体封装的图1G所示的连接结构的示例的横截面图。
参考图2A，可以提供第二连接结构12以进一步包括至少一个第一虚设图案114d和/或至少一个第二虚设图案124d。例如，一个或多个第一虚设图案114d可以与第一导电图案114同时形成。类似地，一个或多个第二虚设图案124d可以与第二导电图案124同时形成。虽然未示出，但是还可以在第三钝化层130上形成第三虚设图案。
每个第一虚设图案114d可以设置在相邻的第一导电图案114之间的第一钝化层110上。第一籽晶图案112可以设置在第一钝化层110和第一虚设图案114d之间。第一虚设图案114d可以防止第二钝化层120在第一导电图案114之间具有起伏。当在平面图中观察时，每个第一虚设图案114d可以具有矩形形状、多边形形状、圆形形状、椭圆形形状或任意形状。
每个第二虚设图案124d可以设置在相邻的第二导电图案124之间的第二钝化层120上。第二籽晶图案122可以设置在第二钝化层120和第二虚设图案124d之间。第二虚设图案124d可以防止第三钝化层130在第二导电图案124之间具有起伏。当在平面图中观察时，每个第二虚设图案124d可以具有矩形形状、多边形形状、圆形形状、椭圆形形状或任意形状。
参考图2B，可以提供第三连接结构13以进一步包括第一附加图案114g、第二附加图案124g、第三附加图案134g和第四附加图案144g。例如，一个或多个第一附加图案114g可以与第一导电图案114同时形成。每个第一附加图案114g可以设置在相邻的第一导电图案114之间的第一钝化层110上。第一籽晶图案112可以设置在第一钝化层110和第一附加图案114g之间。第一附加图案114g的位置可以不限于第一导电图案114之间。
类似地，第二钝化层120、第三钝化层130和第四钝化层140上可以分别设置有电连接到第一附加图案114g的第二附加图案124g、第三附加图案134g和第四附加图案144g。第二附加图案124g、第三附加图案134g和第四附加图案144g可以分别与第二导电图案124、第三导电图案134和第四导电图案144同时形成。第一附加图案114g、第二附加图案124g、第三附加图案134g和第四附加图案144g可以用作用于电力输送或用于电接地的导电图案。第一附加图案114g、第二附加图案124g和第三附加图案134g可以防止在形成第二钝化层120、第三钝化层130和第四钝化层140时发生图案异常如起伏。
第一附加图案114g、第二附加图案124g、第三附加图案134g和第四附加图案144g的平面形状可以分别与第一导电图案114、第二导电图案124、第三导电图案134和第四导电图案144的平面形状相同或相似。例如，当在平面图中观察时，第一附加图案114g的形状(例如，圆形形状)可以与第一导电图案114的形状相同或相似。
参考图2C，可以提供没有下钝化层105的第四连接结构14。例如，第一钝化层110可以直接形成在承载基板100上，或者可以提供粘合剂层(参见图1的101)以在承载基板100上形成第一钝化层110。可选地，还可以形成第一虚设图案114d和第二虚设图案124d。代替第一虚设图案114d和第二虚设图案124d，还可以如图2B所示形成第一附加图案114g至第四附加图案144g。
图3A至图3D图示了示出根据示例实施例的制造半导体封装的方法的横截面图。
参考图3A，半导体芯片200可以设置在第一连接结构11上。半导体芯片200可以包括存储器电路、逻辑电路或其组合。半导体芯片200可以包括与第四导电图案114对应的芯片焊盘210。诸如焊球之类的连接端子220可以设置在芯片焊盘210和第四导电图案144之间。半导体芯片200可以通过连接端子220电连接到第一连接结构11。
参考图3B，可以在第一连接结构11上形成模塑层240，从而覆盖半导体芯片200。模塑层240可以包括环氧树脂模塑料(EMC)。可选地，在形成模塑层240之前，还可以在第一连接结构11和半导体芯片200之间形成底填充层230。底填充层230可以包括与模塑层240的材料相同或相似的材料。
参考图3C，可以去除承载基板100。当在承载基板100和下钝化层105之间具有图1A所示的粘合剂层101时，可以用激光或紫外线照射粘合剂层101，以使承载基板100与下钝化层105分离。可以对由于承载基板100的分离而露出的下钝化层105执行图案化工艺，因此可以形成开口106以暴露第一导电图案114。例如，可以通过对下钝化层105执行蚀刻工艺来形成开口106。因此，开口106可以建立如下所述将要形成外部端子的位置(参见图3D的108)。可以可选地执行蚀刻工艺以去除第一籽晶图案112通过开口106暴露的部分。
参考图3D，外部端子108可以形成为与第一导电图案114电连接。例如，可以设置焊料并回流焊料以形成与第一导电图案114对应的外部端子108例如焊球。因此，半导体封装1可以被制造为包括安装在第一连接结构11上的半导体芯片200。第一连接结构11可以用作半导体封装1的封装基板。
如上面参考图3C所述，可以去除第一籽晶图案112通过开口106暴露的部分。因此，第一籽晶图案112可以不设置在第一导电图案114和外部端子108之间。在这种情况下，在第一导电图案114和外部端子108之间的界面处可以不产生金属间化合物。附加地或备选地，用于形成外部端子108的焊料可以具有对第一导电图案114的改善润湿性。部分去除第一籽晶图案112可以不是必要的过程，因此如果不必要则可以省略。
图4A至图4F图示了示出根据示例实施例的图3D所示的半导体封装的示例的横截面图。
参考图4A，半导体封装2可以设置为包括安装在用作封装基板的第一连接结构11上的半导体芯片200。可以不去除第一籽晶图案112通过开口106暴露的部分。因此，第一籽晶图案112可以介于第一导电图案114和外部端子108之间。
第一连接结构11可以替换为第二连接结构12、第三连接结构13和第四连接结构14之一，如下面参考图4B至图4E所述。详细描述可以如下。
参考图4B，半导体封装3可以设置为包括安装在用作封装基板的第二连接结构12上的半导体芯片200。如上面参考图2A所述，第二连接结构12可以包括形成在相邻的第一导电图案114之间的第一钝化层110上的一个或多个第一虚设图案114d、以及形成在相邻的第二导电图案124之间的第二钝化层120上的一个或多个第二虚设图案124d。第一虚设图案114d和第二虚设图案124d可以是电隔离的，因此可以不参与第二连接结构12和半导体芯片200之间的电连接。如上面参考图2A所述，第一虚设图案114d和第二虚设图案124d可以防止在形成第二钝化层120和第三钝化层130时发生图案异常如起伏。
参考图4C，半导体封装4可以设置为包括安装在用作封装基板的第三连接结构13上的半导体芯片200。如上面参考图2B所述，第三连接结构13可以包括分别形成在第一钝化层110、第二钝化层120、第三钝化层130和第四钝化层140上的第一附加图案114g、第二附加图案124g、第三附加图案134g和第四附加图案144g。第一附加图案114g、第二附加图案124g、第三附加图案134g和第四附加图案144g可以用作向半导体芯片200提供电力或者使半导体芯片200电接地所需的导电图案。如上面参考图2B所述，第一附加图案114g、第二附加图案124g和第三附加图案134g可以防止在形成第二钝化层120、第三钝化层130和第四钝化层140时发生图案异常如起伏。
参考图4D，半导体封装5可以设置为包括安装在用作封装基板的第三连接结构14上的半导体芯片200。如上面参考图2C所述，第四连接结构14可以包括形成在第一钝化层110上的第一虚设图案114d和/或形成在第二钝化层120上的第二虚设图案124d。备选地，代替第一虚设图案114d和第二虚设图案124d，半导体封装5可以包括分别形成在第一钝化层110至第四钝化层140上的第一附加图案114g至第四附加图案144g，如图2B所示。
参考图4E，半导体封装6可以与图4D所示的半导体封装5相同或相似地配置。与半导体封装5不同，第一钝化层110可以被部分蚀刻并变薄。例如，第一钝化层110可以经历蚀刻工艺以从第一钝化层110去除表面损伤或外来物质，该表面损坏或外来物质可能是在图2C的第四连接结构14中从第一钝化层110分离承载基板100时产生的。附加地或备选地，可以执行蚀刻工艺以减小第一钝化层110的厚度。
当第一钝化层110的厚度减小时，第一导电图案114可以从变薄的第一钝化层110向外突出。第一导电图案114的突出可以增加第一导电图案114和外部端子108之间的接触面积。增加的接触面积可以减小第一导电图案114和外部端子108之间的接触电阻。
参考图4F，半导体封装7可以设置为包括安装在用作封装基板的第一连接结构11上的半导体芯片200和半导体封装30。半导体封装7可以具有封装内封装配置，其中半导体封装30安装在图3D的半导体封装1内。第一连接结构11可以替换为图4B至图4E所示的第二连接结构12、第三连接结构13和第四连接结构14之一。
半导体封装30可以包括安装在封装基板300上的一个或多个半导体芯片320和330、将半导体芯片320和330电连接到封装基板300的接合线350、以及包封半导体芯片320和330的模塑层340。半导体封装30可以设置在包封半导体芯片200的模塑层240内。
一些第四导电图案144可以用于第一连接结构11和半导体芯片200之间的电连接。其他第四导电图案144可以用于第一连接结构11和半导体封装30之间的电连接。例如，第一连接结构11和半导体芯片200可以通过半导体芯片200的芯片焊盘210与一些第四导电图案144之间的连接端子220如焊球彼此电连接。第一连接结构11和半导体封装30可以通过封装基板300与其他第四导电图案144之间的连接端子360如焊球彼此电连接。
封装基板300可以包括内部图案302，接合线350和连接端子360电连接到内部图案302。内部图案302可以与第一连接结构11相同或相似地配置。例如，内部图案302可以包括耦合到连接端子360的下导电图案314、耦合到接合线350的上导电图案334、以及将下导电图案314和上导电图案334彼此电连接的中间导电图案324。
下导电图案314可以对应于第一导电图案114，上导电图案334可以对应于第四导电图案144，并且中间导电图案324可以对应于第二导电图案124或第三导电图案134。封装基板300的形成可以与第一连接结构11的形成相同或相似。
包括内部图案302的封装基板300可以用作插入器或双层再分布层。第一连接结构11可以替换为图4B至图4E所示的第二连接结构12、第三连接结构13和第四连接结构14之一。
根据本发明构思，在导电图案如相对厚的凸块下金属之间的钝化层上以及在形成于该钝化层上的特定图案上，可以不出现图案异常。因此，钝化层或特定图案可以没有可能导致电气故障(例如，电短路或开路)的图案异常。总之，连接结构和包括该连接结构的半导体封装可以改善结构稳定性和电特性。
本发明构思的该详细描述不应被解释为限于本文阐述的实施例，本发明构思旨在覆盖在不脱离本发明的精神和范围的情况下对上述实施例的各种组合、修改和变化。所附权利要求应被解释为包括其他实施例。

Claims (25)

1.一种连接结构，包括：
第一钝化层，具有开口；
第一导电图案，穿透所述第一钝化层并从所述第一钝化层向上突出；
第二钝化层，在所述第一钝化层上并覆盖所述第一导电图案；
第二导电图案，在所述第二钝化层上并电连接到所述第一导电图案；
第三钝化层，在所述第二钝化层上并覆盖所述第二导电图案；以及
外部端子，在所述开口中并电连接到所述第一导电图案，
其中，所述第一导电图案比所述第二导电图案厚。
2.根据权利要求1所述的连接结构，其中，所述第一导电图案包括：
头部部分，在所述第一钝化层上水平延伸并与所述第二导电图案连接；以及
尾部部分，竖直穿透所述第一钝化层并与所述外部端子连接。
3.根据权利要求1所述的连接结构，其中，所述第二导电图案包括：
再分布层部分，在所述第二钝化层上水平延伸；以及
过孔部分，竖直穿透所述第二钝化层并与所述第一导电图案连接。
4.根据权利要求1所述的连接结构，其中，所述第二钝化层是所述第一钝化层至所述第三钝化层之中最厚的钝化层。
5.根据权利要求1所述的连接结构，还包括：第三导电图案，在所述第三钝化层上并电连接到所述第二导电图案。
6.根据权利要求1所述的连接结构，还包括：附加图案，在所述第一钝化层和所述第二钝化层中至少之一上。
7.根据权利要求6所述的连接结构，其中，所述第一导电图案和所述第二导电图案中至少之一被设置为多个，并且
其中，所述附加图案形成在所述多个第一导电图案之间或在所述多个第二导电图案之间。
8.根据权利要求6所述的连接结构，其中，所述附加图案是以下之一：
所述第一钝化层和所述第二钝化层中至少之一上电隔离的虚设图案；以及
用于电力输送或用于电接地的导电图案。
9.根据权利要求1所述的连接结构，还包括所述第一导电图案的底表面上的第一籽晶图案，所述第一导电图案的底表面面对所述外部端子。
10.根据权利要求9所述的连接结构，其中，所述第一籽晶图案不设置在所述第一导电图案与所述外部端子之间的界面处。
11.根据权利要求1所述的连接结构，还包括所述第二导电图案的底表面上的第二籽晶图案，所述第二导电图案的底表面面对所述第一导电图案。
12.一种连接结构，包括：
承载基板；
第一钝化层、第二钝化层和第三钝化层，顺序设置在所述承载基板上；
第一导电图案，穿透所述第一钝化层并从所述第一钝化层向上突出；以及
第二导电图案，在所述第二钝化层上并电连接到所述第一导电图案，
其中，所述第一导电图案比所述第二导电图案厚。
13.根据权利要求12所述的连接结构，其中，所述第一导电图案具有T形状，包括：
头部部分，在所述第一钝化层上水平延伸；以及
尾部部分，竖直穿透所述第一钝化层。
14.根据权利要求12所述的连接结构，其中，所述第二导电图案是再分布层，所述再分布层包括：
线部分，在所述第二钝化层上水平延伸；以及
过孔部分，竖直穿透所述第二钝化层。
15.根据权利要求12所述的连接结构，还包括：第三导电图案，在所述第三钝化层上并电连接到所述第二导电图案。
16.根据权利要求15所述的连接结构，其中，所述第三导电图案是连接焊盘，所述连接焊盘包括：
焊盘部分，在所述第二钝化层上水平延伸；以及
通孔部分，竖直穿透所述第二钝化层。
17.根据权利要求12所述的连接结构，还包括：附加图案，在所述第一钝化层和所述第二钝化层中至少之一上，
其中，所述附加图案是以下之一：
所述第一钝化层和所述第二钝化层中至少之一上电隔离的虚设图案；以及
用于电力输送或用于电接地的导电图案。
18.根据权利要求17所述的连接结构，其中，所述第一导电图案和所述第二导电图案中至少之一被设置为多个，并且
其中，所述附加图案形成在所述多个第一导电图案之间或在所述多个第二导电图案之间。
19.根据权利要求12所述的连接结构，还包括：
所述第一导电图案的底表面上的第一籽晶图案，所述第一导电图案的底表面面对所述承载基板；以及
所述第二导电图案的底表面上的第二籽晶图案，所述第二导电图案的底表面面对所述第一导电图案。
20.根据权利要求12所述的连接结构，其中，所述第二钝化层是所述第一钝化层至所述第三钝化层之中最厚的。
21.一种形成连接结构的方法，所述方法包括：
在承载基板上形成具有多个第一开口的第一钝化层；
形成多个第一导电图案，所述多个第一导电图案填充所述第一开口并从所述第一钝化层向上突出；
在所述第一钝化层上形成第二钝化层，所述第二钝化层具有暴露所述第一导电图案的多个第二开口；
在所述第二钝化层上形成多个第二导电图案，所述多个第二导电图案填充所述第二开口并与所述第一导电图案电连接；以及
在所述第二钝化层上形成覆盖所述第二导电图案的第三钝化层。
22.根据权利要求21所述的方法，其中，在形成所述第一钝化层之后，形成所述第一导电图案。
23.根据权利要求21所述的方法，其中，形成所述第一导电图案包括：
在所述第一钝化层上形成第一籽晶层；
在所述第一籽晶层上形成第一导电层；以及
图案化所述第一导电层和所述第一籽晶层以将所述第一导电层转换为所述第一导电图案，并且同时将所述第一籽晶层转换为与所述第一导电图案对应的多个第一籽晶图案。
24.根据权利要求21所述的方法，其中，形成所述第二导电图案包括：
在所述第二钝化层上形成第二籽晶层；
在所述第二籽晶层上形成第二导电层；以及
图案化所述第二导电层和所述第二籽晶层以将所述第二导电层转换为所述第二导电图案，并且同时将所述第二籽晶层转换为与所述第二导电图案对应的多个第二籽晶图案。
25.根据权利要求21所述的方法，还包括：在所述第三钝化层上形成电连接到所述第二导电图案的多个第三导电图案。
CN201910962639.0A 2018-12-06 2019-10-10 连接结构及其形成方法 Pending CN111293090A (zh)

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