TWI780972B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI780972B
TWI780972B TW110140682A TW110140682A TWI780972B TW I780972 B TWI780972 B TW I780972B TW 110140682 A TW110140682 A TW 110140682A TW 110140682 A TW110140682 A TW 110140682A TW I780972 B TWI780972 B TW I780972B
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Taiwan
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layer
semiconductor device
gold
nickel
manufacturing
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TW110140682A
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English (en)
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TW202320186A (zh
Inventor
鄭湘寧
許文政
王晨聿
郭志明
陳傳迢
何榮華
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頎邦科技股份有限公司
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Priority to TW110140682A priority Critical patent/TWI780972B/zh
Priority to CN202211013137.1A priority patent/CN116072548A/zh
Priority to JP2022132672A priority patent/JP7470748B2/ja
Priority to KR1020220106017A priority patent/KR20230064542A/ko
Priority to US17/896,171 priority patent/US20230135424A1/en
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Publication of TWI780972B publication Critical patent/TWI780972B/zh
Publication of TW202320186A publication Critical patent/TW202320186A/zh

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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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Abstract

一封裝結構包含一第一載板、一種子層、複數個線路、一晶粒及一封膠材料，將一第二載板設置於該封膠材料後，移除該第一載板以顯露該種子層，接著移除該種子層以顯露該些線路，再以化學浸金方式沈積一金層於各該線路上，以形成一半導體裝置，該金層用以避免各該線路氧化，並可提供良好焊接可靠度。

Description

半導體裝置之製造方法
本發明關於一種半導體裝置之製造方法，特別是一種提高半導體裝置焊接可靠度之製造方法。
為了避免線路接觸空氣後氧化，可於線路上形成表面處理層，以阻隔空氣接觸線路，表面處理層一般為化鎳浸金(ENIG, Electroless Nickel Immersion Gold)或化鎳鈀浸金(ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold)，化鎳浸金係透過還原劑將鎳離子還原成鎳金屬，使鎳沈積於銅線路上形成鎳層，再透過置換反應於鎳層上鍍金，反應過程產生的氫氣氣泡會造成氣孔問題，而化鎳鈀浸金係透過化學反應將銅表面置換為鈀後，於鈀核的基礎上以化學鍍方式形成鎳磷合金層，再透過置換反應於鎳磷合金層上鍍金，除了氣孔問題，鎳磷合金層於浸金過程中會被過度蝕刻，進而影響到焊接可靠度。
本發明之目的在於提供一種半導體裝置之製造方法，以化學浸金方式形成金層於封裝結構之線路上，可避免線路氧化，亦可提昇其焊接可靠度。
本發明之一種半導體裝置之製造方法，首先提供一封裝結構，該封裝結構包含一第一載板、一種子層、複數個線路、一晶粒及一封膠材料，該種子層形成於該第一載板上，該些線路形成於該種子層上，該晶粒接合於該些線路，該封膠材料覆蓋該晶粒及該些線路，設置一第二載板於該封膠材料上，接著移除該第一載板以顯露該種子層，並移除該種子層以顯露該些線路，再以化學浸金方式沈積一金層於各該線路上。
請參閱第1圖，於一半導體裝置之製造方法中，首先提供一封裝結構100，該封裝結構100包含一第一載板110及一種子層120，該種子層120形成於該第一載板110上，較佳地，該第一載板110包含一第一基板111及一第一離型層112，該第一離型層112形成於該第一基板111表面，該種子層120形成於該第一離型層112上，其中該第一基板111之材質可為玻璃、矽晶圓或陶瓷，該第一離型層112之材質可為聚醯亞胺(PI)或無機離型劑(鹵素金屬化合物)，該種子層120可為鈦鎢/銅(TiW/Cu)層或鈦/銅(Ti/Cu)層，較佳地，係以濺鍍(sputtering)方式於該第一離型層112鍍上該種子層120。
請參閱第1圖，該封裝結構100另包含複數個線路130、至少一晶粒150及一封膠材料160，該些線路130形成於該種子層120上，該晶粒150接合於該些線路130，該封膠材料160覆蓋該晶粒150及該些線路130，較佳地，該晶粒150藉由凸塊覆晶接合於該些線路130上，該些線路130係藉由一圖案化介電層140形成於該種子層120上，於該種子層120上形成一介電層後，圖案化該介電層以形成複數個開口，該些開口顯露該種子層120，而該些線路130分別形成於該些開口中，該介電層材料可為聚醯亞胺(PI, polyimide)、苯並環丁烯(BCB, benzocyclobutene)或環氧樹脂(epoxy)，在本實施例中，該介電層之材質為聚醯亞胺。
在第一實施例中，各該線路130包含一鎳層131及一銅層132，該鎳層131以純鎳電鍍方式形成於該種子層120，該鎳層131為不含磷之純鎳金屬，不會產生氣孔及磷沈積的問題，因此孔隙率低於化學鍍形成之鎳層，且緻密性高於化學鍍形成之鎳層，該銅層132為形成於該鎳層131上的重分佈線路結構(RDL, redistribution layer)。
請參閱第2圖，接著設置一第二載板200於該封膠材料160上，較佳地，該第二載板200包含一第二基板210及一第二離型層220，該第二基板210之材質可為玻璃、矽晶圓、陶瓷、不鏽鋼、貼霸(矽膠+玻璃纖維)或三明治結構(不鏽鋼+貼霸)，該第二離型層220之材質可為感壓膠(PSA, pressure sensitive adhesive)、環氧樹脂(epoxy)或矽膠(silicon glue)，該第二基板210及該第一基板111可為相同材質或不同材質，本發明不以此為限制。
請參閱第3圖，設置該第二載板200於該封膠材料160後，翻轉半導體裝置，使該第一載板110位於上方而該第二載板200位於下方，請參閱第4圖，接著移除該第一載板110，以顯露該第一載板110下方的該種子層120，在本實施例中，係以機械分離(mechanical debonding)方式使該第一離型層112自該種子層120剝離，藉此移除該第一基板111及該第一離型層112。
請參閱第5圖，移除該第一載板110後，接著移除該種子層120，以顯露該些線路130，較佳地，係以蝕刻方式移除該種子層120，以顯露各該線路130之一頂面130a，在第一實施例中，係以電漿蝕刻(plasma etching)方式移除該種子層120，以顯露各該線路130之該鎳層131。
請參閱第6圖，移除該種子層120後，接著以化學浸金(immersion gold plating)方式沈積一金層300於顯露之各該線路130上，該金層300為表面處理層或鈍化層，用以保護該些線路130，避免該些線路130接觸空氣後氧化，相較於電鍍金層，化學浸金方式形成的該金層300厚度均勻性及覆蓋程度較佳，因此厚度較薄的該金層300與厚度較厚的電鍍金層抗氧化防護效果相近，可達到降低成本的效益。
在第一實施例中，移除該種子層120後，顯露各該線路130之該鎳層131，接著以化學浸金方式使該金層300沈積於該鎳層131上，由於以純鎳電鍍方式形成的該鎳層131不含磷且緻密性高，沈積該金層300時，該鎳層131表面不會被過度蝕刻，亦不易產生黑墊(black pad)，因此具有較佳的抗氧化防護效果，可有效提昇焊接可靠度。
請參閱第7圖，若該半導體裝置為一球柵陣列封裝(BGA, ball grid array)，則於沈積該金層300後，形成一焊球400於該金層300上，完成後續製程後即可得BGA，後續製程包含移除該第二載板200、切割及形成電磁干擾屏蔽罩(EMI shielding layer)等習知製程，在此不贅述，反之，若該半導體裝置為一平面網格陣列封裝(LGA, land grid array)，則無須形成焊球於該金層300，可直接進行後續製程，以取得該半導體裝置。
請參閱第8及9圖，其為本發明之第二實施例，較佳地，使用電漿蝕刻方式移除該種子層120時，可藉由調整電漿蝕刻參數，同時移除該種子層120及部份該圖案化介電層140，而顯露出各該線路130之一頂面130a及一側面130b，因此以化學浸金方式沈積該金層300時，該金層300會沈積於各該線路130之該頂面130a及該側面130b，藉此增加該金層300面積，以提高焊接可靠度，在第二實施例中，以電漿蝕刻方式移除該種子層120及部份該圖案化介電層140後，各該線路130顯露之該頂面130a及該側面130b為該鎳層131之頂面及側面，因此該金層300係沈積於該鎳層131之頂面及側面。
較佳地，於電漿蝕刻該種子層120及部份該圖案化介電層141時，可藉由調整電漿蝕刻參數，使該圖案化介電層140之蝕刻厚度不大於1.5 μm，藉此顯露出該鎳層131之該頂面及該側面，亦同時保有足夠厚度的介電層，以避免失去介電層效果。
第10及11圖為本發明之第三實施例，第三實施例與第一實施例之差異在於各該線路130未包含鎳層，僅包含一銅層132，該銅層132為形成於該種子層120上的重分佈線路結構，移除該種子層120後，顯露該銅層132，再以化學浸金方式沈積該金層300於該銅層132上。
請參閱第12及13圖，在第四實施例中，以電漿蝕刻方式移除該種子層120及部份該圖案化介電層140後，各該線路130顯露之該頂面130a及該側面130b為該銅層132之頂面及側面，因此該金層300係沈積於該銅層132之頂面及側面。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100:封裝結構 110:第一載板 111:第一基板 112:第一離型層 120:種子層 130:線路 130a:頂面 130b:側面 131:鎳層 132:銅層 140:圖案化介電層 150:晶粒 160:封膠材料 200:第二載板 210:第二基板 220:第二離型層 300:金層 400:焊球
第1圖：依據本發明之第一實施例，一封裝結構之剖視圖。 第2至7圖：依據本發明之第一實施例，一半導體裝置之製造方法之剖視示意圖。 第8及9圖：依據本發明之第二實施例，一半導體裝置之製造方法之剖視示意圖。 第10及11圖：依據本發明之第三實施例，一半導體裝置之製造方法之剖視示意圖。 第12及13圖：依據本發明之第四實施例，一半導體裝置之製造方法之剖視示意圖。
130:線路
130a:頂面
131:鎳層
132:銅層
140:圖案化介電層
150:晶粒
160:封膠材料
200:第二載板
210:第二基板
220:第二離型層
300:金層

Claims (13)

  1. 一種半導體裝置之製造方法，其包含：提供一封裝結構，該封裝結構包含一第一載板、一種子層、複數個線路、一晶粒及一封膠材料，該種子層形成於該第一載板上，該些線路係藉由一圖案化介電層形成於該種子層上，該晶粒接合於該些線路，該封膠材料覆蓋該晶粒及該些線路；設置一第二載板於該封膠材料上；移除該第一載板，以顯露該種子層；以電漿蝕刻方式移除該種子層及部份該圖案化介電層，以顯露各該線路之一頂面及一側面；以及以化學浸金方式沈積一金層於各該線路上。
  2. 如請求項1之半導體裝置之製造方法，其中各該線路包含一鎳層及一銅層，該鎳層以純鎳電鍍方式形成於該種子層，該銅層形成於該鎳層，移除該種子層後，顯露該鎳層，再以化學浸金方式沈積該金層於該鎳層上。
  3. 如請求項1之半導體裝置之製造方法，其中各該線路包含一銅層，該銅層形成於該種子層，移除該種子層後，顯露該銅層，再以化學浸金方式沈積該金層於該銅層上。
  4. 如請求項1之半導體裝置之製造方法，其中該金層沈積於各該線路之該頂面及該側面。
  5. 如請求項1之半導體裝置之製造方法，其中各該線路包含一鎳層及一銅層，該鎳層以純鎳電鍍方式形成於該種子層，該銅層形成於該鎳層，以電漿蝕刻方式移除該種子層及部份該圖案化介電層後，顯露該鎳層之一頂面及一 側面。
  6. 如請求項5之半導體裝置之製造方法，其中該金層沈積於該鎳層之該頂面及該側面。
  7. 如請求項1之半導體裝置之製造方法，其中各該線路包含一銅層，該銅層形成於該種子層，以電漿蝕刻方式移除該種子層及部份該圖案化介電層後，顯露該銅層之一頂面及一側面。
  8. 如請求項7之半導體裝置之製造方法，其中該金層沈積於該銅層之該頂面及該側面。
  9. 如請求項1或5或7之半導體裝置之製造方法，其中該圖案化介電層之蝕刻厚度不大於1.5μm。
  10. 如請求項1之半導體裝置之製造方法，其中該第一載板包含一基板及一離型層，該離型層形成於該基板表面，該種子層形成於該離型層上，移除該基板及該離型層後，顯露該種子層。
  11. 如請求項1之半導體裝置之製造方法，其中該種子層為鈦鎢/銅層或鈦/銅層。
  12. 如請求項2或3之半導體裝置之製造方法，其中該銅層為重分佈線路結構。
  13. 如請求項1之半導體裝置之製造方法，其中於沈積該金層後，形成一焊球於該金層上。
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