JP7470748B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP7470748B2
JP7470748B2 JP2022132672A JP2022132672A JP7470748B2 JP 7470748 B2 JP7470748 B2 JP 7470748B2 JP 2022132672 A JP2022132672 A JP 2022132672A JP 2022132672 A JP2022132672 A JP 2022132672A JP 7470748 B2 JP7470748 B2 JP 7470748B2
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layer
semiconductor device
manufacturing
circuits
nickel
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JP2023068617A (ja
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湘寧 鄭
文政 許
晨聿 王
志明 郭
傳迢 陳
榮華 何
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▲き▼邦科技股▲分▼有限公司
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Description

本発明は、半導体装置の製造方法に関し、より詳しくは、半導体装置の溶接の信頼性を高める製造方法に関する。
回路が空気に接触して酸化するのを回避するため、回路に表面処理層を形成し、空気が回路に接触しないように隔離している。表面処理層は一般的に無電解ニッケル浸漬金メッキ（ＥＮＩＧ、Ｅｌｅｃｔｒｏｌｅｓｓ Ｎｉｃｋｅｌ Ｉｍｍｅｒｓｉｏｎ Ｇｏｌｄ）または無電解ニッケル無電解パラジウム浸漬金メッキ（ＥＮＥＰＩＧ、Ｅｌｅｃｔｒｏｌｅｓｓ Ｎｉｃｋｅｌ Ｅｌｅｃｔｒｏｌｅｓｓ Ｐａｌｌａｄｉｕｍ Ｉｍｍｅｒｓｉｏｎ Ｇｏｌｄ）である。無電解ニッケル浸漬金メッキは還元剤によりニッケルイオンをニッケル金属に還元し、銅回路にニッケルを蓄積してニッケル層を形成し、置換反応によりニッケル層に金メッキを施すが、ニッケルの蓄積過程で発生する水素の気泡が気孔問題を引き起こす。無電解ニッケル無電解パラジウム浸漬金メッキは、化学反応により銅表面をパラジウムに置換した後、パラジウム核の基礎に化学メッキ方式によりニッケルリン合金層を形成し、置換反応によりニッケルリン合金層に金メッキを施すが、気孔問題以外に、ニッケルリン合金層の浸漬金メッキ過程で過度にエッチングを行い過ぎ、溶接の信頼性に影響が及ぶことがある。
本発明は、上述に鑑みてなされたものであり、その目的は、浸漬金メッキ方式（ｉｍｍｅｒｓｉｏｎ－ｇｏｌｄ－ｐｌａｔｉｎｇ）でパッケージ構造の回路にゴールドレイヤーを形成し、回路の酸化を回避すると共に、溶接の信頼性を高める半導体装置の製造方法を提供することにある。
上記目的を達成するための主たる発明の半導体装置の製造方法は、まず、第一載置板と、シード層と、複数の回路と、ダイと、成形材料と、を含んで構成されるパッケージ構造を提供する。前記シード層は前記第一載置板に形成され、これら前記回路は前記シード層に形成され、前記ダイは前記回路に接合され、前記成形材料は前記ダイ及び前記回路を被覆している。前記成形材料に第二載置板を設置し、次いで、前記第一載置板を除去して前記シード層を露出し、且つ前記シード層を除去して前記回路を露出し、浸漬金メッキ方式で各前記回路にゴールドレイヤーを蓄積する。
本発明は、上記説明したように構成されているので、以下に記載されるような効果を奏する。
本発明の他の目的、構成及び効果については、以下の発明の実施の形態の項から明らかになる。
本発明の第１実施例に係るパッケージ構造を示す断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第１実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第２実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第２実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第３実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第３実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第４実施例に係る半導体装置の製造方法を示す概略断面図である。 本発明の第４実施例に係る半導体装置の製造方法を示す概略断面図である。
以下、本発明の実施形態について具体的に説明するが、本発明はこれに限定されるものではない。
＜第１実施例＞
図１に示す如く、半導体装置の製造方法において、まず、第一載置板１１０及びシード層１２０を含んで構成されるパッケージ構造１００を提供する。シード層１２０は第一載置板１１０に形成され、好ましくは、第一載置板１１０は第一基板１１１及び第一剥離層１１２を含む。第一剥離層１１２は第一基板１１１の表面に形成され、シード層１２０は第一剥離層１１２に形成されている。第一基板１１１の材質はガラス、シリコンウェハー、またはセラミックであり、第一剥離層１１２の材質はポリイミド（ＰＩ）または無機離型剤（ハロゲン－金属化合物）であり、シード層１２０はチタン・タングステン／銅（ＴｉＷ／Ｃｕ）層またはチタン／銅（Ｔｉ／Ｃｕ）層である。好ましくは、スパッタリング（ｓｐｕｔｔｅｒｉｎｇ）方式で第一剥離層１１２にシード層１２０をメッキする。
図１を参照すると、パッケージ構造１００は複数の回路１３０と、少なくとも１つのダイ１５０と、成形材料１６０と、を更に含んで構成される。これら回路１３０はシード層１２０に形成され、ダイ１５０は回路１３０に接合され、成形材料１６０はダイ１５０及び回路１３０を被覆する。好ましくは、ダイ１５０がフリップチップバンプにより回路１３０に接合され、回路１３０がパターン化された誘電体層１４０によりシード層１２０に形成される。シード層１２０に誘電体層を形成した後、誘電体層をパターン化することで複数の開口部を形成し、開口部はシード層１２０を露出し、回路１３０はこれら開口部中にそれぞれ形成する。誘電体層材料はポリイミド（ＰＩ、ｐｏｌｙｉｍｉｄｅ）、ベンゾシクロブテン（ＢＣＢ、ｂｅｎｚｏｃｙｃｌｏｂｕｔｅｎｅ）、またはエポキシ樹脂（ｅｐｏｘｙ）であり、本実施例では、誘電体層の材質はポリイミドである。
第１実施例において、各回路１３０はニッケル層１３１及び銅層１３２を含み、ニッケル層１３１は純ニッケル電気メッキ方式によりシード層１２０に形成している。ニッケル層１３１の材料はリン非含有純ニッケル金属であり、気孔及びリンの蓄積問題を発生させない。このため、ニッケル層１３１の多孔率（ｐｏｒｏｓｉｔｙ）は化学メッキにより形成されるニッケル層より低く、且つニッケル層１３１の密度（ｄｅｎｓｉｔｙ）は化学メッキにより形成されるニッケル層より高い。銅層１３２はニッケル層１３１に形成される再分布回路構造（ＲＤＬ、ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ ｌａｙｅｒ）である。
図２に示す如く、次いで、成形材料１６０に第二載置板２００を設置する。好ましくは、第二載置板２００が第二基板２１０及び第二剥離層２２０を含み、第二基板２１０の材質はガラス、シリコンウェハー、セラミック、ステンレス、またはシリカゲル／グラスファイバーであり、第二剥離層２２０の材質は感圧接着剤（ＰＳＡ、ｐｒｅｓｓｕｒｅ ｓｅｎｓｉｔｉｖｅ ａｄｈｅｓｉｖｅ）、エポキシ樹脂（ｅｐｏｘｙ）、またはシリカゲル（ｓｉｌｉｃｏｎ ｇｌｕｅ）である。第二基板２１０及び第一基板１１１を同じ材質或いは異なる材質とするが、本発明はこの限りではない。
図３に示す如く、成形材料１６０に第二載置板２００を設置した後、半導体装置を裏返し、第一載置板１１０を上方に位置させ、第二載置板２００を下方に位置させる（図４参照）。次いで、第一載置板１１０を除去し、第一載置板１１０の下方にあるシード層１２０を露出する。本実施例では、機械的剥離（ｍｅｃｈａｎｉｃａｌ ｄｅｂｏｎｄｉｎｇ）方式で第一剥離層１１２をシード層１２０から剥離し、第一基板１１１及び第一剥離層１１２を除去している。
図５に示す如く、第一載置板１１０を除去した後、続いてシード層１２０を除去し、これら回路１３０を露出する。好ましくは、エッチング方式でシード層１２０を除去し、各回路１３０の上面１３０ａを露出する。第１実施例において、プラズマエッチング（ｐｌａｓｍａ ｅｔｃｈｉｎｇ）方式でシード層１２０を除去し、各回路１３０のニッケル層１３１を露出する。
図６に示す如く、シード層１２０を除去した後、続いて浸漬金メッキ（ｉｍｍｅｒｓｉｏｎ ｇｏｌｄ ｐｌａｔｉｎｇ）方式により露出した各回路１３０にゴールドレイヤー３００を蓄積させる。ゴールドレイヤー３００は表面処理層またはパッシベーション層であり、これら回路１３０が酸化するのを回避するように保護するために用いられている。電気メッキゴールドレイヤーと比べると、浸漬金メッキ方式で形成されたゴールドレイヤー３００は、厚さの均一性及び被覆程度が高く、よって、厚さが薄いゴールドレイヤー３００でも、抗酸化防護効果が厚さが厚い電気メッキゴールドレイヤーに近く、コスト削減効果を達成している。
第１実施例において、シード層１２０を除去した後、各回路１３０のニッケル層１３１を露出する。次いで、浸漬金メッキ方式によりニッケル層１３１にゴールドレイヤー３００を蓄積する。純ニッケル電気メッキ方式で形成したニッケル層１３１がリンを非含有であり、且つ密度が高い。ゴールドレイヤー３００を蓄積する際に、ニッケル層１３１の表面を過度にエッチングせず、ブラックパッド（ｂｌａｃｋ ｐａｄ）も発生しにくい。ゴールドレイヤー３００は好ましい抗酸化防護効果を有し、溶接の信頼性を有効的に高めている。
図７に示す如く、半導体装置がボールグリッドアレイパッケージ（ＢＧＡ、ｂａｌｌ ｇｒｉｄ ａｒｒａｙ）である場合、ゴールドレイヤー３００を蓄積した後、ゴールドレイヤー３００にはんだボール４００を形成し、後続のプロセスが完了した後にＢＧＡを取得する。後続のプロセスは第二載置板２００の除去、電磁干渉シールドレイヤー（ＥＭＩ ｓｈｉｅｌｄｉｎｇ ｌａｙｅｒ）の切断及び形成等の従来のプロセスを含み、その説明は省略する。翻って、半導体装置がランドグリッドアレイパッケージ（ＬＧＡ、ｌａｎｄ ｇｒｉｄ ａｒｒａｙ）である場合、ゴールドレイヤー３００にはんだボールを形成する必要がなく、後続のプロセスを直接実行し、半導体装置を取得する。
＜第２実施例＞
本発明の第２実施例の構成を図８及び図９に示す。好ましくは、プラズマエッチング方式を使用してシード層１２０を除去する際に、プラズマエッチングパラメーターを調整することで、シード層１２０及び部分的なパターン化された誘電体層１４０を同時に除去し、各回路１３０の上面１３０ａ及び側面１３０ｂを露出する。これにより、浸漬金メッキ方式でゴールドレイヤー３００を蓄積する際に、ゴールドレイヤー３００が各回路１３０の上面１３０ａ及び側面１３０ｂに蓄積され、ゴールドレイヤー３００面積が増加し、溶接の信頼性が高まる。第２実施例において、プラズマエッチング方式によりシード層１２０及び部分的なパターン化された誘電体層１４０を除去した後、各回路１３０の露出する上面１３０ａ及び側面１３０ｂがニッケル層１３１の上面及び側面となり、これにより、ゴールドレイヤー３００がニッケル層１３１の上面及び側面に蓄積する。
好ましくは、シード層１２０及び部分的なパターン化された誘電体層１４０にプラズマエッチングを行う際に、プラズマエッチングパラメーターを調整することで、パターン化された誘電体層１４０のエッチングの厚さを１．５μｍ以上にせず、ニッケル層１３１の上面及び側面を露出する。十分な厚さの誘電体層を有すると同時に、誘電体層の効果を失効することも回避している。
＜第３実施例＞
本発明の第３実施例の構成を図１０及び図１１に示す。第３実施例の第１実施例との相違点は、各回路１３０がニッケル層を含まず、銅層１３２のみを含み、銅層１３２はシード層１２０の再分布回路構造に形成し、シード層１２０を除去した後、銅層１３２を露出し、浸漬金メッキ方式で銅層１３２にゴールドレイヤー３００を蓄積する点である。
＜第４実施例＞
本発明の第４実施例の構成を図１２及び図１３に示す。第４実施例において、プラズマエッチング方式でシード層１２０及び部分的なパターン化された誘電体層１４０を除去した後、各回路１３０の露出する上面１３０ａ及び側面１３０ｂを銅層１３２の上面及び側面とする。これにより、銅層１３２の上面及び側面にゴールドレイヤー３００を蓄積する。
以上、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の形態で実施可能である。
１００ パッケージ構造
１１０ 第一載置板
１１１ 第一基板
１１２ 第一剥離層
１２０ シード層
１３０ 回路
１３０ａ 上面
１３０ｂ 側面
１３１ ニッケル層
１３２ 銅層
１４０ パターン化された誘電体層
１５０ ダイ
１６０ 成形材料
２００ 第二載置板
２１０ 第二基板
２２０ 第二剥離層
３００ ゴールドレイヤー
４００ はんだボール

Claims (15)

  1. 第一載置板と、シード層と、複数の回路と、ダイと、成形材料と、を含んで構成されるパッケージ構造であって、前記シード層は前記第一載置板に形成され、前記回路は前記シード層に形成され、前記ダイは前記回路に接合され、前記成形材料は前記ダイ及び前記回路を被覆している前記パッケージ構造を提供するステップと、
    第二載置板を前記成形材料に設置するステップと、
    前記第一載置板を除去し、前記シード層を露出するステップと、
    前記シード層を除去し、前記回路を露出するステップと、
    浸漬金メッキ方式で各前記回路にゴールドレイヤーを蓄積するステップと、を含むことを特徴とする半導体装置の製造方法。
  2. 各前記回路はニッケル層及び銅層を含み、前記ニッケル層は純ニッケル電気めっき方式で前記シード層に形成され、前記銅層は前記ニッケル層に形成され、前記シード層を除去した後、前記ニッケル層を露出し、浸漬金メッキ方式で前記ニッケル層に前記ゴールドレイヤーを蓄積することを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 各前記回路は前記シード層に形成されている銅層を含み、前記シード層を除去した後、前記銅層を露出し、浸漬金メッキ方式で前記銅層に前記ゴールドレイヤーを蓄積することを特徴とする請求項１に記載の半導体装置の製造方法。
  4. プラズマエッチング方式で前記シード層を除去することを特徴とする請求項１に記載の半導体装置の製造方法。
  5. 前記回路はパターン化された誘電体層により前記シード層に形成され、プラズマエッチング方式で前記シード層及び部分的な前記パターン化された誘電体層を除去した後、各前記回路の上面及び側面を露出することを特徴とする請求項１に記載の半導体装置の製造方法。
  6. 前記ゴールドレイヤーは各前記回路の前記上面及び前記側面に蓄積していることを特徴とする請求項５に記載の半導体装置の製造方法。
  7. 前記回路はパターン化された誘電体層により前記シード層に形成され、各前記回路はニッケル層及び銅層を含み、前記ニッケル層は純ニッケル電気めっき方式で前記シード層に形成され、前記銅層は前記ニッケル層に形成され、プラズマエッチング方式で前記シード層及び部分的な前記パターン化された誘電体層を除去した後、前記ニッケル層の上面及び側面を露出することを特徴とする請求項１に記載の半導体装置の製造方法。
  8. 前記ゴールドレイヤーは前記ニッケル層の前記上面及び前記側面に蓄積していることを特徴とする請求項７に記載の半導体装置の製造方法。
  9. 前記回路はパターン化された誘電体層により前記シード層に形成され、各前記回路は前記シード層に形成されている銅層を含み、プラズマエッチング方式で前記シード層及び部分的な前記パターン化された誘電体層を除去した後、前記銅層の上面及び側面を露出することを特徴とする請求項１に記載の半導体装置の製造方法。
  10. 前記ゴールドレイヤーは前記銅層の前記上面及び前記側面に蓄積していることを特徴とする請求項９に記載の半導体装置の製造方法。
  11. 前記パターン化された誘電体層のエッチング厚さは１．５μｍ以上ではないことを特徴とする請求項５、７、または９に記載の半導体装置の製造方法。
  12. 前記第一載置板は基板及び剥離層を含み、前記剥離層は前記基板の表面に形成され、前記シード層は前記剥離層に形成され、前記基板及び前記剥離層を除去した後、前記シード層を露出することを特徴とする請求項１に記載の半導体装置の製造方法。
  13. 前記シード層はチタン・タングステン／銅層またはチタン／銅層であることを特徴とする請求項１に記載の半導体装置の製造方法。
  14. 前記銅層は再分布回路構造であることを特徴とする請求項２または３に記載の半導体装置の製造方法。
  15. 前記ゴールドレイヤーが蓄積した後、前記ゴールドレイヤーにはんだボールが形成されることを特徴とする請求項１に記載の半導体装置の製造方法。
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