NL2002693C2 - Solder plating method for copper pads of wafer. - Google Patents

Solder plating method for copper pads of wafer. Download PDF

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Publication number
NL2002693C2
NL2002693C2 NL2002693A NL2002693A NL2002693C2 NL 2002693 C2 NL2002693 C2 NL 2002693C2 NL 2002693 A NL2002693 A NL 2002693A NL 2002693 A NL2002693 A NL 2002693A NL 2002693 C2 NL2002693 C2 NL 2002693C2
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Prior art keywords
solder
copper
wafer
layer
copper contacts
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NL2002693A
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Dutch (nl)
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NL2002693A1 (en
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Wei-Hua Lu
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Univ Nat Pingtung Sci & Tech
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
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    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
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    • H01L2924/014—Solder alloys

Description

-1 -
SOLDER PLATING METHOD FOR COPPER PADS OF WAFER
FIELD OF THE INVENTION 5
[0001] The present invention relates to a solder plating method for copper pads of a wafer, and more particularly to a solder plating method for copper pads of a wafer, wherein a solder layer is tightly formed on each of the copper pads of the wafer and penetrated through a metal film on each of the copper pads, so that the solder layer can be directly used as (or 10 connected to) bumps with a smaller size.
BACKGROUND OF THE INVENTION
[0002] Recently, there is a trend to design and manufacture electronic products with higher 15 performance, higher integrated-circuit density, lower cost and more compact size. To carry out the foregoing purpose, assembly technologies of integrated circuits are developed to improve the miniaturization and the assembly density thereof. Nowadays, general assembly technologies includes dual in-line package (DIP), quad flat package (QFP), quad flat no-lead package (QFN), pin grid array package (PGA), ball grid array package (BGA) and chip scale 20 package (CSP). For example, a package structure of BGA or PGA has a multi-layer substrate which has an upper surface mounted with at least one chip by means of wire-bonding or flip-chip (FC), and a lower surface mounted with a plurality of solder balls. Especially, because the package structure of BGA or PGA can mount two or more than two chips on the same substrate by means of stack-die arrangement or side-by-side arrangement, it is advantageous 25 to construct a system-in-package (SIP) structure with multi-functions. Thus, the package structure of BGA or PGA is rapidly developed and improved in recent years. On the other hand, a package structure of CSP integrates a plurality of chips into a single chip, so as to construct a system-on-chip (SOC) structure with multi-functions. Hence, the package structure of CSP is also rapidly developed and improved in recent years. As described above, 30 advanced assembly technologies of BGA, PGA or CSP use related processes of flip-chip (FC), which are used to form a plurality of bumps on a lower surface of a chip. Therefore, related processes of flip chip (FC) have become one of key factors affecting successes of advanced assembly technologies.
35 [0003] For example, Taiwan Pat. No. 521406, entitled “Process for Forming Bumps” discloses the following steps of: providing a wafer having a plurality of pads; forming an adhesion layer, a barrier layer and a wetting layer on a surface of the wafer in turn; defining the wetting layer and the barrier layer to form a plurality of under bump metallization (UBM) -2- patterns and expose the adhesion layer; forming a plurality of solder layer patterns on a surface of the UBM patterns; removing the exposed adhesion layer; and reflowing the solder layer patterns to form a plurality of bumps. The material of the adhesion layer is selected from Cr, Cu, Al or Ti; the material of the barrier layer is selected from Ti-W alloy, Ti, Ni-V alloy or 5 Cr-Cu alloy; and the material of the wetting layer is selected from Cu, Ni, Pd, Au, Ag or Pt. After finishing the process, the pads (Al pads) of the wafer is formed with a lamination of the adhesion layer, the barrier layer, the wetting layer and the solder bumps in turn.
[0004] In addition, Taiwan Pat. No. 1257136, entitled “Method for Manufacturing Bumps of 10 Wafer Level Package” discloses the following steps of: providing a wafer having a surface formed with a plurality of cutting lines, a protective layer and a plurality of pads; forming a electro-conductive layer on the wafer, wherein the electro-conductive layer is electrically connected to the pads and filled into the cutting lines; forming a photo-resist layer on the electro-conductive layer; patterning the photo-resist layer to form a plurality of first openings 15 on the pads to expose the electro-conductive layer and a plurality of second openings on a region excluding the pads to un-expose the electro-conductive layer; and forming a plurality of bumps in the first openings to electrically connect to the electro-conductive layer on the pads. The material of the electro-conductive layer is selected from one layer structure (such as Ti, Ti-W alloy, Al, Ni-V alloy, Ni, Cu or Cr), three layer structure (such as Ti/Ni-V alloy/Cu or 20 Al/Ni-V alloy/Cu), two layer structure (such as Ti/Cu) or four layer structure (such as Al/Ti/Ni-V alloy/Cu). After finishing the method, the pads (Al pads) of the wafer is formed with the electro-conductive layer (one-four layer structure) and the solder bumps in turn.
[0005] Moreover, Taiwan Pat. No. I283433, entitled “Method for Lowering Surfaces 25 Roughness of Metal Bumps on Wafer” discloses the following steps of: providing a wafer having an active surface; forming a metal layer on the active surface of the wafer; forming a photo-resist layer on the metal layer, wherein the photo-resist layer has a plurality of opening to expose the metal layer; forming a plurality of metal bumps in the opening of the photoresist layer, wherein each of the metal bumps has a connection surface exposed out of the 30 photo-resist layer; grinding the connection surfaces of the metal bumps to lower the surface roughness thereof; removing the photo-resist layer after grinding; and etching the metal bumps to eliminate the ground traces on the connection surface of the metal bumps after removing the photo-resist layer. The metal layer is selected from a composite metal lamination having one or more than one metal or alloy, i.e. a UBM structure. After finishing 35 the process, the pads (Al pads) of the wafer is formed with the electro-conductive layer (one-four layer structure) and the solder bumps in turn.
[0006] Besides, prior arts related to flip chip (FC) and under bump metallization (UBM) -3- further includes Taiwan Pat. No. 556293, entitled “Process of Bumping”; Taiwan Pat. No. 1221334, entitled “Bumping Process”; Taiwan Pat. No. I225698, entitled “Bumping Process for Wafer Level Package” and Taiwan Pat. No. I239578, entitled “Process of Bumps”. After finishing the process, the pads (Al pads) of the wafer is also formed with a lamination of the 5 UBM structure (composite layer) and the solder bumps in turn.
[0007] On the other hand, in comparison with the development of package technologies, technologies of semiconductor wafer processes are also developed to improve the miniaturization thereof. Especially, when 0.13 urn wafer technology is replaced by 90 nm 10 wafer technology, Al process is gradually replaced by Cu process, wherein Al pads formed on the wafer are replaced by Cu pads thereon. However, there is a technological problem of the advanced Cu process, i.e. various traditional UBM structures originally applied to Al pads on the wafer can not be applied to next-generation Cu pads on the wafer due to metallurgical compatibility. Furthermore, because the traditional UBM structures generally need a plurality 15 of metal layers, related processes thereof are too complicated, while the manufacture cost thereof is relatively high. In addition, it is necessary to think how to develop an advanced technology to reduce the size of bumps on Cu pads of the wafer for the purpose of relatively reducing the pitch between the bumps and increasing the allocated number of the bumps per unit area of a flip chip.
20
[0008] As a result, it is necessary to develop a solder plating method for copper pads of a wafer to solve the problems existing in the traditional technologies, as described above.
25 SUMMARY OF THE INVENTION
[0009] A primary object of the present invention is to provide a solder plating method for copper pads of a wafer, which temporarily forms an overall semi-penetrable metal film on a wafer, and then forms a solder layer which penetrates through the metal film above Cu pads 30 of the wafer by immersion plating, so that the bumping process and the bump structure can be simplified, while the manufacture cost thereof can be lowered.
[0010] A secondary object of the present invention is to provide a solder plating method for copper pads of a wafer, which replaces a surface portion of Cu pads exposed out of the metal 35 film with a solder layer by immersion plating, so that the solder layer is tightly formed on the Cu pads and the connection strength of the bumps can be enhanced.
[0011] A third object of the present invention is to provide a solder plating method for copper - 4 - pads of a wafer, wherein a solder layer penetrates through the metal film and is tightly formed on the Cu pads of the wafer, so that the solder layer can be directly used as a small bump to shorten the pitch between adjacent bumps, increase the allocated number of the bumps per unit area and conform to lead-free standards of environmental protection rules.
5
[0012] A fourth object of the present invention is to provide a solder plating method for copper pads of a wafer, wherein a solder layer penetrates through the metal film and is tightly formed on the Cu pads of the wafer, so that the solder layer can further connect to a lead-free bump to provide a lead-free flip-chip (FC) technology and conform to lead-free standards of 10 environmental protection rules.
[0013] To achieve the above object, the solder plating method for copper pads of a wafer according to a preferred embodiment of the present invention comprises steps of: providing a wafer having copper (Cu) pads on a surface thereof; forming a metal film on the surface of 15 the wafer to electrically connect all of the copper pads and to expose partial surfaces of each of the copper pads; processing the partial surfaces of the copper pads exposed out of the metal film by immersion plating, so as to replace the partial surfaces of the copper pads by a solder layer, until the solder layer is deposited over the metal film; forming a photo-resist layer on the solder layer, and patterning the photo-resist layer to form openings for exposing the 20 metal film on a region of the wafer excluding the copper pads; removing the remaining metal film in the openings uncovered by the photo-resist layer; and removing the photo-resist layer.
[0014] Then, after cutting the wafer into a plurality of chips, the solder layers on the copper pads of the chip can be directly used as small bumps for connecting the chip to a substrate, 25 so as to construct a BGA (ball grid array) or PGA (pin grid array) package structure. Alternatively, after cutting the wafer into a plurality of chips, the solder layers on the copper pads of the chip can be directly used as small bumps, while the chip can be directly used as a chip-scale package (CSP) structure.
30 [0015] Furthermore, according to a solder plating method for copper pads of a wafer of another embodiment of the present invention, after the step of removing the photo-resist layer, the method further comprises steps of: forming a secondary photo-resist layer on the wafer, and patterning the secondary photo-resist layer to form a plurality of openings to expose the solder layers on the copper pads; forming a solder material in each of the 35 openings; removing the secondary photo-resist layer; and reflowing the solder material to form a plurality of metal bumps.
-5-
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed 5 description of the preferred embodiments and the accompanying drawings, wherein
[0017] Fig. 1 is a schematic view of a first step of a solder plating method for copper pads of a wafer according to a first embodiment of the present invention; 10 [0018] Fig. 2 is a schematic view of a second step of the solder plating method for copper pads of a wafer according to the first embodiment of the present invention;
[0019] Fig. 3 and 3A are a schematic view and a partially enlarged view of a third step of the solder plating method for copper pads of a wafer according to the first embodiment of the 15 present invention;
[0020] Fig. 4 and 5 are schematic views of a fourth step of the solder plating method for copper pads of a wafer according to the first embodiment of the present invention; 20 [0021] Fig. 6 is a schematic view of a fifth step of the solder plating method for copper pads of a wafer according to the first embodiment of the present invention;
[0022] Fig. 7 is a schematic view of a sixth step of the solder plating method for copper pads of a wafer according to the first embodiment of the present invention; and 25
[0023] Fig. 8, 9, 10, 11 and 12 are schematic views of a seventh step to a tenth step of a solder plating method for copper pads of a wafer according to a second embodiment of the present invention.
30 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] Referring now to Figs. 1 to 7, a solder plating method for copper pads of a wafer according to a preferred embodiment of the present invention is illustrated. As shown, the solder plating method comprises steps of: providing a wafer 1 having copper (Cu) pads 11 on 35 a surface thereof; forming a metal film 2 on the surface of the wafer 1 to electrically connect all of the copper pads 11 and to expose partial surfaces of each of the copper pads 11; forming a solder layer 3 which penetrates through the metal film 2 and deposits over the metal film 2; forming a photo-resist layer 4 on the solder layer 3, and patterning the photo- -6- resist layer 4 to form openings 41 for exposing the metal film 2 on a region of the wafer 1 excluding the copper pads 11; removing the remaining metal film 2 in the openings 41 uncovered by the photo-resist layer 4; and removing the photo-resist layer 4. The solder plating method for copper pads of a wafer of the present invention can be carried out 5 according to one of a first embodiment and a second embodiment, both of which will be described more detailed hereinafter, respectively.
[0025] Referring now to Figs. 1 to 7, a solder plating method for copper pads of a wafer according to a first embodiment of the present invention is illustrated. As shown, the solder 10 plating method comprises steps of: providing a wafer 1 having copper (Cu) pads 11 on a surface thereof; forming a metal film 2 on the surface of the wafer 1 to electrically connect all of the copper pads 11 and to expose partial surfaces of each of the copper pads 11; processing the partial surfaces of the copper pads 11 exposed out of the metal film 2 by immersion plating, so as to replace the partial surfaces of the copper pads 11 by a solder 15 layer 3, until the solder layer 3 is deposited over the metal film 2; forming a photo-resist layer 4 on the solder layer 3, and patterning the photo-resist layer 4 to form openings 41 for exposing the metal film 2 on a region of the wafer 1 excluding the copper pads 11; removing the remaining metal film 2 in the openings 41 uncovered by the photo-resist layer 4; and removing the photo-resist layer 4.
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[0026] Referring back to Fig. 1, in the first embodiment of the present invention, the first step of the solder plating method for copper pads of a wafer is to provide a wafer 1 having copper (Cu) pads 11 on a surface thereof. In the step, the wafer 1 is preferably selected from silicon wafer which is processed by Cu processes of 0.18 urn or less than 0.18 urn, so that a 25 surface of the wafer 1 can be formed with the copper pads 11 and copper circuits (not-shown). Then, the surface of the wafer 1 is further formed with a protective layer 12 which is patterned to define a plurality of openings (unlabeled), so as to expose the copper pads 11 and cover the copper circuits. The protective layer 12 is generally selected from insulated material, such as silicon dioxide or silicon nitride.
30
[0027] Referring now to Fig. 2, in the first embodiment of the present invention, the second step of the solder plating method for copper pads of a wafer is to form a metal film 2 on the surface of the wafer 1 to electrically connect all of the copper pads 11 and to expose partial surfaces of each of the copper pads 11. In the step, the present invention preferably 35 processes the surface of the wafer 1 by sputtering deposition, evaporation deposition or electroless plating under vacuum, in order to form the metal film 2. The thickness of the metal film 2 is preferably controlled between 1 nm to 1 urn, especially between 5 nm to 800 nm, more particularly between 10 nm to 600nm. The thickness of the metal film 2 must be suitably -7- controlled to be a very thin condition, so that the metal film 2 can provide the semipenetrability to expose partial surfaces of each of the copper pads 11. Thus, in the following step, it is advantageous to replace the partial surfaces of the copper pads 11 below the metal film 2 with a solder layer 3 by immersion plating. In addition, the material of the metal film 2 is 5 preferably selected from a metal which can not be replaced by tin (Sn), such as silver (Ag) or gold (Au). The metal film 2 is temporarily used to electrically connect all of the copper pads 11 to each other. In this case, the metal film 2 can solve the problem that inner copper circuits (not-shown) of the wafer 1 may cause different potential on each of the copper pads 11 during the following step of immersion plating, so as to ensure to form solder layers 3 with an 10 uniform thickness on all of the copper pads 11.
[0028] Referring now to Figs. 3 and 3A, in the first embodiment of the present invention, the third step of the solder plating method for copper pads of a wafer is to process the partial surfaces of the copper pads 11 exposed out of the metal film 2 by immersion plating, so as to 15 replace the partial surfaces of the copper pads 11 by a solder layer 3, until the solder layer 3 is deposited over the metal film 2. In the step, the immersion plating method is preferably selected from a plating method having a replacement function, especially the immersion tin process. An electrolyte used by the immersion plating method is preferably selected from a tin-based electrolyte, such as an electrolyte including tin chloride (SnCI2) solution with a 20 complex agent, wherein the complex agent can be preferably selected from thiourea. Because the partial surfaces of the copper pads 11 exposed out of the metal film 2 are gradually replaced by tin ion in (Sn2+) the electrolyte, the solder layer 3 is gradually deposited and formed. Finally, the partial surfaces of the copper pads 11 exposed out of the metal film 2 are replaced by tin (Sn) and filled with tin. As shown in Fig. 3A, it should be noted that the 25 metal film 2 is not replaced by tin, while copper of each of the partial surfaces of the copper pads 11 exposed out of the metal film 2 is replaced by tin, so that the copper pads 11 form a rough concave portion 111 which is tightly connected to the solder layer 3. In this case, if the reaction time of immersion plating is elongated, tin ion may further replace copper of other portions adjacent to the partial surfaces of the copper pads 11 exposed out of the metal film 30 2, wherein copper of the adjacent portions are originally covered by the metal film 2. Thus, a replacement range of the solder layer 3 and the concave degree of the rough concave portion 111 may be further expanded. Furthermore, the solder layer 3 is continuously deposited until the solder layer 3 is deposited over the metal film 2. The height (thickness) of the solder layer 3 is preferably controlled between 100 nm to 100 urn, especially between 0.1 urn to 75 urn, 35 more particularly between 1 urn to 50 urn. Moreover, the material of the solder layer 3 is preferably selected from tin (Sn) or other equivalent lead-free solder material, such as Sn-Ag alloy, Sn-Ag-Cu alloy and etc. It should be noted that it is advantageous to inhibit to form intermetallic compounds (IMC) between copper and tin if the metal film 2 is selected from -8- silver (Ag).
[0029] Referring now to Figs. 4 and 5, in the first embodiment of the present invention, the fourth step of the solder plating method for copper pads of a wafer is to form a photo-resist 5 layer 4 on the solder layer 3, and pattern the photo-resist layer 4 to form openings 41 for exposing the metal film 2 on a region of the wafer 1 excluding the copper pads 11. In the step, the present invention preferably forms the photo-resist layer 4 by coating a liquid photo resist material or adhering with a dry film. The photo-resist layer 4 can be selected from negative photo resist or positive photo resist. Then, the photo-resist layer 4 is patterned by 10 known processes of exposure and development, so as to form the openings 41 which are corresponding to a region of the wafer 1 excluding the copper pads 11. Thus, in the following step, the metal film 2 on the region can be exposed and removed.
[0030] Referring now to Fig. 6, in the first embodiment of the present invention, the fifth step 15 of the solder plating method for copper pads of a wafer is to remove the remaining metal film 2 in the openings 41 uncovered by the photo-resist layer 4. In the step, the present invention preferably uses at least one suitable etchant to selectively etch silver, gold or other equivalent metal of the metal film 2, which can not be replaced by tin, so as to remove the remaining metal film 2 in the openings 41 and expose the protective layer 12 on the surface of the wafer 20 1. After etching, only the solder layer 3 and the metal film 2 on the copper pads 11, which are covered by the photo-resist layer 4, are remained.
[0031] Referring now to Fig. 7, in the first embodiment of the present invention, the sixth step of the solder plating method for copper pads of a wafer is to remove the photo-resist 25 layer 4. In the step, the photo-resist layer 4 can be removed by known processes of development. When the photo-resist layer 4 is selected from a dry film, it can be directly peeled off. After removing the photo-resist layer 4, the solder layer 3 on the copper pads 11 will be exposed.
30 [0032] According to the first to sixth steps, the first embodiment of the present invention can form the solder layer 3 which penetrates through the metal film 2 and is tightly formed on the copper pads 11 of the wafer 1, so that the solder layer 3 can be directly used as a small bump. After finishing the solder plating method for copper pads of a wafer in the first embodiment of the present invention, the wafer 1 can be cut into a plurality of chips (not-35 shown), the solder layers 3 on the copper pads 11 of the chip can be directly used as small bumps for connecting the chip to a substrate (not-shown), so as to construct a BGA (ball grid array) or PGA (pin grid array) package structure. Alternatively, after cutting the wafer 1 into a plurality of chips (not-shown), the solder layers 3 on the copper pads 11 of the chip can be -9- directly used as small bumps, while the chip can be directly used as a chip-scale package (CSP) structure. Because the small bumps defined by the solder layer 3 have a relatively small size, it is advantageous to shorten the pitch between adjacent copper pads 11 and the pitch between adjacent bumps, and increase the allocated number of the bumps per unit 5 area, while the small bumps can conform to lead-free standards of international environmental-protection rules (such as RoHS and WEEE).
[0033] Referring now to Figs. 1-7 and 8-12, a solder plating method for copper pads of a wafer according to a second embodiment of the present invention is illustrated and similar to 10 the first embodiment. As shown, the solder plating method of the second embodiment comprises steps of: providing a wafer 1 having copper (Cu) pads 11 on a surface thereof; forming a metal film 2 on the surface of the wafer 1 to electrically connect all of the copper pads 11 and to expose partial surfaces of each of the copper pads 11; processing the partial surfaces of the copper pads 11 exposed out of the metal film 2 by immersion plating, so as to 15 replace the partial surfaces of the copper pads 11 by a solder layer 3, until the solder layer 3 is deposited over the metal film 2; forming a photo-resist layer 4 on the solder layer 3, and patterning the photo-resist layer 4 to form openings 41 for exposing the metal film 2 on a region of the wafer 1 excluding the copper pads 11; removing the remaining metal film 2 in the openings 41 uncovered by the photo-resist layer 4; removing the photo-resist layer 4; 20 forming a secondary photo-resist layer 5 on the wafer 1, and patterning the secondary photoresist layer 5 to form a plurality of openings 51 to expose the solder layers 3 on the copper pads 11; forming a solder material 6 in each of the openings 51; removing the secondary photo-resist layer 5; and reflowing the solder material 6 to form a plurality of metal bumps 6’.
25 [0034] In comparison with the first embodiment, the second embodiment further comprises a seventh step to a tenth step after finishing the first to sixth steps of the first embodiment, so as to form the secondary photo-resist layer 5 which has a thickness greater than that of the photo-resist layer 4. The secondary photo-resist layer 5 is defined with a plurality of openings 51 for forming the solder material 6 on the solder layer 3. The present invention preferably 30 forms the secondary photo-resist layer 5 by coating a liquid photo resist material or adhering with a dry film. Furthermore, the solder material 6 can be formed on the solder layer 3 in the openings 51 by means of printing, electroless plating or evaporation deposition, wherein the solder material 6 is preferably selected from tin (Sn) or other equivalent lead-free solder material, such as Sn-Ag alloy, Sn-Ag-Cu alloy and etc. The material of the solder material 6 35 can be equal to or different from that of the solder layer 3, while the melting point of the solder material 6 can be equal to or different from that of the solder layer 3. However, based on actual needs, the solder material 6 still can be selected from lead-containing solder material, such as Sn-Pb alloy and etc. After reflowing, the solder material 6 is converted to form the -10- metal bumps 6’ which has a height (thickness) preferably controlled between 5 urn to 300 urn, especially between 10 urn to 250 urn, more particularly between 20 urn to 200 urn.
[0035] According to the first to tenth steps, the second embodiment of the present invention 5 can form the solder layer 3 which penetrates through the metal film 2 and is tightly formed on the copper pads 11 of the wafer 1, while the solder layer 3 can be used to further form the metal bumps 6’. After finishing the solder plating method for copper pads of a wafer in the second embodiment of the present invention, the wafer 1 can be cut into a plurality of chips (not-shown), the metal bumps 6’ on the copper pads 11 of the chip can be used for 10 connecting the chip to a substrate (not-shown), so as to construct a BGA (ball grid array) or PGA (pin grid array) package structure. Alternatively, after cutting the wafer 1 into a plurality of chips (not-shown), the chip can be directly used as a chip-scale package (CSP) structure with the metal bumps 6’. Because the combination of the solder layer 3 and the metal bumps 6’ still has a relatively small size, it is also advantageous to shorten the pitch between 15 adjacent copper pads 11 and the pitch between adjacent bumps, and increase the allocated number of the bumps per unit area, while the metal bumps 6’ can conform to lead-free standards of international environmental-protection rules (such as RoHS and WEEE).
[0036] As described above, the traditional UBM structures can not be applied to next- 20 generation Cu pads on the wafer due to its metallurgical compatibility, while the bumps formed on the UBM structures have a size which can not be further reduced. In comparison, the solder plating method for copper pads of a wafer according to the first and second embodiments of the present invention as shown in Figs. 7 and 12 can temporarily form the overall semi-penetrable metal film 2 on the wafer 1, and then process the partial surfaces of 25 the copper pads 11 exposed out of the metal film 2 by immersion plating, so as to replace the partial surfaces of the copper pads 11 by a solder layer 3 which penetrates through the metal film 2 and is tightly formed on the Cu pads 11 of the wafer 1, so that the bumping process can be simplified, while the manufacture cost thereof can be lowered. Furthermore, it is also advantageous to shorten the pitch between adjacent bumps, increase the allocated number 30 of the bumps per unit area, and conform to lead-free standards of environmental-protection rules.
[0037] The present invention has been described with a preferred embodiment thereof and it is understood that many changes and modifications to the described embodiment can be 35 carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.

Claims (23)

1. Soldeerwerkwijze voor kopercontacten van een wafer, omvattende: het verschaffen van een wafer, die op zijn oppervlak kopercontacten heeft; het vormen van een metaalfolie op het oppervlak van de wafer om alle kopercontacten elektrisch te verbinden en om deeloppervlakken van elk van de 5 kopercontacten bloot te stellen aan de metaalfolie; het bewerken van de deeloppervlakken van de aan de metaalfolie blootgestelde deeloppervlakken van de kopercontacten door middel van dompelplateren, om de deeloppervlakken van de kopercontacten te voorzien van een soldeerlaag, totdat de soldeerlaag op het metaalfolie is neergeslagen; 10 het vormen van een fotolaklaag op de soldeerlaag en het patroneren van de fotolaklaag om openingen te vormen voor het blootleggen van het metaalfolie in een gebied van de wafer, exclusief de kopercontacten; het verwijderen van het resterende metaalfolie in de door de fotolaklaag onbedekt gelaten openingen; en 15 het verwijderen van de fotolaklaag.A soldering method for copper contacts of a wafer, comprising: providing a wafer that has copper contacts on its surface; forming a metal foil on the surface of the wafer to electrically connect all copper contacts and to expose partial surfaces of each of the copper contacts to the metal foil; machining the sub-surfaces of the sub-surfaces of the copper contacts exposed to the metal foil by means of dip plating to provide the sub-surfaces of the copper contacts with a solder layer until the solder layer has deposited on the metal foil; Forming a photoresist layer on the solder layer and patterning the photoresist layer to form apertures for exposing the metal foil in an area of the wafer excluding the copper contacts; removing the remaining metal foil in the openings left uncovered by the photoresist layer; and removing the photoresist layer. 2. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij de stap van het verschaffen van de wafer verder omvat: het vormen van een beschermingslaag op het oppervlak van de wafer en het patroneren van de beschermingslaag om een aantal openingen voor het blootleggen van de kopercontacten te 20 definiëren.The copper contact soldering method of the wafer according to claim 1, wherein the step of providing the wafer further comprises: forming a protective layer on the surface of the wafer and patterning the protective layer around a plurality of openings for exposing the wafer. define copper contacts. 3. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij de stap van het vormen van het metaalfolie verder omvat: het bewerken van de wafer door middel van sputterdepositie, verdampingsdepostie of electrodeloos plateren om het metaalfolie te vormen.The copper contact soldering method of the wafer according to claim 1, wherein the step of forming the metal foil further comprises: processing the wafer by sputter deposition, evaporation deposition or electrodeless plating to form the metal foil. 4. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij de dikte van het metaalfolie tussen 1 nm tot en met 1 pm ligt.The soldering method for copper contacts of the wafer according to claim 1, wherein the thickness of the metal foil is between 1 nm and 1 µm. 5. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij het materiaal van het metaalfolie een metaal is, dat niet door tin kan worden vervangen.The copper contact soldering method of the wafer according to claim 1, wherein the metal foil material is a metal that cannot be replaced with tin. 6. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 5, waarbij 30 het materiaal van het metaalfolie zilver of goud is.The solder method for copper contacts of the wafer according to claim 5, wherein the material of the metal foil is silver or gold. 7. Soldeerwerkwijze voor kopercontacten van een substraat volgens conclusie 1, waarbij het dompelplateren een dompeltinproces is.The solder method for copper contacts of a substrate according to claim 1, wherein the dip plating is a dip tin plating process. 8. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 7, waarbij een door het dompeltinproces gebruikt elektrolyt tinchloride omvat.The copper contact solder method of the wafer according to claim 7, wherein an electrolyte used by the dip-in process comprises tin chloride. 9. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 8, waarbij het door het dompeltinproces gebruikte elektrolyt verder een complexmiddel omvat.The solder method for copper contacts of the wafer according to claim 8, wherein the electrolyte used by the dip-in process further comprises a complexing agent. 10. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 9, waarbij het complexmiddel thiourea is.The copper contact soldering method of the wafer according to claim 9, wherein the complexing agent is thiourea. 11. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij in de stap van het dompelplateren koper van elk van de deeloppervlakken van de kopercontacten door tin wordt vervangen, zodat de kopercontacten een ruw concaaf gedeelte vormen, dat stevig met de soldeerlaag wordt verbonden.The copper contact soldering method of the wafer according to claim 1, wherein in the dipping plating step, copper of each of the partial surfaces of the copper contacts is replaced with tin, so that the copper contacts form a rough concave portion that is firmly connected to the solder layer. 12. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 11, 10 waarbij een reactietijd van het dompelplateren verder wordt verlengd, zodat tinionen koper van andere gedeelten, die grenzen aan de deeloppervlakken van de kopercontacten, die door het metaalfolie zijn blootgelegd, verder vervangen, waarbij koper van de aangrenzende gedeelten oorspronkelijk door het metaalfolie zijn bedekt, en een vervangingsbereik van de soldeerlaag en de mate van concaafheid van het ruwe concave gedeelte verder worden 15 uitgebreid.The copper contact soldering method of the wafer according to claim 11, wherein an immersion plating reaction time is further extended, so that tin ions further replace copper from other portions adjacent to the partial surfaces of the copper contacts exposed by the metal foil, wherein copper from the adjacent portions were originally covered by the metal foil, and a replacement range of the solder layer and the degree of concavity of the raw concave portion are further extended. 13. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij de hoogte van de soldeerlaag tussen 100 nm en 100 pm ligt.The solder method for copper contacts of the wafer according to claim 1, wherein the height of the solder layer is between 100 nm and 100 µm. 14. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 1, waarbij het materiaal van de soldeerlaag loodvrij soldeermateriaal is.The solder method for copper contacts of the wafer according to claim 1, wherein the material of the solder layer is lead-free solder material. 15. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 14, waarbij het loodvrije soldeermateriaal wordt gekozen uit Sn, Sn-Ag legering en Sn-Ag-Cu legering.The solder method for copper contacts of the wafer according to claim 14, wherein the lead-free solder material is selected from Sn, Sn-Ag alloy and Sn-Ag-Cu alloy. 16. Soldeerwerkwijze voor kopercontacten van een substraat volgens conclusie 1, waarbij in de stap van het vormen van de fotolaklaag de fotolaklaag wordt gevormd door 25 middel van het aanbrengen van een vloeibaar fotolaklaagmateriaal of door middel van vasthechten met een droogfolie.16. Copper contact soldering method of a substrate according to claim 1, wherein in the step of forming the photoresist layer, the photoresist layer is formed by applying a liquid photoresist layer material or by means of adhesion with a drying film. 17. Soldeerwerkwijze voor kopercontacten van een substraat volgens conclusie 1, verder omvattende na de stap van het verwijderen van de fotolaklaag: het vormen van een secundaire fotolaklaag op de wafer, en het in patroon vormen 30 van de secundaire fotolaklaag om een aantal openingen te vormen teneinde de soldeerlagen op de kopercontacten bloot te leggen; het vormen van een soldeermateriaal in elk van de openingen; het verwijderen van de secundaire fotolaklaag; en het doen vloeien van het soldeermateriaal om een aantal metalen 35 contacteerbobbels te vormen.17. The copper contact soldering method of a substrate according to claim 1, further comprising after the step of removing the photoresist layer: forming a secondary photoresist layer on the wafer, and patterning the secondary photoresist layer to form a plurality of apertures to expose the solder layers on the copper contacts; forming a solder material in each of the openings; removing the secondary photoresist layer; and flowing the solder material to form a plurality of metal contact bumps. 18. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 17, waarbij in de stap van het vormen van het soldeermateriaal het soldeermateriaal wordt gevormd op de soldeerlaag in de openingen door middel van printen, electrodeloos plateren of verdampingsdepositie.The solder method for copper contacts of the wafer according to claim 17, wherein in the step of forming the solder material the solder material is formed on the solder layer in the openings by means of printing, electrodeless plating or evaporation deposition. 19. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 17, waarbij het soldeermateriaal loodvrij soldeermateriaal is.The solder method for copper contacts of the wafer according to claim 17, wherein the solder material is lead-free solder material. 20. Soldeerwerkwijze voor kopercontacten van een de wafer volgens conclusie 19, waarbij het loodvrije soldeermateriaal wordt gekozen uit Sn, Sn-Ag legering en Sn-Ag-Cu legering.The solder method for copper contacts of a wafer according to claim 19, wherein the lead-free solder material is selected from Sn, Sn-Ag alloy and Sn-Ag-Cu alloy. 21. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 17, waarbij het materiaal en het smeltpunt van het soldeermateriaal gelijk zijn aan het materiaal 10 en het smeltpunt van de soldeerlaag.The solder method for copper contacts of the wafer according to claim 17, wherein the material and the melting point of the solder material are the same as the material 10 and the melting point of the solder layer. 22. Soldeerwerkwijze voor kopercontacten van het substraat volgens conclusie 17, waarbij het materiaal en het smeltpunt van het soldeermateriaal verschillen van het materiaal en het smeltpunt van de soldeerlaag.The solder method for copper contacts of the substrate according to claim 17, wherein the material and the melting point of the solder material differ from the material and the melting point of the solder layer. 23. Soldeerwerkwijze voor kopercontacten van de wafer volgens conclusie 17, 15 waarbij de hoogte van de metalen contacteerbobbels tussen 5 pm en 300 pm ligt.The soldering method for copper contacts of the wafer according to claim 17, wherein the height of the metal contact bumps is between 5 µm and 300 µm.
NL2002693A 2008-04-03 2009-03-31 Solder plating method for copper pads of wafer. NL2002693C2 (en)

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US6551931B1 (en) * 2000-11-07 2003-04-22 International Business Machines Corporation Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped
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US20050001324A1 (en) * 2003-07-01 2005-01-06 Motorola, Inc. Corrosion-resistant copper bond pad and integrated device

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