TW200943444A - Tin processing method for copper pads of wafer - Google Patents
Tin processing method for copper pads of waferInfo
- Publication number
- TW200943444A TW200943444A TW097112408A TW97112408A TW200943444A TW 200943444 A TW200943444 A TW 200943444A TW 097112408 A TW097112408 A TW 097112408A TW 97112408 A TW97112408 A TW 97112408A TW 200943444 A TW200943444 A TW 200943444A
- Authority
- TW
- Taiwan
- Prior art keywords
- copper pads
- wafer
- metal film
- photo
- tin
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
A tin processing method for copper pads of a wafer includes steps of: providing a wafer having copper pads on a surface thereof; forming a metal film on the surface of the wafer to electrically connect all of the copper pads and to expose partial surfaces of each of the copper pads; processing the partial surfaces of the copper pads exposed out of the metal film by immersion plating, so as to replace the partial surfaces of the copper pads by a tin layer, until the tin layer is deposited over the metal film; forming a photo-resist layer on the tin layer, and patterning the photo-resist layer to form openings for exposing the metal film on a region of the wafer excluding the copper pads; removing the remaining metal film uncovered by the photo-resist layer; and removing the photo-resist layer.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097112408A TWI353645B (en) | 2008-04-03 | 2008-04-03 | Tin processing method for copper pads of wafer |
NL2002693A NL2002693C2 (en) | 2008-04-03 | 2009-03-31 | Solder plating method for copper pads of wafer. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097112408A TWI353645B (en) | 2008-04-03 | 2008-04-03 | Tin processing method for copper pads of wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200943444A true TW200943444A (en) | 2009-10-16 |
TWI353645B TWI353645B (en) | 2011-12-01 |
Family
ID=41397322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097112408A TWI353645B (en) | 2008-04-03 | 2008-04-03 | Tin processing method for copper pads of wafer |
Country Status (2)
Country | Link |
---|---|
NL (1) | NL2002693C2 (en) |
TW (1) | TWI353645B (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6551931B1 (en) * | 2000-11-07 | 2003-04-22 | International Business Machines Corporation | Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped |
JP3679001B2 (en) * | 2000-12-22 | 2005-08-03 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US7078796B2 (en) * | 2003-07-01 | 2006-07-18 | Freescale Semiconductor, Inc. | Corrosion-resistant copper bond pad and integrated device |
-
2008
- 2008-04-03 TW TW097112408A patent/TWI353645B/en active
-
2009
- 2009-03-31 NL NL2002693A patent/NL2002693C2/en active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
TWI353645B (en) | 2011-12-01 |
NL2002693C2 (en) | 2010-11-02 |
NL2002693A1 (en) | 2009-10-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200737375A (en) | Method for forming metal bumps | |
TW200737454A (en) | Method for forming metal bumps | |
JP2008263125A5 (en) | ||
MY158939A (en) | Method to form solder deposits on substrates | |
SG150421A1 (en) | Method of forming thin film metal conductive lines | |
TW200605225A (en) | Methods for fabricating pad redistribution layer and copper pad redistribution layer | |
JP2010518603A5 (en) | ||
MX2013005144A (en) | Method for reducing creep corrosion. | |
TW200629416A (en) | Semiconductor device and fabrication method thereof | |
WO2008101093B1 (en) | Post-seed deposition process | |
WO2012004137A3 (en) | Method to form solder deposits on substrates | |
TW200633609A (en) | Electrical connector structure of circuit board and method for fabricating the same | |
EP2197253A8 (en) | Method for electric circuit deposition | |
TW200637448A (en) | Method for fabricating conducting bump structures of circuit board | |
MY185302A (en) | Method of forming a conductive image on a non-conductive surface | |
JP2012114400A5 (en) | ||
WO2010002736A3 (en) | Methods for fabricating line/space routing between c4 pads | |
CN100539056C (en) | Form the method for metal coupling | |
PH12015501133A1 (en) | Substrate for mounting semiconductor element and method for manufacturing said substrate | |
TW200943443A (en) | Tin processing method for surfaces of copper pads of wafer | |
WO2011010889A3 (en) | Flexible printed circuit board and method for manufacturing the same | |
TW200943444A (en) | Tin processing method for copper pads of wafer | |
JP2005256090A5 (en) | ||
TW200731436A (en) | Manufacturing method of wiring board and manufacturing method of semiconductor device | |
CN100524675C (en) | Method for forming metal projection |