JP2012114400A5 - - Google Patents

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JP2012114400A5
JP2012114400A5 JP2011117724A JP2011117724A JP2012114400A5 JP 2012114400 A5 JP2012114400 A5 JP 2012114400A5 JP 2011117724 A JP2011117724 A JP 2011117724A JP 2011117724 A JP2011117724 A JP 2011117724A JP 2012114400 A5 JP2012114400 A5 JP 2012114400A5
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substrate
hole
manufacturing
wiring board
board according
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JP2011117724A
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JP2012114400A (en
JP5608605B2 (en
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以下開示の一観点によれば、厚み方向に貫通するスルーホールを備えた基板を用意する工程と、前記基板の下面に保護フィルムを配置する工程と、前記スルーホール内に樹脂部を充填する工程と、前記保護フィルムを除去して、前記基板の下面及び前記樹脂部の下面を露出させる工程と、前記基板の下面及び前記樹脂部の下面にシード層を形成する工程と、前記スルーホール内から樹脂部を除去する工程と、前記シード層をめっき給電経路に利用する電解めっきにより、前記スルーホール内に金属めっき層を充填して貫通電極を得る工程とをこの順で有する配線基板の製造方法が提供される。   According to one aspect of the disclosure below, a step of preparing a substrate having a through hole penetrating in the thickness direction, a step of disposing a protective film on the lower surface of the substrate, and a step of filling a resin portion in the through hole Removing the protective film to expose the lower surface of the substrate and the lower surface of the resin portion, forming a seed layer on the lower surface of the substrate and the lower surface of the resin portion, and from within the through hole A method for manufacturing a wiring board, comprising: a step of removing a resin portion; and a step of filling a through-hole with a metal plating layer to obtain a through electrode by electrolytic plating using the seed layer as a plating power feeding path. Is provided.

Claims (12)

厚み方向に貫通するスルーホールを備えた基板を用意する工程と、
前記基板の下面に保護フィルムを配置する工程と、
前記スルーホール内に樹脂部を充填する工程と、
前記保護フィルムを除去して、前記基板の下面及び前記樹脂部の下面を露出させる工程と、
前記基板の下面及び前記樹脂部の下面にシード層を形成する工程と、
前記スルーホール内から樹脂部を除去する工程と、
前記シード層をめっき給電経路に利用する電解めっきにより、前記スルーホール内に金属めっき層を充填して貫通電極を得る工程とをこの順で有することを特徴とする配線基板の製造方法。 Preparing a substrate with a through hole penetrating in the thickness direction;
Placing a protective film on the lower surface of the substrate;
Filling the resin part in the through hole;
Removing the protective film to expose the lower surface of the substrate and the lower surface of the resin portion;
Forming a seed layer on the lower surface of the substrate and the lower surface of the resin portion;
Removing the resin part from the through hole;
A method of manufacturing a wiring board, comprising: in this order, a step of filling the through hole with a metal plating layer to obtain a through electrode by electrolytic plating using the seed layer as a plating power feeding path. 前記基板はシリコンウェハであり、
前記スルーホールを備えた基板を用意する工程は、前記シリコンウェハの両面及び前記スルーホールの内面に絶縁層を形成することを含むことを特徴とする請求項１に記載の配線基板の製造方法。 The substrate is a silicon wafer;
The method of manufacturing a wiring board according to claim 1, wherein the step of preparing the substrate having the through hole includes forming an insulating layer on both surfaces of the silicon wafer and on the inner surface of the through hole. 前記貫通電極を得る工程の後に、
前記シード層を除去する工程をさらに有することを特徴とする請求項１又は２に記載の配線基板の製造方法。 After the step of obtaining the through electrode,
The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the seed layer. 前記樹脂部は、アクリル樹脂、フェノール樹脂、又はレジストからなることを特徴とする請求項１乃至３のいずれか一項に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, wherein the resin portion is made of an acrylic resin, a phenol resin, or a resist. 前記シード層を除去する工程の後に、
前記基板の両面側に前記貫通電極に接続されるｎ層（ｎは１以上の整数）の配線層を形成する工程をさらに有することを特徴とする請求項３に記載の配線基板の製造方法。 After the step of removing the seed layer,
4. The method for manufacturing a wiring board according to claim 3, further comprising a step of forming n layers (n is an integer of 1 or more) of wiring layers connected to the through electrodes on both sides of the substrate. 前記基板はシリコンウェハであり、
前記シード層を形成する工程の後に、
前記スルーホール内の内壁面に前記樹脂部を残すように、前記樹脂部に貫通孔を形成することにより側壁絶縁部を得る工程をさらに有し、
前記貫通電極を得る工程の後に、
前記シード層を除去する工程をさらに有することを特徴とする請求項１に記載の配線基板の製造方法。 The substrate is a silicon wafer;
After the step of forming the seed layer,
A step of obtaining a side wall insulating part by forming a through hole in the resin part so as to leave the resin part on the inner wall surface in the through hole;
After the step of obtaining the through electrode,
The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the seed layer. 前記シード層を除去する工程の後に、
前記シリコンウェハの両面側に前記貫通電極の上に開口部が設けられた絶縁パターン層をそれぞれ形成する工程をさらに有することを特徴とする請求項６に記載の配線基板の製造方法。 After the step of removing the seed layer,
The method of manufacturing a wiring board according to claim 6, further comprising forming an insulating pattern layer having an opening on the through electrode on both sides of the silicon wafer. 前記基板は、ガラス基板又はセラミックス基板であることを特徴とする請求項１に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, wherein the substrate is a glass substrate or a ceramic substrate. 前記基板の下面に保護フィルムを配置する工程において、
前記保護フィルムが前記基板の前記スルーホールに押し込まれて該スルーホールの下部に充填部が部分的に形成され、
前記保護フィルムを除去する工程において、
前記基板の前記スルーホールの下部側面が露出し、
前記シード層を形成する工程において、
前記スルーホールの前記下部側面に前記シード層が形成されることを特徴とする請求項１乃至３のいずれか一項に記載の配線基板の製造方法。 In the step of disposing a protective film on the lower surface of the substrate,
The protective film is pushed into the through hole of the substrate, and a filling portion is partially formed at the bottom of the through hole,
In the step of removing the protective film,
The lower side surface of the through hole of the substrate is exposed,
In the step of forming the seed layer,
4. The method for manufacturing a wiring board according to claim 1, wherein the seed layer is formed on the lower side surface of the through hole. 前記保護フィルムを除去する工程の後に、前記樹脂部の下部を部分的に除去することにより、前記基板の前記スルーホールの下部側面を露出させる工程をさらに有し、
前記シード層を形成する工程において、
前記スルーホールの前記下部側面に前記シード層が形成されることを特徴とする請求項１乃至３のいずれか一項に記載の配線基板の製造方法。 After the step of removing the protective film, further comprising the step of exposing the lower side surface of the through hole of the substrate by partially removing the lower portion of the resin portion,
In the step of forming the seed layer,
4. The method for manufacturing a wiring board according to claim 1, wherein the seed layer is formed on the lower side surface of the through hole. 前記シード層において、前記スルーホールの前記下部側面に接触する層は、スパッタ法、蒸着法、又はＣＶＤ法によって形成される金属層、無電解金属めっき層、又は導電性ペーストから形成されることを特徴とする請求項９又は１０に記載の配線基板の製造方法。   In the seed layer, the layer in contact with the lower side surface of the through hole is formed of a metal layer, an electroless metal plating layer, or a conductive paste formed by a sputtering method, a vapor deposition method, or a CVD method. The method for manufacturing a wiring board according to claim 9 or 10, characterized in that: 前記金属層は、チタン層又はクロム層であることを特徴とする請求項１１に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 11, wherein the metal layer is a titanium layer or a chromium layer.
JP2011117724A 2010-11-05 2011-05-26 Wiring board manufacturing method Expired - Fee Related JP5608605B2 (en)

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JP2011117724A JP5608605B2 (en) 2010-11-05 2011-05-26 Wiring board manufacturing method

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JP2010248328 2010-11-05
JP2010248328 2010-11-05
JP2011117724A JP5608605B2 (en) 2010-11-05 2011-05-26 Wiring board manufacturing method

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JP2012114400A JP2012114400A (en) 2012-06-14
JP2012114400A5 true JP2012114400A5 (en) 2014-04-10
JP5608605B2 JP5608605B2 (en) 2014-10-15

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JP6435860B2 (en) * 2012-11-05 2018-12-19 大日本印刷株式会社 Wiring structure
JP2014236102A (en) * 2013-05-31 2014-12-15 凸版印刷株式会社 Wiring board with through electrode, manufacturing method of the same, and semiconductor device
KR20150049515A (en) * 2013-10-30 2015-05-08 삼성전기주식회사 Printed Circuit Board and The Method of Manufacturing the same
WO2015151512A1 (en) 2014-03-31 2015-10-08 凸版印刷株式会社 Interposer, semiconductor device, interposer manufacturing method, and semiconductor device manufacturing method
JP2015198093A (en) * 2014-03-31 2015-11-09 凸版印刷株式会社 Interposer, semiconductor device, method of manufacturing interposer, and method of manufacturing semiconductor device
JP6539992B2 (en) * 2014-11-14 2019-07-10 凸版印刷株式会社 Printed circuit board, semiconductor device, method of manufacturing wired circuit board, method of manufacturing semiconductor device
CN105657987B (en) * 2014-12-03 2019-05-21 北大方正集团有限公司 Plate method for plugging and circuit board
KR102039887B1 (en) * 2017-12-13 2019-12-05 엘비세미콘 주식회사 Methods of fabricating semiconductor package using both side plating
JP6828733B2 (en) * 2018-12-25 2021-02-10 凸版印刷株式会社 Interposer, semiconductor device, interposer manufacturing method, semiconductor device manufacturing method
KR102442256B1 (en) * 2020-11-05 2022-09-08 성균관대학교산학협력단 Method of manufacturing void-free through silicon via electrode

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JPS63232487A (en) * 1987-03-20 1988-09-28 日本電気株式会社 Manufacture of printed wiring board
JPH0423488A (en) * 1990-05-18 1992-01-27 Hitachi Ltd Manufacture of printed board
JPH06260757A (en) * 1993-03-05 1994-09-16 Meikoo:Kk Manufacture of printed circuit board
JP2006237431A (en) * 2005-02-28 2006-09-07 New Japan Radio Co Ltd Manufacturing method of ceramic substrate
JP2007095743A (en) * 2005-09-27 2007-04-12 Matsushita Electric Works Ltd Through-hole wiring and its manufacturing method

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