JP5608605B2 - Wiring board manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a wiring board on which an electronic component such as a semiconductor chip is mounted.

  Conventionally, there are wiring boards on which electronic components such as semiconductor chips are mounted. In an example of such a wiring substrate, a through electrode is provided on the core substrate, and multilayer wiring layers interconnected via the through electrode are formed on both sides of the core substrate.

  In recent years, with higher performance of electronic components such as semiconductor chips, there has been a demand for higher density of wiring boards, and a technique for forming through electrodes with a narrow pitch on a core board with high reliability is required.

JP 2006-237431-A JP 2007-95743 A

  In a method for manufacturing a wiring board on which an electronic component such as a semiconductor chip is mounted, an object is to reliably form a through electrode on the board.

  According to one aspect of the disclosure below, a step of preparing a substrate having a through hole penetrating in the thickness direction, a step of disposing a protective film on the lower surface of the substrate, and a step of filling a resin portion in the through hole Removing the protective film to expose the lower surface of the substrate and the lower surface of the resin portion, forming a seed layer on the lower surface of the substrate and the lower surface of the resin portion, and from within the through hole A method for manufacturing a wiring board, comprising: a step of removing a resin portion; and a step of filling a through-hole with a metal plating layer to obtain a through electrode by electrolytic plating using the seed layer as a plating power feeding path. Is provided.

  According to the following disclosure, the resin portion is filled in the through hole in a state where the protective film is disposed on the lower surface of the substrate provided with the through hole. Further, after the protective film is removed, a seed layer is formed on the lower surface of the substrate with good adhesion by sputtering or the like. In this way, the seed layer is formed with good adhesion on the lower surface of the substrate provided with the through hole.

  Thereafter, metal plating is applied from the bottom of the through hole by electrolytic plating to obtain a through electrode.

  By adopting such a method, a highly reliable narrow pitch through electrode can be formed in the through hole of the substrate with a high yield without causing a problem.

FIGS. 1A and 1B are sectional views (No. 1) showing a method of manufacturing a wiring board according to related art. FIGS. 2A and 2B are sectional views (No. 2) showing a method for manufacturing a wiring board according to the related art. 3A to 3D are cross-sectional views (No. 1) showing the method for manufacturing the wiring board according to the first embodiment. 4A to 4D are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the first embodiment. 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the first embodiment. 6A to 6C are cross-sectional views (part 4) illustrating the method for manufacturing the wiring board according to the first embodiment. FIG. 7 is a sectional view (No. 5) showing the method for manufacturing the wiring board according to the first embodiment. FIG. 8 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of the first embodiment shown in FIG. FIG. 9 is a cross-sectional view showing a state in which electronic components are mounted on a wiring board according to a modification of the first embodiment. 10A to 10D are cross-sectional views (part 1) showing the method for manufacturing the wiring board according to the second embodiment. 11A to 11C are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the second embodiment. FIG. 12 is a cross-sectional view (part 3) illustrating the method for manufacturing the wiring board according to the second embodiment. 13A to 13D are cross-sectional views (part 1) showing the method for manufacturing the wiring board according to the third embodiment. 14A to 14E are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the third embodiment. 15A to 15E are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the third embodiment. FIG. 16 is a cross-sectional view (part 4) illustrating the method of manufacturing the wiring board according to the third embodiment. FIG. 17 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of the third embodiment of FIG. 16 and a cap is provided.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  Prior to the description of the present embodiment, a basic related technology (preliminary matter) will be described.

  In the related art wiring board manufacturing method, as shown in FIG. 1A, first, the silicon wafer 100 is etched from the upper surface to the middle of the thickness by RIE (Reactive Ion Etching) or the like, thereby forming the non-through holes H. Form.

At this time, an etching method that repeats an etching step using SF ₆ -based gas and a polymer deposition step using C ₄ F ₈ -based gas is used, and fine irregularities are continuously formed on the inner surface of the non-through hole H. It occurs.

  Thereafter, an insulating layer (not shown) made of a silicon oxide layer or the like is formed on the surface of the silicon wafer 100 and the inner surface of the non-through hole H.

  Further, a seed layer 200 made of copper is formed on the upper surface of the silicon wafer 100 and the inner surface of the non-through hole H by sputtering. At this time, as shown in the partially enlarged view of FIG. 1A, since the unevenness is generated on the inner surface of the non-through hole H, the seed layer 200 is formed in the shaded portion of the unevenness particularly in the lower part of the non-through hole H. Since the film is not formed well, the seed layer 200 is often disconnected.

  Next, as shown in FIG. 1B, an electrolytic plating layer 300 made of copper is formed in the non-through hole H and on the upper surface side of the silicon wafer 100 by electrolytic plating using the seed layer 200 as a plating power feeding path.

  At this time, since the seed layer 200 is disconnected under the non-through hole H as described above, the current for electrolytic plating is not supplied and the void B is formed.

  Further, FIG. 2A shows a case where the seed layer 200 is formed by connecting the entire irregularities on the inner surface of the non-through hole H with good step coverage. However, as shown in FIG. 2B, since the upper part of the non-through hole H tends to be plated more than the lower part, the seam S is likely to be generated inside the non-through hole H.

  Although it is possible to suppress the generation of the seam S to some extent depending on the conditions of electrolytic plating, it is difficult to completely suppress the generation of the seam S when the diameter of the non-through hole H is reduced.

  In the related art described above, after the electrolytic plating layer 300 is formed, the lower surface of the electrolytic plating layer 300 in the non-through hole H is polished by polishing the back side of the silicon wafer 100 until it reaches the lower portion of the non-through hole H. Exposed and used as a through electrode.

  The related art method for manufacturing a wiring board has the above-described problems, and it is difficult to form through electrodes having a narrow pitch with a design specification with a high yield.

  In the embodiment described below, the above-described problems can be solved.

(First embodiment)
3 to 7 are cross-sectional views showing a method of manufacturing the wiring board of the first embodiment, and FIG. 8 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the wiring board of the first embodiment.

  In the method for manufacturing a wiring substrate according to the first embodiment, as shown in FIG. 3A, first, a silicon wafer 10 is prepared as a substrate for obtaining a wiring substrate. The thickness of the silicon wafer 10 is 50 to 500 μm, and a silicon wafer having a thickness of 700 to 800 μm is obtained by grinding and thinning with a BG (back grinder).

  Next, as shown in FIG. 3B, a resist 11 provided with an opening 11a for forming a through hole is formed on the silicon wafer 10 by photolithography. The resist 11 may be a dry film resist or a liquid resist.

  Subsequently, as shown in FIG. 3C, through-holes TH that penetrate from the upper surface to the lower surface are formed by penetrating the silicon wafer 10 by dry etching such as RIE through the opening 11a of the resist 11.

At this time, when using the etching method that repeats the etching step using SF ₆ type gas and the polymer deposition step using C ₄ F ₈ type gas described in the related art, the inner surface of the through hole TH is uneven. (Not shown) occurs.

  A large number of electronic component mounting areas are defined in the silicon wafer 10, and a plurality of through holes TH are arranged in each electronic component mounting area. The through hole TH has a horizontal cross section formed in, for example, a circular shape. FIG. 3C schematically shows one electronic component mounting area of the silicon wafer 10.

  Instead of dry etching, the through hole TH may be formed by penetrating the silicon wafer 10 by wet etching. Alternatively, the through hole TH may be formed by penetrating the silicon wafer 10 with a laser or a drill. When using a laser or a drill, the resist 11 may be omitted.

  In addition, after forming a non-through hole to the middle of the thickness of a silicon wafer having a thickness of 700 to 800 μm, the back side of the silicon wafer may be ground until reaching the non-through hole to obtain a through hole. That is, a silicon wafer 10 having a desired thickness provided with a through hole TH penetrating from the upper surface to the lower surface may be prepared.

  Next, as shown in FIG. 3D, after the resist 11 is removed, the silicon wafer 10 is thermally oxidized to form a silicon oxide layer having a thickness of about 1 μm on both sides of the silicon wafer 10 and the inner surface of the through hole TH. An insulating layer 12 is formed. As conditions for thermally oxidizing the silicon wafer 10, for example, annealing is performed at a temperature of 1000 to 1100 ° C. and a processing time of 2 to 6 hours.

  Alternatively, the insulating layer 12 may be formed by forming a silicon oxide layer or a silicon nitride layer on both sides of the silicon wafer 10 and the inner surface of the through hole TH by CVD.

  In addition, when using the silicon wafer 10 having a high resistance (sheet resistance value: 1000 Ω / □), the insulating layer 12 can be omitted if electrical insulation does not become a problem.

  Thereafter, as shown in FIG. 4A, a protective film 20 is disposed on the lower surface of the silicon wafer 10 in FIG. As the protective film 20, a PET (polyethylene terephthalate) film or an acrylic film is used.

  The silicon wafer 10 may be simply stacked and pressed on the protective film 20 disposed on the processing stage. When an acrylic film is used, it may be heated and lightly adhered. Since it is necessary to remove the protective film 20 later, it is stuck in a state where it can be easily peeled off.

  Next, as shown in FIG. 4B, the resin portion 30 is filled into the through hole TH. The resin part 30 is formed by filling the through hole TH with a liquid resin by spin coating, squeegee printing or vacuum printing, and then curing the resin by heating at a temperature of about 100 ° C. Let

  Alternatively, a liquid resin may be applied to the entire upper surface of the silicon wafer 10, and the resin portion 30 may be filled in the through holes TH by pressing the resin in a vacuum state.

  Since the resin part 30 needs to be removed later, an acrylic resin, a phenol resin, or the like that can be easily removed with a peeling solution even after curing is used. A general resist may be used as the resin portion 30.

  There is no particular problem even if a resin is formed on the upper surface of the silicon wafer 10, but when the resin portion 30 is formed only in the through hole TH, a photosensitive resin is used to remove excess resin by exposure / development. It may be.

  Furthermore, the resin part 30 may be filled in the through hole TH of the silicon wafer 10 by placing a resin film such as acrylic resin or phenol resin on the silicon wafer 10 and performing hot pressing.

  Subsequently, as shown in FIG. 4C, the lower surface of the silicon wafer 10 and the resin portion 30 are exposed by peeling off and removing the protective film 20 provided on the lower surface of the silicon wafer 10. At this time, the lower surface of the silicon wafer 10 (insulating layer 12) and the resin portion 30 are the same surface and are exposed in a flat state.

  Next, as shown in FIG. 4D, a seed layer 40 is formed on the lower surfaces of the silicon wafer 10 and the resin portion 30 by sputtering. The seed layer 40 is made of copper or the like, and the thickness thereof is set to about 5 to 15 μm.

  In addition to the sputtering method, the seed layer 40 may be formed by vapor deposition or MO-CVD (Metal Organic-Chemical Vapor Deposition). Alternatively, the seed layer 40 may be formed by applying a conductive paste such as a copper paste or a silver paste.

  Since the resin portion 30 is filled in the through hole TH of the silicon wafer 10, the seed layer 40 is formed on the lower surface of the silicon wafer 10 with good adhesion so as to close the lower portion of the through hole TH.

  As a preferred method for forming the seed layer 40, a first metal layer of a thin film (about 1 μm) is first formed with good adhesion by sputtering or the like, and reinforced by electrolytic plating or electroless plating thereon. There is a method of laminating a second metal layer having a thick film (about 5 to 10 μm) as a layer. In this case, the tact time of the wafer processing is shortened and the production efficiency can be improved as compared with the case where the seed layer 40 is formed only by the sputtering method.

  Next, as shown in FIG. 5A, the resin portion 30 filled in the through hole TH of the silicon wafer 10 is removed. When the resin part 30 consists of an acrylic resin or a phenol resin, the resin part 30 is removed with those resin peeling liquids (strippers). Or when the resin part 30 consists of resists, the resin part 30 is removed by resist stripping solution (stripper) or dry ashing.

  As a result, the seed layer 40 is reliably formed with good adhesion on the lower surface (insulating layer 12) of the silicon wafer 10 provided with the hollow through hole TH.

  Subsequently, as shown in FIG. 5B, a metal plating layer is formed in the through hole TH of the silicon wafer 10 by electroplating using the seed layer 40 as a plating power feeding path to obtain the through electrode 50. The through electrode 50 is preferably formed from an electrolytic copper plating layer or an electrolytic nickel plating layer.

  At this time, plating growth starts from the seed layer 40 at the bottom of the through hole TH of the silicon wafer 10, and plating is sequentially performed from the bottom of the through hole TH toward the upper side, and the inside of the through hole TH is the through electrode 50. Filled.

  Therefore, unlike the related art described above, since plating is performed in order from the bottom to the top of the through hole TH, even if the inner surface of the through hole TH is uneven, the plating growth is not affected at all. There is no risk of voids or seams in the hole TH.

  Further, even when the through hole TH is processed in a barrel shape or the like, the through electrode 50 can be stably filled without generating voids or seams in the through hole TH.

  Furthermore, since the seed layer 40 is formed in close contact with the lower portion of the through hole TH of the silicon wafer 10 without a gap, there is no possibility that metal plating proceeds on the lower surface side of the silicon wafer 10.

  In addition, since it is not necessary to employ special plating conditions such as setting a long plating time in order to suppress the generation of voids and seams, the plating time can be shortened.

  When the through electrode 50 is formed so as to protrude upward from the upper surface of the silicon wafer 10, the upper surface of the through electrode 50 is polished by CMP or the like to be flush with the upper surface (insulating layer 12) of the silicon wafer 10. You may planarize so that it may become.

  Thereafter, as shown in FIG. 5C, the seed layer 40 is removed from the silicon wafer 10 by wet etching, thereby exposing the lower surfaces of the silicon wafer 10 and the through electrode 50.

  The seed layer 40 may be patterned by photolithography and etching to form a wiring layer connected to the through electrode 50.

  As described above, the wiring member 3 in which the through hole TH of the silicon wafer 10 is filled with the through electrode 50 is obtained.

  The wiring member 3 in FIG. 5C may be cut so as to obtain each electronic component mounting region and used as an individual wiring board. However, a multilayer wiring layer is formed on the wiring member 3 in FIG. The form of the wiring board will be described.

  As shown in FIG. 6A, first wiring layers 60 interconnected through the through electrodes 50 are formed on both sides of the silicon wafer 10 provided with the through electrodes 50 in FIG. The first wiring layer 60 is preferably formed by a semi-additive method.

  More specifically, seed layers (not shown) made of copper or the like are formed on both sides of the silicon wafer 10 by sputtering or electroless plating. Next, on both sides of the silicon wafer 10, plating resists (not shown) each having an opening provided in a portion where the first wiring layer 60 is disposed are formed on the seed layer.

  Subsequently, on both sides of the silicon wafer 10, metal plating layers (not shown) are respectively formed in the opening portions of the plating resist by electrolytic plating using the seed layer as a plating power feeding path.

  Further, after removing the plating resist on both sides of the silicon wafer 10, the first wiring layer 60 is obtained by etching the seed layer using the metal plating layer as a mask.

  5B, when the seed layer 40 is patterned and used as the first wiring layer 60, the first wiring layer 60 is formed only on the upper surface of the silicon wafer 10 by the semi-additive method.

  Next, as shown in FIG. 6B, an interlayer insulating layer 70 that covers the first wiring layer 60 is formed on both sides of the silicon wafer 10, and then the interlayer insulating layer 70 is processed with a laser or the like. Via holes VH reaching the first wiring layer 60 are formed. The interlayer insulating layer 70 is formed by attaching a resin sheet such as an epoxy resin or a polyimide resin.

  Alternatively, a photosensitive epoxy resin, a photosensitive polyimide resin, or a photosensitive resist may be used as the interlayer insulating layer 70, and the via hole VH may be formed by photolithography. In addition to attaching the resin sheet, a liquid resin may be applied.

  Further, as shown in FIG. 6C, the both sides of the silicon wafer 10 are connected to the first wiring layer 60 through the via hole VH (via conductor) by the same method as the method of forming the first wiring layer 60. Second wiring layers 62 are formed on the interlayer insulating layer 70, respectively.

  Subsequently, as illustrated in FIG. 7, solder resists 72 each having an opening 72 a are formed on the connection portion of the second wiring layer 62 on both sides of the silicon wafer 10. Further, contact layers C are obtained by forming Ni / Au plating layers in order from the bottom on the connection portions of the second wiring layers 62 on both sides.

  Furthermore, each wiring board 1 is obtained by cutting the silicon wafer 10 so that each electronic component mounting area is obtained. The timing of cutting the silicon wafer 10 may be performed after mounting the electronic component, or may be performed before mounting the electronic component.

  As described above, the wiring board 1 of the first embodiment is obtained as shown in FIG. FIG. 7 shows a state in which the silicon wafer 10 is cut before mounting electronic components, and the silicon wafer 10 is divided into individual silicon substrates 10x.

  In the present embodiment, two multilayer wiring layers connected to the through electrode 50 are formed on both sides of the silicon wafer 10, respectively. However, n multilayer wiring layers (n is an integer of 1 or more) are arbitrarily formed. be able to.

  As described above, in the method for manufacturing a wiring board according to the present embodiment, the protective film 20 is disposed on the lower surface of the silicon wafer 10 provided with the through hole TH, and the resin portion 30 is filled in the through hole TH.

  Next, after removing the protective film 20, the seed layer 40 is formed on the lower surfaces of the silicon wafer 10 and the resin portion 30 with good adhesion by a sputtering method or the like.

  Further, after the resin portion 30 is removed to make the through hole TH hollow, the through electrode 50 is formed in the through hole TH by electrolytic plating. The seed layer 40 is removed as necessary, and a multilayer wiring layer connected to the through electrode 50 is formed on both sides of the silicon wafer 10.

  By adopting such a method, the metal plating layer can be filled with reliability into the through hole TH of the silicon wafer 10 without causing a problem, and the through electrode 50 with a narrow pitch can be obtained with a high yield. .

In the embodiment described above, a silicon wafer is used as the substrate, but a glass substrate or a ceramic substrate such as alumina (Al ₂ O ₃ ) or silicon carbide (SiC) may be used. When a glass substrate is used, a through hole is formed by laser, wet etching, or drilling. When a ceramic substrate is used, a through hole is formed in the green seed before sintering by punching, or the ceramic substrate is processed by a laser to form a through hole. And the through-hole provided in the glass substrate or the ceramic substrate is filled with the penetration electrode by the same method.

  FIG. 8 shows a state in which a semiconductor chip is mounted on the wiring board 1 of the first embodiment shown in FIG. As shown in FIG. 8, the connecting portion of the semiconductor chip 80 (LSI chip) is flip-chip connected to the contact layer C of the second wiring layer 62 on the upper side of the wiring substrate 1 by the bump electrode 82. Furthermore, the underfill resin 84 is filled in the gap below the semiconductor chip 80.

  For example, when a CPU chip is used as the semiconductor chip 80, a memory chip (not shown) is similarly mounted in the vicinity of the side.

  Then, external connection terminals 86 are provided by mounting solder balls on the contact layer C of the second wiring layer 62 on the lower side of the wiring board 1.

  By the first and second wiring layers 60 and 62 on both sides of the silicon substrate 10x, the pitch is widened so that the pitch of the connection portions of the semiconductor chip 80 corresponds to the pitch of the connection electrodes of the mounting substrate.

  As described above, in the example of FIG. 8, the wiring substrate 1 of the first embodiment is used as an interposer for aligning or grid-converting the semiconductor chip 80 and the mounting substrate.

  FIG. 9 shows a state in which electronic components are mounted on the wiring board 1a according to the modification of the first embodiment. As shown in FIG. 9, the wiring board 1a of the modification of the first embodiment is used as a package board. A cavity 5 (concave portion) is formed at the center of the silicon substrate 10 x, and a through hole TH is provided on the bottom side of the cavity 5. Insulating layers 12 are formed on both sides of the silicon substrate 10x and the inner surface of the through hole TH.

  Further, the through electrode 50 is filled in the through hole TH of the silicon substrate 10x by the same method as described above. A wiring layer 60a connected to the through electrode 50 is formed on the lower surface of the silicon substrate 10x.

  Further, a solder resist 72 having an opening 72a provided on the connection portion of the wiring layer 60a is formed on the lower surface of the silicon substrate 10x. A contact layer C made of a Ni / Au plating layer or the like is formed for connection of the wiring layer 60a.

  A connection electrode 80x of an electronic component 80a such as an LED or a sensor is mounted on the upper surface of the through electrode 50 in the cavity 5 of the silicon substrate 10x by flip chip connection. Further, a cap 90 made of glass or the like is bonded on the silicon substrate 10x.

  As described above, the wiring substrate manufactured in the present embodiment can be applied to various substrates including through electrodes such as an interposer and a package substrate.

(Second Embodiment)
10 to 12 are cross-sectional views illustrating a method of manufacturing a wiring board according to the second embodiment. A feature of the second embodiment is not to form an insulating layer on the silicon wafer by thermal oxidation or CVD, but to leave the resin portion filled in the through hole in a ring shape on the inner wall surface to form a sidewall insulating portion. . In the second embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  In the method of manufacturing the wiring board according to the second embodiment, as shown in FIG. 10A, the step (FIG. 3D) of forming the insulating layer 12 on the silicon wafer 10 in the first embodiment described above is omitted. After the protective film 20 is disposed on the lower surface of the silicon wafer 10, the through hole TH is filled with the resin portion 30.

  Next, as shown in FIG. 10B, the protective film 20 is removed from the silicon wafer 10. Further, as shown in FIG. 10C, a seed layer 40 is formed on the lower surfaces of the silicon wafer 10 and the resin portion 30 by the same method as in the first embodiment.

  Subsequently, as shown in FIG. 10 (d), the resin portion 30 is left in a ring shape on the inner wall surface of the through hole TH by forming a through hole by penetrating the central portion of the resin portion 30 with a laser or the like. The side wall insulating portion 30a. At this time, the resin part 30 is selectively processed with respect to the seed layer 40 (copper). Further, the inside of the through hole TH is cleaned by performing a desmear process by a permanganic acid method or the like.

  Alternatively, the side wall insulating portion 30a may be obtained by forming the resin portion 30 from a photosensitive resin and forming through holes in the photosensitive resin by patterning by photolithography.

  Furthermore, as shown in FIG. 11A, the through-hole 50 is filled into the through hole TH by electrolytic plating using the seed layer 40 as a plating power feeding path by the same method as in the first embodiment.

  Thereby, the through electrode 50 is formed in a state of being electrically insulated from the silicon wafer 10 by the side wall insulating portion 30a. Thereafter, as shown in FIG. 11B, the seed layer 40 is removed.

  Next, as shown in FIG. 11C, a photosensitive resin layer is formed on both sides of the silicon wafer 10, and exposure / development by photolithography is performed. Thereby, the insulating pattern layer 14 is formed on both sides of the silicon wafer 10.

  The insulating pattern layers 14 on both sides are formed so as to extend from the silicon wafer 10 to overlap with the sidewall insulating portions 30a, and the openings 14a of the insulating pattern layer 14 are disposed on the upper and lower surfaces of the through electrodes 50, respectively.

  Subsequently, as shown in FIG. 12, similarly to FIG. 7 of the first embodiment, two multilayer wiring layers (first and second wiring layers) connected to the through electrode 50 are formed on both sides of the silicon wafer 10. 60, 62, an interlayer insulating layer 70, and a solder resist 72) are formed.

  Thereby, the wiring board 2 of 2nd Embodiment is obtained. Furthermore, as in FIG. 8 of the first embodiment, a semiconductor chip (not shown) is flip-chip connected to the contact layer C of the uppermost second wiring layer 62 of the wiring board 2.

  Also in the second embodiment, as in FIG. 9 of the first embodiment, it may be used as a package substrate having a cavity.

  The wiring board manufacturing method of the second embodiment also has the same effect as that of the first embodiment.

(Third embodiment)
In the manufacturing method of the first embodiment described above, the through electrode 50 is obtained by performing electrolytic copper plating on the entire through hole TH of the silicon wafer 10. Since the through electrode 50 (electrolytic copper plating layer) is simply in contact with the side surface (silicon oxide layer) of the through hole TH, the adhesion between the side surface of the through hole TH and the through electrode 50 is not sufficient.

  As illustrated in FIG. 9, there is a case where the cap 90 is provided on the wiring board 10 x provided with the cavity 5 and the electronic component 80 a is hermetically sealed in the cavity 5. In this case, the cavity 5 may be evacuated and decompressed, or the cavity 5 may be filled with an inert gas.

  In such a mounting structure, since the adhesion between the through electrode 50 and the side surface of the through hole TH is poor, the atmosphere enters the cavity 5 from the outside, and it is impossible to secure a reduced pressure, or the inert gas concentration is low. There is a possibility that sufficient reliability cannot always be obtained.

  In the wiring substrate manufacturing method according to the third embodiment to be described next, since the through electrode is formed with good adhesion at the lower part of the through hole, it is possible to prevent air from entering the inside of the hermetically sealed cavity. be able to.

  In the third embodiment, detailed description of the same steps and the same elements as those in the first embodiment is omitted.

  In the method of manufacturing the wiring board of the third embodiment, as shown in FIG. 13A, first, through holes are formed in the silicon wafer 10 by the same method as that of FIGS. 3A to 3D of the first embodiment. After forming TH, a silicon oxide layer is formed on the entire silicon wafer 10 to obtain the insulating layer 12.

  Next, as shown in FIG. 13B, a protective film 21 is attached to the lower surface of the silicon wafer 10. At this time, a thermoplastic resin is used as the protective film 21, and the protective film 21 is pressed toward the silicon wafer 10 while being heated. Thus, the softened protective film 21 is pushed into the through hole TH of the silicon wafer 10, and the filling portion 21a is partially formed below the through hole TH.

  As the protective film 21, a PET film or an acrylic film can be used.

  For example, when the thickness of the silicon wafer 10 is 200 to 300 μm and the diameter of the through hole TH is 50 to 60 μm, the height h of the filling portion 21a from the lower end of the through hole TH is set to 20 to 50 μm.

  Subsequently, as shown in FIG. 13C, the resin portion 30 is filled into the through hole TH of the silicon wafer 10 by the same method as the process of FIG. 4B of the first embodiment.

  Further, as shown in FIG. 13D, the protective film 21 provided on the lower surface of the silicon wafer 10 is peeled off and removed. Thereby, the lower surfaces of the silicon wafer 10 and the resin part 30 are exposed.

  At this time, since the resin portion 30 is raised in the through hole TH by the height h of the filling portion 21a of the protective film 21, when the protective film 21 is removed, the lower portion of the through hole TH becomes a cavity. The lower side surface LS is partially exposed.

  In this way, a structure is obtained in which the resin part 30 is partially filled in the through hole TH of the silicon wafer 10 so that the lower part thereof is hollow.

  Although the method of obtaining the structure of FIG. 13D by the first method shown in FIGS. 13A to 13D has been described, the second method shown in FIGS. 14A to 14E described later is used. The method may be used to obtain the same structure as in FIG.

  More specifically, as shown in FIG. 14A, first, after forming the through hole TH in the silicon wafer 10 by the same method as in FIGS. 3A to 3D of the first embodiment, An insulating layer 12 is obtained by forming a silicon oxide layer on the entire portion 10.

  Next, as shown in FIG. 14B, the entire side surface of the through hole TH is formed on the lower surface of the silicon wafer 10 in FIG. 14A by the same method as in the step of FIG. 4A of the first embodiment. The protective film 20 is arrange | positioned so that it may expose.

  Subsequently, as shown in FIG. 14C, the resin portion 30 is filled in the entire through hole TH of the silicon wafer 10 by the same method as the process of FIG. 4B of the first embodiment.

  Furthermore, as shown in FIG. 14D, the protective film 20 provided on the lower surface of the silicon wafer 10 is peeled off and removed, as in the step of FIG. 4C of the first embodiment.

Next, as shown in FIG. 14E, the lower part of the resin part 30 is partially removed by a dry process such as ashing using oxygen (O ₂ ) gas to expose the lower side surface LS of the through hole TH. . The height ha of the lower side surface LS of the through hole TH corresponds to the height h of the filling portion 21a of the protective film 21 in FIG. 13B of the first method described above.

  When removing the lower portion of the resin portion 30, a mask material is formed on the entire upper surface of the silicon wafer 10 as necessary to protect the upper surface side of the resin portion 30.

  As a result, as shown in FIG. 14E, the same structure as that shown in FIG. 13D is obtained by the second method.

  As described above, the structure in which the resin portion 30 is partially filled in the through hole TH of the silicon wafer 10 so that the lower portion is hollow by the first method or the second method (FIG. 13D). And FIG.14 (e)) can be obtained.

  Next, as shown in FIG. 15A, the first seed layer 41a is formed on the lower surface LS of the silicon wafer 10 and the resin portion 30, and the lower side surface LS of the through hole TH by sputtering, vapor deposition, CVD, or the like. To do.

  In a preferred example of the first seed layer 41a, a laminated film in which a titanium (Ti) layer / copper (Cu) layer or a chromium (Cr) layer / copper layer is formed in this order from the silicon wafer 10 side is used. The thickness of the first seed layer 41a is set to about 1 μm.

  At this time, since the first seed layer 41a is formed by a sputtering method, a vapor deposition method, a CVD method, or the like, the insulating layer 12 (silicon oxide layer) on the lower surface of the silicon wafer 10 and the lower side surface LS of the through hole TH are insulated. It is formed on the layer 12 (silicon oxide layer) with good adhesion.

  Since the titanium layer or the chromium layer has better adhesion to the insulating layer 12 (silicon oxide layer) than the copper layer, it is preferable to form the titanium layer or the chromium layer under the copper layer. The layer 41a may be formed only from a copper layer.

  Next, as shown in FIG. 15B, a metal plating layer made of copper, nickel (Ni), or the like is formed on the first seed layer 41a by electrolytic plating or electroless plating to form the second seed layer 41b. obtain.

  When the second seed layer 41b is obtained by forming the metal plating layer, the lower side of the through hole TH is covered with the metal plating layer so that the lower cavity of the through hole TH is buried and no recess is generated below the through hole TH. Fully embedded. In this way, the second seed layer 41b is formed with the entire bottom surface being flat. The second seed layer 41b also functions as a substrate reinforcing layer.

  In the step of forming the second seed layer 41b, the lower cavity of the through hole TH is not completely filled, and the lower cavity of the through hole TH is completely filled at the same time in the process of obtaining the upper metal plating portion 51a described later. Good.

  Thereby, the seed layer 41 formed from the first seed layer 41a and the second seed layer 41b is obtained on the lower surface of the silicon wafer 10 and the resin portion 30 and the lower side surface LS of the through hole TH.

  In this way, the seed layer 41 is formed with good adhesion on each insulating layer 12 on the lower surface of the silicon wafer 10 and the lower side surface LS of the through hole TH.

  Further, since the electroless plating layer (such as a copper layer or a nickel layer) formed as the second seed layer 41b is formed with good adhesion to the insulating layer 12 (silicon oxide layer), the first seed layer 41a is omitted. Thus, the seed layer may be formed only from the electroless metal plating layer.

  Alternatively, a seed layer may be obtained by forming a conductive paste on the lower surface of FIG. 13D or FIG. 14E by a squeegee method or printing. As the conductive paste, a copper (Cu) paste or a silver (Ag) paste is used. The conductive paste contains conductive metal powder and a binder resin as main components, and a conductive layer is obtained by heating and curing the binder resin.

  A conductive layer obtained from the conductive paste is formed on the insulating layer 12 (silicon oxide layer) with good adhesion. For this reason, the first seed layer 41a in FIG. 15A may be omitted, and the seed layer may be formed only from the conductive paste, or the first seed layer 41a (titanium layer / copper layer or chromium layer / copper layer). A conductive paste may be formed on the layer) to form a seed layer.

  The conductive paste is formed with a thickness that fills the lower cavity of the through hole TH of the silicon wafer 10. When the seed layer is obtained using the conductive paste, it is not necessary to form the second seed layer 41b (copper plating layer or nickel plating layer).

  As described above, in order to obtain sufficient adhesion of the seed layer 41 under the through hole TH, the layer that contacts the lower side surface LS of the through hole TH is formed by sputtering, vapor deposition, or CVD. It is formed from a metal layer, an electroless metal plating layer, or a conductive paste. Furthermore, as a metal layer formed by sputtering, vapor deposition, or CVD, a titanium layer or a chromium layer has excellent adhesion.

  Subsequently, as shown in FIG. 15C, the resin part 30 is removed by a method similar to the process of FIG. 5A of the first embodiment, so that the first seed layer 41a is formed below the through hole TH. To expose. As a result, the seed layer 41 is reliably formed with good adhesion on the lower surface of the silicon wafer 10 having the hollow through hole TH and the lower side surface LS of the through hole TH.

  When the uppermost layer of the first seed layer 41a is a titanium layer or a chromium layer, the titanium layer or the chromium layer is removed by wet etching or the like until the copper layer is exposed in the through hole TH. In the next step, when the electrolytic copper plating layer is filled in the through hole TH of the silicon wafer 10, the electrolytic plating is not performed well on the titanium layer or the chromium layer, so the copper layer needs to be exposed. .

  Thereafter, as shown in FIG. 15D, as in the step of FIG. 5B of the first embodiment, the through hole TH of the silicon wafer 10 is obtained by electrolytic plating using the seed layer 41 as a plating power feeding path. A copper plating layer or the like is formed from the lower side to the upper side to obtain the upper metal plating part 51a.

  Next, as shown in FIG. 15E, the seed layer 41 on the lower surface side of the silicon wafer 10 is polished and removed by CMP (Chemical Mechanical Polishing) or the like until the insulating layer 12 is exposed.

  Thus, the through electrode 51 is formed by the upper metal plating part 51a embedded in the upper main part of the through hole TH of the silicon wafer 10 and the lower metal part 51b embedded in the lower part of the through hole TH.

  The lower metal portion 51b of the through electrode 51 is formed of a first seed layer 41a that contacts the lower surface of the upper metal plating portion 51a and the lower side surface LS of the through hole TH, and a second seed layer 41b disposed therebelow. The

  Thereafter, as shown in FIG. 16, as in FIG. 7 of the first embodiment, two multilayer wiring layers (first and second wiring layers) connected to the through electrode 51 are formed on both sides of the silicon wafer 10. 60, 62, an interlayer insulating layer 70, and a solder resist 72) are formed.

  Thereby, the wiring board 2a of 3rd Embodiment is obtained. Also in the third embodiment, the silicon wafer 10 is cut at a required timing before or after electronic components are mounted to obtain the individual wiring board 2a.

  Thereafter, as shown in FIG. 17, the semiconductor chip 80 is flip-chip connected to the contact layer C of the uppermost second wiring layer 62 of the wiring board 2a by the bump electrode 82, as in FIG. 8 of the first embodiment. . Further, a cap 90 is provided on the wiring substrate 2, and the semiconductor chip 80 is hermetically sealed in the housing portion H in the cap 90.

  Note that underfill resin is filled in the lower gap of the semiconductor chip 80 as necessary.

  Also in the third embodiment, as in FIG. 9 of the first embodiment, it may be used as a package substrate having a cavity.

  The wiring board manufacturing method of the third embodiment also has the same effect as that of the first embodiment. In addition, in the third embodiment, the first seed layer 41 a formed by sputtering or the like is formed in close contact with the lower side surface LS of the through hole TH of the silicon substrate 10 x, and as a part of the through electrode 51. It is functioning.

  For this reason, when the housing portion H in the cap 90 is evacuated and decompressed, the interface between the lower side surface LS of the through hole TH and the first seed layer 41a has good adhesion, so that the entry of air from the outside is prevented. The

  Therefore, the problem that the atmospheric pressure from the outside enters the housing portion H in the cap 90 and the decompression cannot be secured is solved. Further, even when the accommodating portion H in the cap 90 is filled with an inert gas, the concentration of the inert gas is prevented from being lowered due to the entry of the atmosphere.

  Thereby, the semiconductor chip 80 can be hermetically sealed in the accommodating portion H in the cap 90 with high reliability.

DESCRIPTION OF SYMBOLS 1,1a, 2,2a ... Wiring board, 3 ... Wiring member, 5 ... Cavity, 10 ... Silicon wafer, 10x ... Silicon substrate, 11 ... Resist, 11a, 14a, 72a ... Opening, 12 ... Insulating layer, 20, DESCRIPTION OF SYMBOLS 21 ... Protective film, 21a ... Filling part, 30 ... Resin part, 30a ... Side wall insulating part, 40, 41 ... Seed layer, 41a ... First seed layer, 41b ... Second seed layer, 50, 51 ... Through electrode, 51a ... upper metal plating part, 51b ... lower metal part, 60 ... first wiring layer, 60a ... wiring layer, 62 ... second wiring layer, 70 ... interlayer insulating layer, 72 ... solder resist, 80 ... semiconductor chip, 80a ... Electronic components, 80x ... connection electrode, 82 ... bump electrode, 86 ... external connection terminal, 90 ... cap, C ... contact layer, H ... receiving portion, LS ... lower side, TH ... through hole, VH ... via hole.

Claims (12)

Preparing a substrate with a through hole penetrating in the thickness direction;
Placing a protective film on the lower surface of the substrate;
Filling the resin part in the through hole;
Removing the protective film to expose the lower surface of the substrate and the lower surface of the resin portion;
Forming a seed layer on the lower surface of the substrate and the lower surface of the resin portion;
Removing the resin part from the through hole;
A method of manufacturing a wiring board, comprising: in this order, a step of filling the through hole with a metal plating layer to obtain a through electrode by electrolytic plating using the seed layer as a plating power feeding path. The substrate is a silicon wafer;
The method of manufacturing a wiring board according to claim 1, wherein the step of preparing the substrate having the through hole includes forming an insulating layer on both surfaces of the silicon wafer and on the inner surface of the through hole. After the step of obtaining the through electrode,
The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the seed layer.   The method for manufacturing a wiring board according to claim 1, wherein the resin portion is made of an acrylic resin, a phenol resin, or a resist. After the step of removing the seed layer,
4. The method for manufacturing a wiring board according to claim 3, further comprising a step of forming n layers (n is an integer of 1 or more) of wiring layers connected to the through electrodes on both sides of the substrate. The substrate is a silicon wafer;
After the step of forming the seed layer,
A step of obtaining a side wall insulating part by forming a through hole in the resin part so as to leave the resin part on the inner wall surface in the through hole;
After the step of obtaining the through electrode,
The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the seed layer. After the step of removing the seed layer,
The method of manufacturing a wiring board according to claim 6, further comprising forming an insulating pattern layer having an opening on the through electrode on both sides of the silicon wafer.   The method for manufacturing a wiring board according to claim 1, wherein the substrate is a glass substrate or a ceramic substrate. In the step of arranging a protective film on the lower surface of the substrate,
The protective film is pushed into the through hole of the substrate, and a filling portion is partially formed at the bottom of the through hole,
In the step of removing the protective film,
The lower side surface of the through hole of the substrate is exposed,
In the step of forming the seed layer,
4. The method for manufacturing a wiring board according to claim 1, wherein the seed layer is formed on the lower side surface of the through hole. After the step of removing the protective film, further comprising the step of exposing the lower side surface of the through hole of the substrate by partially removing the lower portion of the resin portion,
In the step of forming the seed layer,
4. The method for manufacturing a wiring board according to claim 1, wherein the seed layer is formed on the lower side surface of the through hole.   In the seed layer, the layer in contact with the lower side surface of the through hole is formed of a metal layer, an electroless metal plating layer, or a conductive paste formed by a sputtering method, a vapor deposition method, or a CVD method. The method for manufacturing a wiring board according to claim 9 or 10, characterized in that:   The method for manufacturing a wiring board according to claim 11, wherein the metal layer is a titanium layer or a chromium layer.

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