JP4580752B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device .

Conventionally, there is a semiconductor device 52 configured by embedding a semiconductor element 51 in a package 53 having the form of a wiring board as shown in FIG. 10A (for example, Patent Document 1).
The package 53 has a core substrate 50 on which a semiconductor element 51 is bonded and mounted. An insulating layer 55a is provided on the upper surface of the core substrate 50 so as to cover the semiconductor element 51, and a wiring pattern 54a having a required shape is formed on the insulating layer 55a. The wiring pattern 54a and an electrode pad (not shown) arranged on the upper surface of the semiconductor element 51 are connected by a conductor layer 62 formed on the inner wall surface of the via hole 61 that penetrates the insulating layer 55a.
Further, a wiring pattern 54b having a required shape is formed on the lower surface of the core substrate 50, and the wiring pattern 54b is electrically connected to the wiring pattern 54a on the upper surface side by a conductor layer 60 formed on the inner wall surface of the through hole 59. Has been.

Furthermore, the wiring patterns 54a and 54b formed on the core substrate 50 are covered with solder resist layers 63 and 63, respectively. The solder resist layers 63 and 63 have openings corresponding to the pad portions of the wiring patterns 54a and 54b, and solder bumps 64 as external connection terminals are joined to the pad portions through the openings.
The semiconductor device 52 having the above configuration is advantageous for high integration and miniaturization because the semiconductor element 51 is embedded in the package 53, and has high commercial value.

  By the way, the semiconductor device 52 has a problem that the crack 57 is likely to occur in the insulating layer 55 a outside the semiconductor element 51. There is also a problem that a step 58 is likely to occur in the wiring pattern 54 a provided outside the semiconductor element 51.

These defects are caused by the method of manufacturing the semiconductor device.
As shown in FIG. 10B, in the manufacture of the semiconductor device 52, first, the semiconductor element 51 is mounted on the upper surface of the core substrate 50 via an adhesive. Thereafter, when forming the insulating layer 55 a, a resin film as the insulating layer 55 a is overlaid so as to cover the semiconductor element 51 mounted on the core substrate 50. At this time, the insulating layer 55 c on the semiconductor element 51 is formed so as to protrude from the periphery by the thickness of the semiconductor element 51. Due to the protruding portion 55c, the step 58 of the wiring pattern 54a and the crack 57 of the insulating layer 55a occurred.
The crack 57 in the insulating layer and the step 58 in the wiring pattern cause disconnection and the like, causing a malfunction of the semiconductor device.

As a semiconductor device that solves the above problems, there is one described in Patent Document 2. In this method, a wiring pattern having the same thickness as that of the semiconductor element is formed so that the upper surface of the semiconductor element and the upper surface of the wiring pattern have substantially the same height.
According to this, when the thickness of the semiconductor element is relatively large, the wiring pattern must also be formed thick. In order to obtain a thick wiring pattern, plating time is required, and the above-described manufacturing method has a problem that efficiency is poor. Furthermore, the thick wiring pattern is liable to be cracked and has a drawback of poor durability.
JP 2001-217337 A JP 2004-165277 A

Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a highly reliable semiconductor device manufacturing method that is free from disconnection due to cracks in the insulating layer, steps in the wiring pattern, and the like. Is to provide.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a semiconductor element is buried in an insulating layer in a package in which wiring patterns are laminated via an insulating layer. a) a core substrate or core formed insulating layer on the substrate, thereby forming a first wiring pattern, and forming a first dummy metal layer on the mounting area for mounting the semiconductor element, then (b) , of the core substrate, wherein forming a first plating mask covering a portion other than the dummy metal layers, (c) then, by plating, a second dummy required thickness to the first dummy metal layer Forming a metal layer; (d) then removing the plating mask; and (e) then covering the surface of the core substrate including the first wiring pattern and the second dummy metal layer. First Forming an edge layer, planarizing continuously (f) then polished by, the second dummy metal layer and the first insulating layer to expose the second dummy metal layer (G) Next, a step of forming a via hole in which the first wiring pattern is exposed in the first insulating layer; and (h) Next, a conductor is placed in the via hole by plating through a plating mask. Filling to form vias, forming a second wiring pattern on the first insulating layer, and forming a third dummy metal layer on the second dummy metal layer; and (i) Next, a step of removing the first, second, and third dummy metal layers; and (j) Next , the second, third, and third dummy metal layers are removed in the second hole. The semiconductor element is mounted so that the upper surface is substantially the same as the upper surface of the wiring pattern. And degree, that a step of forming through (k) Then, on the second wiring pattern becomes the semiconductor element substantially flush, the insulating layer wiring pattern electrically connected by vias Features.
According to this, the insulating layer can be planarized without damaging the semiconductor element. In addition, since the upper surface of the semiconductor element and the upper surface of the wiring pattern are aligned, the insulating layer and wiring pattern laminated thereon can be flattened, and there is no disconnection caused by cracks in the insulating layer or steps in the wiring pattern. A highly reliable semiconductor device can be manufactured.

Further, in a method of manufacturing a semiconductor device in which a semiconductor element is buried in an insulating layer in a package in which wiring patterns are laminated via an insulating layer, (a) formed on the core substrate or on the core substrate in an insulating layer which is, to form a first wiring pattern, and forming a first dummy metal layer on the mounting area for mounting a semiconductor element, (b) then, the core substrate, the first dummy forming a plating mask which covers the region other than the metal layer, and forming a (c) then, by plating, the second dummy metal layer of required thickness on the first dummy metal layer, (d ) then removing the plating mask, (e) then forming a first insulating layer over the first wiring pattern and the surface of the core substrate including the second dummy metal layer and, (f) the following In, polished by, planarizing continuously the second dummy metal layer and the first insulating layer to expose the second dummy metal layers, (g) Then, the first insulating Forming a via hole exposing the first wiring pattern in the layer; and (h) then forming a via by filling the via hole with a conductor by plating through a plating mask. Forming a second wiring pattern on the insulating layer and forming a third dummy metal layer on the second dummy metal layer; (i) Next, the steps (b) to (h) The process is repeated to form one or more dummy metal layers on the third dummy metal layer, and to be electrically connected to the underlying wiring pattern through the via via the insulating layer forming a wiring pattern, and then (j) Removing the laminated dummy metal layer, (k) Next, the dummy metal layer remains in the holes was removed, the semiconductor to be substantially the same upper surface and the upper surface of the wiring pattern of the uppermost layer a step of mounting elements, that a step of forming through (l) then, on the wiring pattern becomes the semiconductor element substantially flush, the insulating layer wiring pattern electrically connected by vias It is characterized by.
According to this, even when the semiconductor element is relatively thick, it is possible to manufacture a highly reliable semiconductor device free from disconnection due to a crack in the insulating layer or a step in the wiring pattern.

  According to the present invention, it is possible to provide a highly reliable semiconductor device without a disconnection or the like due to a crack in an insulating layer or a step in a wiring pattern.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the present invention.
The semiconductor device 10 includes a package 26 formed in the form of a wiring board and two semiconductor elements 27a and 27b embedded and mounted in the package 26.
The package 26 has a core substrate 28, and a multilayer wiring structure is provided on each side of the core substrate 28 to form a wiring substrate. The multilayer wiring structure is a structure in which wiring patterns are laminated in layers via insulating layers, and each wiring pattern is electrically connected by a via formed through the insulating layer. The semiconductor elements 27a and 27b are respectively buried in insulating layers of a multilayer wiring structure formed on both sides of the core substrate 28.

  In the semiconductor device 10, first to third three-layer wiring patterns are formed on both sides of the core substrate 28. The first wiring patterns 11a and 11b are directly formed on the core substrate 28, and the second wiring patterns 12a and 12b are formed on the first wiring patterns 11a and 11b via the first insulating layers 21a and 21b. Is formed. The third wiring patterns 13a and 13b are formed on the second wiring patterns 12a and 12b via the second insulating layers 22a and 22b.

The first wiring patterns 11a and 11b are electrically connected to the second wiring patterns 12a and 12b through the first vias 31a and 31b provided through the first insulating layers 21a and 21b. Has been. The second wiring patterns 12a and 12b are electrically connected to the third wiring patterns 13a and 13b through second vias 32a and 32b provided through the second insulating layers 22a and 22b. Yes. Each via is formed by filling a via hole provided through the insulating layer with a conductor.
Further, a through hole 16 is formed in the core substrate 28, and the first wiring pattern 11 a on one surface side of the core substrate 28 is formed by a conductor layer 16 a provided on the inner wall surface of the through hole 16. The first wiring pattern 11b on the other surface side is electrically connected. The through hole 16 is filled with an insulating resin 16b.

The semiconductor elements 27 a and 27 b are respectively bonded to both surfaces of the core substrate 28 and mounted so as to be embedded in the package 26.
Specifically, the semiconductor elements 27a and 27b are arranged and buried in the layers of the first wiring patterns 11a and 11b, the first insulating layers 21a and 21b, and the second wiring patterns 12a and 12b, respectively. .
The upper surfaces 12c and 12d of the second wiring patterns 12a and 12b and the upper surfaces 27c and 27d of the semiconductor elements 27a and 27b are positioned and aligned on substantially the same plane. That is, the thicknesses H1 and H2 of the semiconductor elements 27a and 27b are the thicknesses C1 and C2 of the first insulating layers 21a and 21b including the thicknesses of the first wiring patterns 11a and 11b, respectively, and the second wiring patterns. It is substantially equal to the value obtained by adding the thicknesses B1 and B2 of 12a and 12b.

Further, electrodes (not shown) provided on the upper surfaces 27c and 27d of the semiconductor element are connected to the third wiring patterns 13a and 13b through the second vias 32d and 32e.
Furthermore, solder resist layers (insulating layers) 29a and 29b are provided on both sides of the semiconductor device 10 to cover and protect the third wiring patterns 13a and 13b and the second insulating layers 22a and 22b from the outside. The solder resist layers 29a and 29b have openings formed at positions corresponding to the pad portions (not shown) of the third wiring patterns 13a and 13b, and are externally connected to the pad portions exposed through the openings. Solder bumps 30a and 30b as terminals are joined.

Next, a method for manufacturing the semiconductor device 10 having the above configuration will be described.
2 to 6 are partial cross-sectional views illustrating the manufacturing process of the semiconductor device 10. In addition, since the semiconductor device 10 is subjected to the same process on both sides of the core substrate 28 at the same time, the semiconductor elements 27a and 27b are mounted on both sides and a multilayer wiring structure is formed. In the figure, only one side is shown and description is omitted.
First, a double-sided copper-clad laminate in which copper foil is deposited on both sides of the core substrate 28 is prepared. As the core substrate 28, a resin substrate such as a glass / epoxy substrate or a BT (bismaleimide triazine) substrate can be used. After forming a plurality of through holes in this double-sided copper-clad laminate by drilling or laser processing, electroless copper plating is applied to the entire surface of the core substrate 28 including the inner wall surface of the through holes, and the copper plating formed thereby Further, copper electroplating is performed using the layer as a power feeding layer. Insulating resin 16b is filled into the through hole in which the conductor layer 16a is formed on the inner wall surface in this way to form the through hole 16.
Next, a copper plating layer is formed again by electroless copper plating on the entire surface of the core substrate 28 in which the through holes 16 are formed, and copper electroplating is performed on the both surfaces as a power supply layer. The core substrate 28 (see FIG. 2A) on which the copper layer (metal layer) 71 is formed can be obtained.

Next, the copper layer 71 on the core substrate 28 is etched to form the first wiring pattern 11a and the first dummy metal layer 41 (see FIG. 2D). The first dummy metal layer 41 is formed on the mounting area 73 of the semiconductor element 27a to be mounted later on the core substrate 28, and the first wiring pattern 11a is formed on the core substrate 28 so as to avoid the mounting area 73. Form.
In forming these, first, a resist layer 72 having a predetermined pattern is formed on the copper layer 71 as shown in FIG. The resist layer 72 can be formed by exposing and developing a photosensitive resist applied to the surface of the copper layer 71. Then, using the resist layer 72 as a mask, the exposed copper layer 71 is removed by etching (see FIG. 2C), and the resist layer 72 is removed by a chemical solution to remove the first wiring pattern 11a and the first wiring pattern 11a. A dummy metal layer 41 is formed (see FIG. 2D).

Next, a second dummy metal layer having a required thickness protruding above the upper surface 11c of the first wiring pattern 11a on the first dummy metal layer 41 provided in the mounting area 73 on which the semiconductor element is placed. 42 is formed (see FIG. 4A). In forming the second dummy metal layer 42, first, as shown in FIG. 3A, the entire upper surface of the core substrate 28 including the surfaces of the first dummy metal layer 41 and the first wiring pattern 11a is formed. The copper plating layer 74 is formed by electroless copper plating. And the resist layer 75 of the pattern shape which covers parts other than the 1st dummy metal layer 41 of the core board | substrate 28 is formed on the copper plating layer 74 (refer FIG.3 (b)). The resist layer 75 as a plating mask can be formed by exposing and developing a photosensitive resist applied to the surface of the copper plating layer 74.
Next, after the second dummy metal layer 42 is formed on the first dummy metal layer 41 by copper electroplating using the copper plating layer 74 as a power feeding layer (see FIG. 3C), the resist layer 75 is treated with a chemical solution. (See FIG. 3D), and the thinner copper plating layer 74 is removed by etching (see FIG. 4A). At this time, the total thickness of the first dummy metal layer 41 and the second dummy metal layer 42 is formed to be slightly larger than the thickness C1.

  Next, a resin film as the first insulating layer 21a is bonded onto the core substrate 28 so as to cover the surface of the core substrate 28 including the second dummy metal layer 42 and the first wiring pattern 11a (FIG. 4 ( b)). As the resin film, an insulating thermosetting resin such as an epoxy resin, a polyimide resin, or a polyphenylene ether resin can be used so as to cover the second dummy metal layer 42 and the first wiring pattern 11a. After the resin film is laminated on the core substrate 28, the resin film is thermally cured at a temperature of 80 to 140 ° C.

Thereafter, the upper surface of the thermally cured resin film and the upper surface of the second dummy metal layer 42 are simultaneously polished so that the upper surface of the second dummy metal layer 42 is exposed from the resin film, and the second dummy metal layer 42 It planarizes so that an upper surface and the upper surface of a resin film may be located on substantially the same plane.
Thus, the first insulating layer 21a made of a resin film and having a thickness C1 (including the thickness of the first wiring pattern 11a) is formed (see FIG. 4C). Therefore, the second dummy metal layer 42 is buried in the first insulating layer 21a.

Next, a via hole 31c that penetrates the first insulating layer 21a is provided at a predetermined position of the first insulating layer 21a so that the first wiring pattern 11a is exposed (see FIG. 4D). The via hole 31c can be formed by removing a predetermined portion of the first insulating layer 21a with a laser or the like.
Then, the second wiring pattern 12a, the first via 31a, and the third dummy metal layer 43 are formed by the same method as the method of forming the second dummy metal layer 42. That is, electroless copper plating is performed on the entire upper surface of the first insulating layer 21a and the second dummy metal layer 42 including the inside of the via hole 31c to form a copper plating layer. Then, a resist layer having a predetermined pattern is formed on the copper plating layer, and copper is electroplated using this as a plating mask. The resist layer is formed in a pattern having a shape that covers portions other than the opening portion of the via hole, the upper surface of the second dummy metal layer 42, and the portion where the second wiring pattern 12a is formed.

As a result, the first via 31a can be formed by filling the via hole 31c with copper as a conductor, and the second wiring pattern 12a and the third dummy metal layer 43 can be formed (FIG. 5). (See (a)). At this time, the electrolytic plating is performed so that the thickness of the second wiring pattern 12a becomes the aforementioned thickness B1. The third dummy metal layer 43 is formed on the second dummy metal layer 42, and the first, second, and third dummy metal layers 41, 42, 43 are stacked later. The semiconductor element 27a is substantially the same thickness (thickness H1) and is stacked in a column shape so as to have substantially the same shape, and the upper surface of the third dummy metal layer 43 and the upper surface 12c of the second wiring pattern 12a are approximately They are located on the same plane.
The resist layer and the copper plating layer are removed after electrolytic plating.

Next, the first, second and third dummy metal layers 41, 42 and 43 are removed from the core substrate 28 (see FIG. 5C). As a removal method, a resist layer 76 having an opening that exposes the upper surface of the third dummy metal layer 43 is formed so as to cover the second wiring pattern 12a and the first insulating layer 21a (FIG. 5). (See (b)), a method of removing the first, second, and third dummy metal layers 41, 42, 43 at a time by etching using the resist layer 76 as a mask can be employed.
After the dummy metal layers 41, 42, 43 are removed and the resist layer 76 is further removed (see FIG. 5C), the semiconductor element 27a is mounted in the hole where the dummy metal layer has been removed (FIG. 5 ( d)). The semiconductor element 27a is applied to the lower surface of the semiconductor element 27a and fixed to the mounting area 73 with the adhesive.
As a result, the upper surface 27c of the semiconductor element 27a mounted on the core substrate 28 and the upper surface 12c of the second wiring pattern 12a are positioned and aligned on substantially the same plane.

Thereafter, a usual method for forming a multilayer wiring structure can be employed.
That is, first, the second insulating layer 22a is formed by overlaying a resin film on the semiconductor element 27a, the second wiring pattern 12a, and the first insulating layer 21a by the same method as described above so as to cover them. (See FIG. 6 (a)). At this time, since the upper surface 27c of the semiconductor element 27a and the upper surface 12c of the second wiring pattern 12a are aligned and located on substantially the same plane, the protruding portion of the second insulating layer 22a is provided above the semiconductor element 27a. The upper surface 22c of the second insulating layer 22a can be planarized without being generated.

Next, the third wiring pattern 13a is formed on the second insulating layer 22a, and the second via 32a penetrating the second insulating layer 22a is formed. These can be formed by a method similar to the method of forming the second wiring pattern 12a and the first via 31a. That is, it is a method comprising the formation of via holes, formation of a copper plating layer by electroless copper plating, coating with a resist layer, electrolytic plating using the resist layer as a plating mask, and removal of the resist layer and the copper plating layer. In this way, the third wiring pattern 13a and the second via 32a that connects the third wiring pattern 13a and the second wiring pattern 12a are formed (see FIG. 6B).
The second via 32a formed at this time also includes a via 32d that connects the third wiring pattern 13a and the electrode provided on the upper surface 27c of the semiconductor element 27a. The via 32d is formed by forming a via hole so that the electrode of the semiconductor element 27a is exposed, and filling the via hole with copper by electrolytic plating.

Thereafter, a solder resist layer 29a having an opening formed at a position corresponding to the pad portion of the third wiring pattern 13a is formed so as to cover the third wiring pattern 13a and the second insulating layer 22a. Then, the solder bump 30a is reflowed and joined to the pad portion exposed through the opening portion to form an external connection terminal. At this time, in order to improve the adhesiveness between the solder bump 30a and the pad portion, the solder bump 30a is joined through a conductor film 77 such as Ni / Au provided on the pad portion (see FIG. 6B).
Thereafter, the semiconductor device 10 is manufactured by being divided into individual semiconductor devices on which the two semiconductor elements 27a and 27b are mounted.

In this embodiment, the following effects can be obtained.
The semiconductor device 10 is advantageous for high integration and miniaturization because the semiconductor element 27a and 27b are mounted on both sides of the core substrate 28 and the package 26 is formed by forming a multilayer wiring structure.
Also, by providing a dummy metal layer instead of the semiconductor element, the insulating layer can be flattened by polishing without destroying the semiconductor element, and a wiring pattern having an upper surface that is aligned with the upper surface of the semiconductor element can be easily formed. can do.
Thereby, the protrusion of the insulating layer above the semiconductor element can be eliminated, the generation of cracks in the insulating layer and the step of the wiring pattern can be prevented, and a highly reliable semiconductor device can be provided.

  In the semiconductor device described in Patent Document 2, a wiring pattern having the same thickness as the semiconductor element is formed, and the upper surface of the semiconductor element and the upper surface of the wiring pattern are flattened. On the other hand, in the above embodiment, the semiconductor element 27a is arranged and embedded in the first wiring pattern 11a, the first insulating layer 21a, and the second wiring pattern 12a. Therefore, even when the semiconductor element 27a is relatively thick, the thickness can be shared by the thicknesses of the two wiring patterns 11a and 12a and the first via 31a, and each of them must be extremely thick. Therefore, cracks and the like hardly occur in these, and the semiconductor device has durability and reliability.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device 80 of the second embodiment.
The semiconductor device 80 includes a package 78 formed in the form of a wiring board having a multilayer wiring structure, and semiconductor elements 27a and 27b embedded and mounted in the package 78, and has the same structure as that of the first embodiment. . The semiconductor device 80 of the second embodiment is different from the first embodiment in that the wiring pattern is composed of three layers (first to first layers) in the layer (K1, K2) where the semiconductor elements 27a, 27b are embedded in the package 78. 3 wiring patterns 11, 12, 13), and two layers (first vias 31 a, 31 b and second vias 32 a, 32 b) connecting these wiring patterns are formed.

  Then, the upper surfaces 13c and 13d of the third wiring patterns 13a and 13b and the upper surfaces 27c and 27d of the semiconductor elements are positioned and aligned on substantially the same plane. That is, the thicknesses H1 and H2 of the semiconductor elements 27a and 27b are the thicknesses C1 and C2 of the first insulating layers 21a and 21b (including the thicknesses of the first wiring patterns 11a and 11b), the second, respectively. The sum of the thicknesses J1 and J2 of the insulating layers 22a and 22b (including the thickness of the second wiring patterns 12a and 12b) and the thicknesses L1 and L2 of the third wiring patterns 13a and 13b is approximately equal.

Next, a method for manufacturing the semiconductor device 80 having the above configuration will be described.
8 and 9 are partial cross-sectional views for explaining the manufacturing process of the semiconductor device 80. The semiconductor device 80 is subjected to the same process on both sides of the core substrate 28 at the same time, so that the semiconductor elements 27a and 27b are mounted on both sides and a multilayer wiring structure is provided to provide a package 78. Therefore, only one side is shown in the figure and the description is omitted.
In the manufacture of the semiconductor device 80, first, the same process as that of the first embodiment described with reference to FIGS. 2 to 4 and FIG. 5A is performed on the core substrate 28. Thus, the first dummy metal layer 41, the second dummy metal layer 42, and the third dummy metal layer 43 are stacked in the mounting area 73, and the second wiring pattern 12a and the first wiring pattern 11a are formed. The core substrate 28 laminated through the first insulating layer 21a can be obtained (see FIG. 8A). The upper surface 43c of the third dummy metal layer 43 and the upper surface 12c of the second wiring pattern 12a are flattened so as to be located on substantially the same plane. Further, the second wiring pattern 12a and the first wiring pattern 11a are electrically connected by a first via 31a provided so as to penetrate the first insulating layer 21a.

Next, as shown in FIG. 8B, a fourth dummy metal layer 44 having a required thickness protruding above the second wiring pattern 12a is formed on the third dummy metal layer 43. . The method of forming the fourth dummy metal layer 44 is the method of forming the second dummy metal layer 42 in the first embodiment described with reference to FIGS. 3A to 3D and 4A. Similar steps are used.
When the fourth dummy metal layer 44 is formed, the first insulating layer 21a, the fourth dummy metal layer 44 and the second dummy metal layer 44 are formed in the same manner as the method shown in FIGS. 4B and 4C. A resin film as the second insulating layer 22a is overlaid thereon so as to cover the wiring pattern 12a. Then, the resin film and the upper surface of the fourth dummy metal layer 44 are simultaneously polished to expose the fourth dummy metal layer 44, and the upper surface of the fourth dummy metal layer 44 and the upper surface of the second insulating layer 22a. The flattening is performed so that 22c is positioned on substantially the same plane (see FIG. 8C). Thus, the second insulating layer 22a having the thickness J1 is formed, and the fourth dummy metal layer 44 is buried in the second insulating layer 22a.

Then, the third wiring pattern 13a is formed on the second insulating layer 22a and the second insulating layer 22a is formed by a method similar to the method described with reference to FIGS. 4D and 5A. A second via 32a is formed. At the same time, a fifth dummy metal layer 45 is formed on the fourth dummy metal layer 44 (see FIG. 8D).
Thus, the first to fifth dummy metal layers 41, 42, 43, 44, 45 are columnar so as to have substantially the same shape with the same thickness (thickness H 1) as the semiconductor element 27 a to be mounted thereafter. Laminate to. Further, a third wiring pattern 13 a having an upper surface 13 c aligned with the upper surface of the fifth dummy metal layer 45 is formed.

Next, the first to fifth dummy metal layers 41, 42, 43, 44, 45 are removed from the core substrate 28. For removal, similarly to the method described above, a resist layer 76 having a pattern shape exposing the upper surface of the fifth dummy metal layer 45 is formed (see FIG. 9A), and the dummy metal layer is formed using the resist layer 76 as a mask. The method of removing by etching can be used. The resist layer 76 is then removed with a chemical solution (see FIG. 9B).
Next, the semiconductor element 27a is mounted in the hole where the dummy metal layer has been removed. The semiconductor element 27a is fixed to the mounting area 73 via an adhesive (see FIG. 9C).
Thereafter, the third insulating layer 23a, the fourth wiring pattern 14a, and the third via are formed by a method similar to the method described with reference to FIGS. 6A and 6B in the first embodiment. 33a is formed. At this time, the upper surface 27c of the semiconductor element 27a and the upper surface 13c of the third wiring pattern 13a are flattened and aligned on substantially the same plane, so that the third insulating layer 23a is located above the semiconductor element 27a. The upper surface of the third insulating layer 23a can be flattened and stacked without generating a protruding portion (see FIG. 9D).

Thus, the fourth wiring pattern 14a is formed on the third wiring pattern 13a via the third insulating layer 23a, and both are electrically connected via the third via 33a. The third via 33a includes a via that connects the fourth wiring pattern 14a and the electrode provided on the upper surface 27c of the semiconductor element 27a.
Subsequently, a solder resist layer 29a is provided by the same method as in the first embodiment, and solder bumps 30a as external connection terminals are bonded to the pad portions of the fourth wiring pattern 14a. Thereafter, the semiconductor device 80 is divided.

According to the second embodiment, the following effects can be obtained as well as the same effects as the first embodiment.
In the semiconductor device 80, three layers of wiring patterns are provided in the layers (K1, K2) in which the semiconductor elements 27a, 27b are embedded, and the via is divided into a plurality of layers. According to this, even when the semiconductor element 27a is relatively thick, the wiring pattern or via can be formed thin, and disconnection due to a crack or the like of the via or wiring pattern can be prevented more reliably.

While the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to this embodiment, and it goes without saying that many modifications can be made without departing from the spirit of the invention. is there.
For example, the semiconductor element is not directly mounted on the core substrate 28 as in the first and second embodiments, but one layer or a plurality of layers formed on the core substrate 28 as shown in FIG. A semiconductor device 79 in which the semiconductor element 27a is fixed on the core substrate 28 through an insulating layer may be used. That is, it may be a semiconductor device in which a plurality of wiring patterns are stacked via an insulating layer below the layer (core substrate side) where the semiconductor element 27a is buried.
In this case, if a wiring pattern is laminated on the core substrate 28 via an insulating layer to form the insulating layer 21h having the mounting area 73 on which the semiconductor element 27a is mounted, the same method as in the first and second embodiments. Thus, the wiring pattern is laminated through the insulating layer while the dummy metal layer is laminated on the mounting area 73. In this manner, after forming the wiring pattern 14h having the upper surface 14s located on and substantially flush with the upper surface 27c of the semiconductor element 27a to be mounted thereafter, the dummy metal layer is removed and the semiconductor element 27a is mounted instead. Thereafter, wiring patterns, solder bumps, and the like are formed by the same method as in the first and second embodiments, and the semiconductor device 79 is manufactured.

In the first embodiment, the semiconductor device 10 in which two wiring patterns (first and second wiring patterns 11a and 12a) are provided in the insulating layer in which the semiconductor element is buried has been described. In the second embodiment, the semiconductor device 80 is described in which three wiring patterns are provided in the insulating layers (K1, K2) in which the semiconductor elements are buried, and two vias are formed accordingly. The number of wiring patterns may be four or more in the insulating layer in which the semiconductor element is buried, and the number of vias may be three or more correspondingly. 3A to 3D, FIG. 4A to FIG. 4D, and FIG. 5A are repeated in the embodiment so that the semiconductor element is buried. A desired number of wiring patterns can be formed in the layer.
Moreover, the wiring pattern provided outside the insulating layer in which the semiconductor element is buried is not limited to one layer, and may be a plurality of layers.
Further, the semiconductor device in which the semiconductor element is mounted on both sides of the core substrate and the multilayer wiring structure is provided has been described. However, the present invention is not limited thereto, and the semiconductor element may be mounted only on one side. Accordingly, a multilayer wiring structure may be provided only on one side where the semiconductor element is mounted. Furthermore, the number of semiconductor elements to be mounted per semiconductor device may be one or plural.
Moreover, the structure by which a several semiconductor element is embed | buried in the different layer on the same side of a core board | substrate may be sufficient.

  In the embodiment, the semi-additive method is used in forming the wiring pattern, the via, and the dummy metal layer. However, the present invention is not limited to this. A subtractive method of forming these by etching using a resist layer formed on the solid-patterned conductor layer as a mask may be used. Furthermore, the full additive method of forming these by performing electroless plating through a plating mask may be used.

It is sectional drawing of 1st Embodiment of the semiconductor device by this invention. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is sectional drawing of 2nd Embodiment of the semiconductor device by this invention. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is a fragmentary sectional view explaining the manufacturing process of a semiconductor device. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing of other embodiment of the semiconductor device by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 1st wiring pattern 12 2nd wiring pattern 13 3rd wiring pattern 21 1st insulating layer 22 2nd insulating layer 27 Semiconductor element 31 1st via | veer 32 2nd via | veer 73 mounting area

Claims (2)

In a manufacturing method of a semiconductor device in which a semiconductor element is buried in an insulating layer in a package in which wiring patterns are laminated via an insulating layer,
(A) forming a first wiring pattern on a core substrate or an insulating layer formed on the core substrate and forming a first dummy metal layer in a mounting area on which a semiconductor element is placed;
(B) Next, a step of forming a plating mask that covers a portion of the core substrate other than the first dummy metal layer;
(C) Next, a step of forming a second dummy metal layer having a required thickness on the first dummy metal layer by plating;
(D) Next, removing the plating mask;
(E) Next, forming a first insulating layer covering the surface of the core substrate including the first wiring pattern and the second dummy metal layer;
(F) Next, the step of exposing the second dummy metal layer by polishing and continuously planarizing the first insulating layer and the second dummy metal layer;
(G) Next, forming a via hole through which the first wiring pattern is exposed in the first insulating layer;
(H) Next, a via is formed by filling a via hole by plating through a plating mask to form a via, and a second wiring pattern is formed on the first insulating layer. Forming a third dummy metal layer on the dummy metal layer;
(I) Next, removing the first, second and third dummy metal layers;
(J) Next, the step of mounting the semiconductor element in the hole after removing the first, second and third dummy metal layers so that the upper surface is substantially the same as the upper surface of the second wiring pattern. When,
(K) Next, a step of forming a wiring pattern electrically connected by a via via an insulating layer on the second wiring pattern substantially flush with the semiconductor element is included. A method for manufacturing a semiconductor device. In a manufacturing method of a semiconductor device in which a semiconductor element is buried in an insulating layer in a package in which wiring patterns are laminated via an insulating layer,
(A) forming a first wiring pattern on a core substrate or an insulating layer formed on the core substrate and forming a first dummy metal layer in a mounting area on which a semiconductor element is placed;
(B) Next, a step of forming a plating mask that covers a portion of the core substrate other than the first dummy metal layer;
(C) Next, a step of forming a second dummy metal layer having a required thickness on the first dummy metal layer by plating;
(D) Next, removing the plating mask;
(E) Next, forming a first insulating layer covering the surface of the core substrate including the first wiring pattern and the second dummy metal layer;
(F) Next, the step of exposing the second dummy metal layer by polishing and continuously planarizing the first insulating layer and the second dummy metal layer;
(G) Next, forming a via hole through which the first wiring pattern is exposed in the first insulating layer;
(H) Next, a via is formed by filling a via hole by plating through a plating mask to form a via, and a second wiring pattern is formed on the first insulating layer. Forming a third dummy metal layer on the dummy metal layer;
(I) Next, the steps (b) to (h) are repeated to form one or more dummy metal layers on the third dummy metal layer, and the lower wiring pattern is interposed via the insulating layer. Forming one or more wiring patterns that are electrically connected to each other through vias;
(J) Next, removing the laminated dummy metal layer;
(K) Next, the step of mounting the semiconductor element so that the upper surface is substantially the same as the upper surface of the wiring pattern in the uppermost layer in the hole where the dummy metal layer has been removed,
(L) Next, a step of forming a wiring pattern electrically connected by a via via an insulating layer on the wiring pattern substantially flush with the semiconductor element is provided. Production method.

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