JP2004079736A - Substrate device with built-in chip and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To mount a chip with high density for miniaturization of a substrate device, and improve characteristics and reduce the cost. <P>SOLUTION: The device is provided with a core substrate 2 where proper wiring patterns 18 and 20 are formed and a chip mounting opening 3 is formed at a part, and with at least one or above bear chips 4 in which electrode forming faces 12 constitute faces similar to a main face by mounting them in the chip mounting opening 3 and sealing them with mounted insulating resin 5 and which are incorporated in the core substrate 2. Wiring layers 25 to 27 of one layer have wiring patterns 25b to 27b that are directly connected to an electrode 21 formed on the electrode forming face 12 of the bear chip 4 through a via 33 are formed in lamination on the main face of the core substrate 2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate device that is mounted on various electronic devices by mounting a semiconductor chip (simply abbreviated as a chip in this specification), an electronic component, and the like, and a method for manufacturing the same.
[0002]
[Prior art]
A board device is mounted on various electronic devices by mounting a chip, an electronic component, or the like on a main surface of a wiring board. As the substrate device, a so-called multi-module in which a plurality of chips are mounted to achieve multi-functions is also provided. In such a substrate device, as electronic devices become multifunctional, multifunctional, small, light, and thin, there is a demand for smaller, lighter and higher density mounting.
[0003]
As for the substrate device, a chip-size mounting method in which mounting is performed with a size substantially equal to the chip, or a bare chip in which a bare chip (referred to as a bare chip in this specification) in which a semiconductor element is not housed in a package is directly mounted. By adopting surface mounting technology such as mounting method, significant downsizing and high density mounting are achieved. The bare chip mounting method is generally connected by the wire bonding method or the tab method with the terminal formation surface of the chip facing up, or by attaching bumps such as solder or gold to the chip terminals and then reversing to solder or anisotropic conductive Connection is performed by a flip-chip method in which the connection is made with a conductive adhesive or the like. In the bare chip mounting method, a bare chip of KGD (known good die) is used.
[0004]
Conventional board devices generally have a limitation in mounting efficiency because chips and electronic components are mounted on the main surface of the wiring board. Even if the size of the chip is reduced by improving semiconductor manufacturing technology, the board device can exert its effect sufficiently because there is a limit to the miniaturization of the wiring pattern of the wiring board on which this chip is surface-mounted. There wasn't.
[0005]
In the substrate device, so-called three-dimensional mounting is realized in which the chips are accommodated in a multilayer by housing the chips inside the wiring board in order to achieve high-density mounting of chips and the like. For example, in Japanese Patent Laid-Open No. 6-45763, an opening is provided in a part of an inner layer substrate sandwiched between a pair of outer layer substrates to accommodate a chip, and formed on the main surface of one outer layer substrate corresponding to the opening. A substrate device (printed wiring board) in which a chip is surface-mounted on a pad of a wiring pattern is disclosed.
[0006]
Japanese Laid-Open Patent Publication No. 7-106509 discloses that individual semiconductor devices formed by housing chips in a recess provided in an insulating base material are stacked, and the chips of each semiconductor device are formed in the insulating base material. A substrate device (multilayered structure semiconductor device) connected to a terminal of an external substrate through a conductive path is disclosed.
[0007]
[Problems to be solved by the invention]
Although the above-described conventional three-dimensional mounting board devices can achieve higher density, all of them have a structure in which the chip is mounted on the wiring board by the surface mounting method, so that the chip can be miniaturized. Thus, it is necessary to form the wiring pattern of the wiring board finely and precisely. However, such a conventional substrate device has a limit in miniaturization corresponding to a miniaturized chip because the accuracy of the wiring board manufactured by the substrate technology is significantly different from the accuracy of the chip manufactured by the semiconductor technology. It was.
[0008]
In addition, the conventional substrate apparatus has a connection process in which bumps are provided on the chip electrodes and the wiring substrate is connected in a precisely positioned state, or wire bonding is performed between the chip electrodes and the land of the wiring substrate. Was necessary. Furthermore, the conventional board device is routed through an appropriate transmission line between the chip and the wiring pattern of the wiring board, so that the transmission line length is increased, and high-speed processing and anti-noise characteristics are deteriorated. There was a problem.
[0009]
Accordingly, the present invention has been proposed for the purpose of providing a low-cost and highly reliable chip-embedded substrate device capable of achieving high-density mounting of chips and reducing the size and improving the characteristics, and a method for manufacturing the same. It is.
[0010]
[Means for Solving the Problems]
A chip built-in substrate device according to the present invention that achieves the above-described object is provided with a core substrate in which an appropriate wiring pattern is formed and a chip loading opening is partially formed, and the chip loading opening is loaded and filled. By being sealed with a sealing resin, the electrode forming surface includes substantially the same surface as the main surface, and includes at least one bare chip built in the core substrate. The chip built-in substrate device is formed by laminating at least one wiring layer having a wiring pattern directly connected via electrodes and vias formed on the bare chip electrode forming surface on the main surface of the core substrate. .
[0011]
According to the chip-embedded substrate device according to the present invention configured as described above, high-density mounting can be achieved by incorporating the bare chip inside the core substrate together with the chip and electronic component mounted on the surface. As a result, downsizing and multi-functionalization of electronic devices will be realized. According to the chip-embedded substrate device, the electrode of the built-in bare chip and the wiring pattern of the wiring layer formed on the main surface of the core substrate are directly connected via vias, so that a connection process is unnecessary, so that high-speed processing is possible. And improvement in noise resistance, and further reduction in size and cost and cost.
[0012]
In addition, in the method for manufacturing a chip-embedded substrate device according to the present invention that achieves the above-described object, an appropriate wiring pattern is formed on the main surface of the base substrate via a release layer, and a chip loading opening is formed in part. A substrate bonding step of bonding the core substrate formed, a chip loading step of loading at least one bare chip with the electrode forming surface facing the release layer in the chip loading opening of the core substrate, and a bare chip in the chip loading opening A resin filling step of filling the holding sealing resin, a substrate peeling step of peeling the core substrate formed by sealing the bare chip in the chip loading opening via the peeling layer after the sealing resin is cured, and the bare chip At least one layer having a wiring pattern that is directly connected to the electrode formed on the electrode forming surface and vias on the main surface of the core substrate, the electrode forming surfaces constituting substantially the same surface It made and a wiring layer forming step of laminating forming a line layer.
[0013]
According to the method for manufacturing a chip-embedded substrate device according to the present invention having the above steps, by manufacturing a substrate device in which a bare chip is built in the core substrate together with a chip and an electronic component mounted on the surface, Chips and electronic components can be mounted at high density, and electronic devices can be miniaturized and multi-functionalized. According to the method for manufacturing a chip-embedded substrate device, the electrode connection of the embedded bare chip is directly performed via the wiring pattern and via of the wiring layer formed on the main surface of the core substrate without the need for a connection process. It is possible to manufacture a substrate device that achieves high-speed processing by shortening the line and improves the anti-noise characteristic, and is further reduced in size and thickness.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, details of the substrate device 1 shown in the drawings will be described as embodiments of the present invention. The substrate device 1 is a high-frequency circuit module substrate device mounted on, for example, a wireless transmission / reception circuit unit of a wireless communication terminal device, and includes a core substrate 2 in which a chip loading opening 3 is partially formed as shown in FIG. A base portion 6 is constituted by a bare chip 4 having a KGB characteristic loaded in the loading opening 3 and a sealing resin layer 5 etc. for holding and sealing the bare chip 4 in the chip loading opening 3. In the substrate device 1, a high-frequency circuit unit 9 including a multilayer wiring layer is formed on a build-up formation surface 7 of the core substrate 2 via a planarization insulating layer 8. A chip 10 or an electronic component 11 is surface-mounted on the upper layer to constitute a multi-module.
[0015]
As will be described in detail later, the substrate device 1 has a build-up formation in which the electrode forming surface 12 of the bare chip 4 housed inside the core substrate 2 is stacked with the high-frequency circuit unit 9 in cooperation with the main surface of the core substrate 2. The surface 7 is configured. The substrate device 1 constitutes a power supply system, a control system wiring section, or a mounting section on a mother board or the like for the high-frequency circuit section 9 in which the base section 6 is formed on the buildup forming surface 7.
[0016]
The core substrate 2 is composed of a double-sided wiring substrate or a multilayer wiring substrate manufactured by a well-known substrate technology. In FIG. 1, the first layer wiring substrate 13 and the second layer wiring substrate 14 are combined with an appropriate insulating adhesive layer or the like. It consists of a substrate with a four-layer structure joined via each other. Of course, the core substrate 2 may be configured in a multilayer structure. In the core substrate 2, one main surface of the first layer wiring substrate 13 constitutes a mounting surface 13a for a mother substrate or the like (not shown), and a plurality of electrodes 15 are formed on the mounting surface 13a together with appropriate wiring patterns.
[0017]
In the first layer wiring board 13, the mounting surface 13 a is covered with a solder resist layer 16 except for the electrodes 15. Although not described in detail, the core substrate 2 is appropriately connected to each electrode 15 and the wiring pattern and the first wiring pattern 18 formed on the main surface via through holes 17 formed in the first layer wiring substrate 13. . The core substrate 2 is connected to the second wiring pattern 20 formed on the main surface and the wiring pattern on the interior side through the through-hole 19 formed in the second layer wiring substrate 14 and on the first layer wiring substrate 13 side. The first wiring pattern 18 is appropriately connected.
[0018]
A chip loading opening 3 is formed in the core substrate 2 through the first layer wiring substrate 13 and the second layer wiring substrate 14. Although the chip loading opening 3 is illustrated as a rectangular opening located in the center of the core substrate 2, the first wiring pattern 18 of the first layer wiring substrate 13 and the second wiring of the second layer wiring substrate 14 are illustrated. What is necessary is just to form in the unformed area | region of the pattern 20, and it does not specifically limit about a formation position or opening shape. Further, the chip loading openings 3 may be formed at a plurality of locations on the core substrate 2.
[0019]
As is well known, the bare chip 4 is a semiconductor chip that is used in a state in which a semiconductor element having an integrated circuit formed on the main surface of a wafer is not housed in a package. As shown in FIG. The individual electrodes 21 are formed, for example, arranged in a matrix. The bare chip 4 is positioned and held by the encapsulating resin layer 5 in the chip loading opening 3 so that the electrode forming surface 12 forms substantially the same surface as the main surface of the second layer wiring substrate 14 of the core substrate 2. Sealed.
[0020]
The sealing resin layer 5 is formed, for example, by using an epoxy resin and filling the chip loading opening 3 in which the bare chip 4 is loaded and curing it. The insulating resin layer 5 positions and holds the bare chip 4 in the chip loading opening 3 and constitutes a part of the buildup forming surface 7 at the outer peripheral portion of the bare chip 4. The sealing resin layer 5 may be formed, for example, by a prepreg or the like, and may be filled in the chip loading opening 3 by the resin component, and further formed by an appropriate method.
[0021]
In the substrate device 1, as shown in FIG. 1, a heat radiation plate 22 is accommodated in the chip loading opening 3 so as to be superimposed on the main surface side of the wafer facing the electrode forming surface 12 of the bare chip 4. It is fixed and held by the sealing resin layer 5. In the sealing resin layer 5, a plurality of vias 24 are formed to connect between the heat dissipation plate 22 and the heat dissipation terminals 23 formed on the first wiring pattern 18 of the first layer wiring board 13.
[0022]
When the substrate device 1 is mounted on the mother board, the heat radiating terminal 23 is connected to a heat radiating member such as a heat sink provided on the mother board side, so that the bare chip 4 is connected via the heat radiating plate 22 and the via 24. Dissipates heat generated in The substrate device 1 does not require such a heat dissipation structure when the bare chip 4 does not generate a large amount of heat, and only the bare chip 4 is sealed in the chip loading opening 3 with a sealing resin.
[0023]
In the base portion 6 configured as described above, a planarization insulating layer 8 is formed on the buildup forming surface 7 in order to form a high-frequency circuit portion 9 having high precision and fine wiring by thin film technology. Yes. The base portion 6 has an influence on the high-frequency circuit portion 9 due to the waviness and unevenness of the first layer wiring substrate 13 and the second layer wiring substrate 14 or the unevenness due to the thickness of the second wiring pattern 20 of the second layer wiring substrate 14. give. Therefore, an insulating layer is formed on the base portion 6 so as to cover the buildup forming surface 7, and the insulating layer is subjected to a polishing process to form a planarizing insulating layer 8. Note that the planarization insulating layer 8 does not necessarily require a polishing process, and is formed by a general film formation method capable of forming a flat layer, such as a spin coat method or a curtain coat method. May be.
[0024]
The high-frequency circuit unit 9 has a three-layer structure of a first wiring layer 25 to a third wiring layer 27 each including dielectric insulating layers 25a to 27a and wiring patterns 25b to 27b, which are stacked by thin film technology. The chip 10 and the electronic component 11 described above are mounted on the electrode 29 formed on the uppermost third wiring layer 27 via 28. In the high-frequency circuit unit 9, the first wiring pattern 25b of the first wiring layer 25 and the first wiring pattern 18 and the second wiring pattern 20 of the core substrate 2 are planarized insulating layer 8 and first dielectric insulating layer 25a. Are appropriately connected through vias 30 formed through the vias.
[0025]
In the high-frequency circuit unit 9, the first wiring pattern 25b to the third wiring pattern 27b of the first wiring layer 25 to the third wiring layer 27 are connected to each other through vias 31 and 32 appropriately formed in the layers. Yes. The high-frequency circuit unit 9 includes a via 33 in which the first wiring pattern 25b of the first wiring layer 25 and the electrode 21 of the bare chip 4 are formed through the planarization insulating layer 8 and the first dielectric insulating layer 25a. Connected directly through. In the high-frequency circuit unit 9, since the first wiring layer 25 to the third wiring layer 27 are formed by thin film technology, the wiring patterns 25b to 27b can be miniaturized and correspond to the electrode 21 group of the bare chip 4. Thus, a fine via 33 is also formed.
[0026]
In the substrate device 1, as described above, the bare chip 4 built in the base portion 6 is laminated on the upper layer of the core substrate 2 without requiring a connection structure such as flip chip connection or wire bonding connection. 9 and via 33 are directly connected. Therefore, in the board device 1, the connection process is simplified and the cost is reduced, and the noise is reduced or the signal is transmitted at high speed by shortening the transmission line.
[0027]
In the high-frequency circuit unit 9, a thin film resistor 34, a thin film inductor 35, or a thin film capacitor 36 is formed in the second wiring pattern 26 b of the second wiring layer 26. Since the high-frequency circuit unit 9 forms the first wiring layer 25 to the third wiring layer 27 by thin film technology, it is possible to form these passive elements with high accuracy, and the first wiring pattern 25b to the second wiring pattern 25b. 3 wiring pattern 27b is miniaturized to achieve miniaturization.
[0028]
According to the substrate device 1 configured as described above, the bare chip 4 is built in the core substrate 2 of the base unit 6 together with the chip 10 and the electronic component 11 mounted on the surface of the high-frequency circuit unit 9. Since high-density mounting is achieved, miniaturization and multi-functionalization of wireless communication terminal devices are realized. According to the substrate device 1, since the electrode 21 of the bare chip 4 on the base portion 6 side and the high frequency circuit portion 9 are directly connected via the via 33, the connection process is not required, and the cost can be reduced. By shortening, it is possible to increase the processing speed and improve the noise resistance.
[0029]
With respect to the substrate apparatus 1 described above, the manufacturing process of the core substrate 2 will be described with reference to FIGS. As described above, a wiring board having a four-layer structure is used as the core substrate 2. However, in the following description of the manufacturing process, the core substrate 2 will be described as a double-sided substrate for the sake of simplicity. Further, the substrate device 1 is described as being manufactured one by one. For example, a plurality of large-sized core substrates are manufactured at once, and the core substrate is divided into one in the final process. You may do it.
[0030]
The core substrate 2 is an organic base material having low dielectric constant characteristics and low Tanδ characteristics, that is, excellent high frequency characteristics, such as polyphenyl ether, bismaleidotriazine, polytetrafluoroethylene, polyimide, liquid crystal polymer, polynorbornene, glass epoxy, A substrate made of phenol resin, polyolefin, ceramic, or a mixture of ceramic and organic base material is used. As the core substrate 2, an epoxy substrate having mechanical rigidity, heat resistance characteristics, and chemical resistance characteristics, which is cheaper than the above-described substrate, may be used as the substrate. Although the core substrate 2 is relatively expensive, a substrate such as a Si substrate or a glass substrate may be used.
[0031]
For example, the core substrate 2 is formed by bonding a copper foil to the main surface of the substrate and subjecting the copper foil to a photolithography process, an etching process, or the like to form the first wiring pattern 18 and the second wiring pattern 20. In addition, the core substrate 2 may be configured to form the first wiring pattern 18 and the second wiring pattern 20 by performing, for example, a photolithography process and an etching process on a resin-coated copper foil bonded by a prepreg. . The core substrate 2 is formed with through-holes by drilling or laser processing in the substrate, conductive treatment is embedded in the inner wall by plating treatment, conductive paste is embedded, and through-holes 17 and 19 are formed by covering with a plating treatment. Is done.
[0032]
In the manufacturing process of the substrate device 1, for example, press punching is performed on the core substrate 2 to form a chip loading opening 3 as shown in FIG. 2. The chip loading opening 3 has an opening size sufficient to load the bare chip 4 and may be formed in the unformed region of the first wiring pattern 18 or the second wiring pattern 20 as described above. The formation position and the opening shape are not limited. When a plurality of bare chips 4 are loaded, the chip loading opening 3 may be formed with an opening size sufficient to load each, and a plurality of chip loading openings 3 may be formed on the core substrate 2.
[0033]
In the manufacturing process of the substrate device 1, a process of bonding the core substrate 2 to the base 40 is performed. The base 40 is not particularly required to have a flat main surface, but a glass substrate or Si substrate having heat resistance, chemical resistance, or mechanical rigidity is used. In the manufacturing process of the substrate device 1, a plurality may be simultaneously manufactured on the base 40.
[0034]
A peeling layer 41 is formed on the main surface of the base 40, and the core substrate 2 is bonded onto the peeling layer 41 with the main surface 14 a of the second layer wiring substrate 14 as a bonding surface. The peeling layer 41 has a thickness of about several tens of μm by spin coating or the like on a metal thin film such as copper or aluminum formed with a thickness of about several μm by sputtering or the like, for example. Thus, it is made of a resin layer such as a polyimide resin formed into a film.
[0035]
In the manufacturing process of the substrate device 1, a process is performed in which the bare chip 4 is loaded into the chip loading opening 3 with the electrode forming surface 12 side as the loading side with respect to the core substrate 2 bonded onto the base 40. The The bare chip 4 is positioned in the chip loading opening 3 using an appropriate jig, for example, and in this state, the electrode forming surface 12 is placed on the main surface of the base 40 as shown in FIG.
[0036]
In the manufacturing process of the substrate device 1, as shown in FIG. 4, a process of forming the sealing resin layer 5 by filling and curing the insulating resin in the chip loading opening 3 loaded with the bare chip 4 is performed. The sealing resin layer 5 is integrated with the core substrate 2 in a state where the bare chip 4 is positioned in the chip loading opening 3, and a part of the sealing resin layer 5 flowing into the main surface of the base 40 is the main surface of the core substrate 2 as described above. The buildup forming surface 7 is configured in cooperation with the above.
[0037]
In the manufacturing process of the substrate device 1, a process of forming the solder resist layer 16 over the entire surface of the main surface 13 a of the first layer wiring substrate 13 of the core substrate 2 is performed. The solder resist layer 16 is subjected to patterning for forming an opening corresponding to the land of the first wiring pattern 18 by performing, for example, a photolithography process and an etching process. An electrode 15 is formed by performing an electrode forming process for performing Ni—Au plating.
[0038]
In the manufacturing process of the substrate device 1, a process of peeling the core substrate 2 from the base 40 through the peeling layer 41 is performed. In the peeling step, the base substrate 40 bonded to the core substrate 2 is immersed in an acid or alkali solution, whereby the core substrate 2 is formed into the base 40 using the metal layer and the resin layer of the peeling layer 41 as an interface as shown in FIG. Peel cleanly from. The core substrate 2 is removed by subjecting the resin layer left on the bonding surface 14a to a dry etching method using oxygen plasma, for example. The core substrate 2 is integrated with the main surface 14 a of the second layer wiring substrate 14, the electrode forming surface 12 of the bare chip 4, and a part of the sealing resin layer 5 constituting the same surface based on the main surface of the base 40. The build-up forming surface 7 is formed.
[0039]
In the manufacturing process of the substrate device 1, the step of forming the planarization insulating layer 8 as shown in FIG. 5 on the buildup forming surface 7 of the core substrate 2 in which the bare chip 4 is integrally stored through the above-described steps. Is given. As described above, the planarization insulating layer 8 is formed in order to laminate the high-precision high-frequency circuit unit 9 on the buildup forming surface 7 and does not directly affect the function of the substrate device 1. The planarization insulating layer 8 is preferably formed of the same insulating dielectric material from the viewpoint of compatibility with the dielectric insulating layer of the high-frequency circuit unit 9 and the common use of materials.
[0040]
The planarizing insulating layer 8 is an insulating dielectric material having low dielectric constant characteristics and low Tanδ characteristics, that is, excellent high frequency characteristics, such as polyphenyl ether, bismaleidotriazine, polyimide, liquid crystal polymer, polynorbornene, benzocyclobutene or epoxy. It is formed by using a resin or acrylic resin. The planarization insulating layer 8 is formed by a film forming method excellent in application uniformity and thickness controllability, for example, a spin coat method, a curtain coat method, a low recoat method or a dip coat method. After the planarization insulating layer 8 is formed by such a method, the planarization insulating layer 8 is planarized with higher accuracy by performing, for example, a polishing process using an abrasive material made of a mixed liquid of alumina and silica as necessary. .
[0041]
For the planarization insulating layer 8, for example, an insulating dielectric layer is formed so as to cover the entire surface of the second wiring pattern 20, and the chemical is applied until the second wiring pattern 20 is exposed to the insulating dielectric layer. You may make it planarize by performing a mechanical polishing process. In this case, the planarization insulating layer 8 forms a flat buildup forming surface 7 on the base portion 6 in cooperation with the second wiring pattern 20.
[0042]
In the manufacturing process of the substrate device 1, the high-frequency circuit unit is formed by thin film technology on the build-up forming surface 7 via the planarization insulating layer 8 with respect to the core substrate 2 that becomes the base unit 6 manufactured through the above-described steps. 9 is performed. In the formation process of the high-frequency circuit unit 9, the second wiring layer 26 and the third wiring layer 27 are stacked after the first wiring layer 25 is formed. The formation process of the high-frequency circuit unit 9 will be described as a representative of the first wiring layer 25 since the first to third wiring layers 25 to 27 are formed in substantially the same manner.
[0043]
The manufacturing process of the first wiring layer 25 includes a process of forming the dielectric insulating layer 25a with an insulating dielectric material and a process of forming the first wiring pattern 25b on the dielectric insulating layer 25a. In the formation process of the dielectric insulating layer 25a, the same material as the insulating dielectric material used for the planarization insulating layer 8 described above is used, and the dielectric insulating layer 25a is formed with a uniform thickness by a film forming method such as a spin coat method. Since the dielectric insulating layer 25a is formed on the buildup forming surface 7 via the planarizing insulating layer 8 as described above, the dielectric insulating layer 25a is formed with a highly accurate film thickness and flatness.
[0044]
As shown in FIG. 6, the dielectric insulating layer 25 a includes a predetermined electrode portion formed on the second wiring pattern 20 of the base portion 6 and a wiring pattern 25 b formed on the first wiring layer 25 of the high-frequency circuit portion 9. A large number of vias 30 for appropriately connecting the electrode portions are formed. The via 30 forms a via hole in the dielectric insulating layer 25a so that a predetermined electrode portion formed in the second wiring pattern 20 of the base portion 6 faces outward. When a photosensitive resin is used as the insulating dielectric material, the via hole is formed by, for example, attaching a mask having a predetermined pattern to the dielectric insulating layer 25a and performing a photolithography process, an etching process, or the like. When a non-photosensitive resin is used as an insulating dielectric material, the via hole is formed by performing a dry etching process such as a directional chemical etching method or a plasma etching method using a metal film such as a photoresist or gold as a mask, for example. The The via hole is formed in the via hole by conducting a conductive treatment on the inner wall of the hole by a plating treatment and then embedding a conductive paste and then applying a lid by the plating treatment.
[0045]
Similarly, a large number of vias 33 for appropriately connecting the second wiring pattern 20 of the base portion 6 and the electrodes 21 of the bare chip 4 are formed in the dielectric insulating layer 25a. The via 33 is formed with high accuracy corresponding to the electrode 21 formed on the bare chip 4 by the above-described method because the dielectric insulating layer 25a has a high accuracy film thickness and flatness.
[0046]
The first wiring pattern 25b is formed by, for example, forming a metal thin film 42 on the dielectric insulating layer 25a by sputtering, for example, as shown in FIG. 7, and photolithography processing, etching processing, etc. on the metal thin film 42. And forming a first wiring pattern 25b as shown in FIG. The metal thin film 42 is formed with a metal material having excellent conductivity such as Cu, Al, Pt, Au, for example. The metal thin film 42 is formed in advance through a barrier layer formed of a metal thin film of, for example, Cr, Ni, Ti or the like as a barrier layer in order to improve adhesion to the dielectric insulating layer 25a. Good.
[0047]
In the manufacturing process of the high-frequency circuit unit 9, the formation process of the second wiring layer 26 and the third wiring layer 27 is sequentially performed on the first wiring pattern 25 b of the first wiring layer 25 described above. As described above, the thin film passive elements 34 to 36 are formed in the second wiring layer 26 and the third wiring layer 27 as described above. In the manufacturing process of the high-frequency circuit unit 9, the first wiring layer 25 to the third wiring layer 27 are formed on the planarization insulating layer 8 by thin film technology, so that high-precision thin film passive elements 34 to 36 are formed. Is done.
[0048]
Hereinafter, an example of the formation process of the thin film passive elements 34 to 36 will be described. In the manufacturing process of the high-frequency circuit unit 9, a tantalum nitride (TaN) layer is formed to cover the second dielectric insulating layer 26a and the second wiring pattern 26b. The TaN layer acts as a resistor and also serves as a base of a tantalum oxide (TaO) dielectric film formed by anodic oxidation when forming a capacitor element. The TaN layer may be a Ta thin film. In the manufacturing process of the high-frequency circuit unit 9, an anodization mask layer made of a photoresist or the like having an opening that exposes the lower electrode portion of the capacitor element is formed, and the capacitor element corresponding to the opening by performing anodizing treatment The TaN layer at the lower electrode portion is selectively anodized.
[0049]
In the manufacturing process of the high-frequency circuit unit 9, the TaN + TaO layer may be patterned after anodizing the entire surface of the TaN layer without forming the anodizing mask layer. In the manufacturing process of the high-frequency circuit unit 9, the TaN layer is anodized on the surface by performing such a process, and this oxide film can be used as a protective film to stabilize the register element.
[0050]
In the manufacturing process of the high-frequency circuit unit 9, the second wiring layer 26 and the third wiring layer 27 may be formed by, for example, a copper electrolytic plating method. In the manufacturing process of the high-frequency circuit unit 9, a copper thin film layer is formed on the second dielectric insulating layer 26a or the third dielectric insulating layer 27a as an electrode for electrolytic extraction. In the manufacturing process of the high-frequency circuit unit 9, a plating resist layer having a predetermined pattern shape is formed on the copper thin film layer, and an electrolytic copper plating process is performed to lift up the copper plating layer in the pattern opening. In the manufacturing process of the high frequency circuit section 9, the plating resist layer is washed and removed, and an unnecessary copper thin film layer is removed by performing an etching process. An element is formed.
[0051]
In the manufacturing process of the high-frequency circuit unit 9, the thin film passive elements 34 to 36 are formed and formed inside the high-frequency circuit unit 9 by other appropriate methods. In the manufacturing process of the high-frequency circuit unit 9, a solder resist generally used for forming a protective layer is applied over the entire surface of the third wiring layer 27 by spin coating or the like, and as shown in FIG. Layer 28 is formed. The solder resist layer 28 is subjected to, for example, a photolithography process and an etching process to form openings corresponding to the electrode portions of the third wiring layer 27 and exposed through the openings. Electrode formation is performed, for example, by electroless Ni—Au plating or the like on the electrode portion.
[0052]
In the manufacturing process of the substrate device 1, the chip 10 and the electronic component 11 are mounted on the electrode portion of the third wiring layer 27 by an appropriate mounting method such as a flip chip method or a reflow solder method. In the manufacturing process of the substrate device 1, although not shown, a shield cover (not shown) is assembled to eliminate the influence of electromagnetic noise and the like.
[0053]
In the manufacturing process of the substrate device 1 described above, the build-up forming surface 7 is formed on the second-layer wiring board 14 side of the base portion 6 to form the high-frequency circuit portion 9 in a stacked manner. Of course, a high-frequency circuit unit may be formed in the same manner on the wiring board 15 side. In the manufacturing process of the substrate device 1, the high-frequency circuit unit 9 is formed by laminating a wiring layer having a high-precision thin film passive element and a fine wiring pattern inside by a thin film technology. It may be formed by a manufacturing process.
[0054]
In the above-described embodiment, the application example to the high-frequency circuit module substrate device mounted on the wireless transmission / reception circuit unit of the wireless communication terminal device is shown as the substrate device 1, but is not limited to the substrate device 1. Of course, the present invention is applied to various substrate apparatuses. In the substrate device 1, one bare chip 4 is accommodated in the base portion 6, but a plurality of bare chips 4 may be accommodated.
[0055]
【The invention's effect】
As described above in detail, according to the present invention, a bare chip is built in the core substrate together with a chip and an electronic component mounted on the surface, so that high density mounting can be achieved. Miniaturization and multifunctionalization can be achieved. According to the present invention, since the electrode of the built-in bare chip and the wiring pattern of the wiring layer formed on the main surface of the core substrate are directly connected via the via, a connection process is not required, so that high-speed processing and In addition to improving the anti-noise characteristic, further downsizing and thinning and cost reduction can be achieved.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of an essential part of a high-frequency circuit module substrate device shown as an embodiment of the present invention.
FIG. 2 is a plan view of an essential part of a core substrate incorporating a bare chip.
FIG. 3 is an explanatory diagram of a manufacturing process of a substrate device, showing a state where a core substrate is bonded to a base and a bare chip is loaded into a chip loading opening;
FIG. 4 shows a state in which the planarization insulating layer is formed.
FIG. 5 shows a state in which the base is formed by peeling the base from the core substrate.
FIG. 6 is an explanatory diagram of a process of forming a high-frequency circuit portion on the base portion, showing a state in which a first dielectric insulating layer is formed and a via is formed.
FIG. 7 shows a state in which a metal thin film layer is formed on the first dielectric insulating layer.
FIG. 8 shows a state in which the first wiring pattern is formed.
FIG. 9 shows a state in which a solder resist layer to be the protective layer is formed.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Board | substrate apparatus, 2 Core board | substrate, 3 Chip loading opening, 4 Bare chip, 5 Sealing resin layer, 6 Base part, 7 Buildup formation surface, 8 Planarization insulating layer, 9 High frequency circuit part, 10 chip | tip, 11 Electronic component, 12 electrode formation surface, 13 first wiring board, 14 second wiring board, 18 first wiring pattern, 25 second wiring pattern, 20 first wiring layer, 21 electrode, 26 second wiring layer, 27 second 3 wiring layers, 30 vias, 31 vias, 32 vias, 34 thin film resistors, 35 thin film inductors, 36 thin film capacitors, 40 bases, 41 release layers

Claims (12)

An appropriate wiring pattern is formed, and a core substrate in which a chip loading opening is formed in part,
And at least one bare chip built in the core substrate in which the electrode forming surface is substantially flush with the main surface by being filled in the chip loading opening and sealed with the filled sealing resin. ,
A chip characterized in that at least one wiring layer having a wiring pattern directly connected via electrodes and vias formed on the electrode forming surface of the bare chip is laminated on the main surface of the core substrate. Built-in board device. 2. The chip built-in substrate according to claim 1, wherein an insulating layer of the wiring layer formed so as to cover a main surface of the core substrate and an electrode forming surface of the bare chip is formed on a flat surface. apparatus. 2. The chip built-in substrate device according to claim 1, wherein the wiring layer has a wiring pattern formed by a thin film process. 2. The chip built-in substrate device according to claim 1, wherein a passive element is formed in the wiring layer. 2. The chip built-in substrate device according to claim 1, wherein a multi-chip module is configured by mounting a chip or a surface mount component on the uppermost wiring layer. 2. The chip built-in according to claim 1, further comprising a heat dissipating plate disposed in the chip loading opening on a main surface facing the electrode forming surface of the bare chip and sealed with the sealing resin. Board device. A substrate bonding step of bonding a core substrate in which an appropriate wiring pattern is formed and a chip loading opening is formed in part through a release layer on the main surface of the base substrate;
A chip loading step of loading at least one bare chip with the electrode formation surface facing the release layer in the chip loading opening of the core substrate;
A resin filling step of filling the chip loading opening with a sealing resin for holding the bare chip;
A substrate peeling step of peeling the core substrate formed by sealing the bare chip in the chip loading opening via the release layer after the sealing resin is cured;
At least one wiring layer having a wiring pattern that is directly connected to the electrodes formed on the electrode forming surface via vias on the main surface of the core substrate on which the electrode forming surface of the bare chip constitutes substantially the same surface And a wiring layer forming step of stacking and forming a chip-embedded substrate device. The wiring layer forming step includes an insulating layer forming step for covering the main surface of the core substrate and the electrode forming surface of the bare chip, and a flattening step for flattening the main surface of the insulating layer. The method for manufacturing a chip-embedded substrate device according to claim 7, wherein: 9. The method of manufacturing a substrate device with a built-in chip according to claim 8, wherein the wiring layer forming step is a step of forming a wiring pattern on the insulating layer by a thin film step. 10. The method of manufacturing a chip built-in substrate device according to claim 9, wherein in the wiring layer forming step, a passive element is formed on a part of the wiring pattern. 8. The method for manufacturing a chip built-in substrate device according to claim 7, further comprising a component mounting step of mounting a chip or a surface mount component on the uppermost wiring layer. Between the chip loading step and the resin filling step, a heat radiating plate loading step of loading the heat radiating plate into the chip loading opening so as to be disposed on the main surface side facing the electrode forming surface of the bare chip is performed. The method for manufacturing a chip-embedded substrate device according to claim 7.

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