JP5568170B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board applicable to a mounting board on which electronic components are mounted and a probe board for evaluating electrical characteristics of the electronic parts, and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, there are multilayer wiring boards provided with through electrodes applied to a mounting board on which electronic components are mounted and a probe board for evaluating electrical characteristics of the electronic parts. Patent Document 1 describes that a probe card used for inspecting an integrated circuit formed on a semiconductor wafer is formed from a ceramic substrate made of a non-oxide ceramic.

JP 2002-31650 A

  As will be described later in the related art section, in a silicon wiring substrate using silicon as a substrate, a through hole is formed in the silicon substrate, and after the silicon substrate is covered with an insulating layer, the through hole is electroplated. The through electrode is filled. In a silicon wiring substrate, the thickness of the substrate is set to be relatively thick in order to obtain stable handling properties. In addition, the pitch of through-holes has been reduced with the improvement in performance of electronic components.

  For this reason, since the aspect ratio of the through hole of the silicon substrate is increased, there is a problem that an unfilled through hole is generated or the plating time is increased when performing electrolytic plating.

  The present invention has been created in view of the above problems, and provides a wiring board capable of obtaining an appropriate substrate strength and forming a through electrode in a through hole of the substrate with high yield and high production efficiency, and a method for manufacturing the same. The purpose is to do.

  In order to solve the above-mentioned problems, the present invention relates to a wiring board, which is formed from a wafer, and is provided on the first substrate part with a first substrate part provided with a first through conductor part in the thickness direction. And a second substrate portion having a second through conductor portion in a thickness direction of a portion corresponding to the first through conductor portion, and penetrating through the first through conductor portion and the second through conductor portion. An electrode is constructed.

  In one preferable aspect of the present invention, the first substrate portion includes a first silicon substrate, through holes formed in the thickness direction thereof, and insulating layers formed on both surfaces of the first silicon substrate and the inner surfaces of the through holes. And the first through conductor portion formed in the through hole.

  In addition, the second substrate portion is also formed of substantially the same structure as the first substrate portion, and the second silicon portion is formed on the first silicon substrate such that the second through conductor portion is disposed on the first through conductor portion. The substrates are bonded and stacked. The first and second penetrating conductor portions arranged above and below constitute a penetrating electrode of the wiring board.

  Further, a filling resin is filled in a gap between the side surface of the through hole of the second silicon substrate and the second through conductor portion. The first silicon substrate and the second silicon substrate are bonded via an adhesive resin layer, or directly bonded based on plasma processing.

  In another preferred embodiment, the insulating layer on the upper surface side of the silicon substrate of the first substrate portion is removed to expose the silicon surface, the second substrate portion is formed of glass, and the upper surface of the first substrate portion is formed. The silicon surface on the side and the glass surface on the lower surface side of the second substrate part may be joined by anodic bonding.

  In the present invention, since the wiring substrate is configured based on the lamination of the thin first and second substrates, the aspect ratio of the through hole of the first substrate can be set small. Therefore, the occurrence of unfilled through holes when electrolytic plating is performed on the through holes TH of the first substrate can be greatly improved, and the manufacturing yield can be improved.

  Further, the electrolytic plating has a characteristic that the average plating rate increases as the through hole TH to be plated is lower in height. Therefore, by dividing and forming the through conductor portion by electrolytic plating, the plating time can be shortened compared to the related art, and the production efficiency can be improved.

  Further, since the second substrate is laminated on the thin first substrate, the strength of the substrate is reinforced and a stable handling property is obtained. In addition, since the through electrode is formed from an electroplated layer having a low electrical resistance, a wiring board having excellent electrical characteristics can be configured.

  In the wiring board of the present invention, the wafers may be laminated and then cut and applied to the mounting board, or the wiring board may be configured with the wafers laminated and applied to the probe board.

  In the wiring board of the present invention, an insulating substrate (wafer) such as silicon carbide or glass can be used as the first and second substrates in addition to a semiconductor substrate (wafer) such as silicon.

  As described above, in the wiring board of the present invention, an appropriate board strength can be obtained, and a through electrode can be formed in a through hole of the board with high yield and high production efficiency.

FIG. 1 is a cross-sectional view showing a method of manufacturing a wiring board according to the related art related to the present invention. 2A to 2E are sectional views (No. 1) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. 3A to 3C are cross-sectional views (part 2) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. 4A to 4C are cross-sectional views (No. 3) showing the method for manufacturing the wiring board (first bonding method) according to the first embodiment of the present invention. 5A to 5C are cross-sectional views showing a second bonding method in the method for manufacturing a wiring board according to the first embodiment of the present invention. FIGS. 6A to 6C are cross-sectional views showing a third bonding method in the method for manufacturing a wiring board according to the first embodiment of the present invention. 7A to 7E are cross-sectional views illustrating a fourth bonding method in the method for manufacturing the wiring board according to the first embodiment of the present invention. 8A to 8C are cross-sectional views (No. 4) showing the method for manufacturing the wiring board according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a wiring board according to a modification of the first embodiment of the present invention. FIG. 10 is a cross-sectional view showing an electronic component device configured using the wiring board according to the first embodiment of the present invention. FIG. 11 is a cross-sectional view showing a probe board configured using the wiring board according to the first embodiment of the present invention. 12A to 12D are cross-sectional views (part 1) showing the method for manufacturing the wiring board according to the second embodiment of the present invention. 13A to 13C are cross-sectional views (part 2) showing the method for manufacturing the wiring board according to the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing an electronic component device configured using the wiring board according to the second embodiment of the present invention. FIG. 15 is a cross-sectional view showing a probe board configured using the wiring board according to the second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(Related technology)
Prior to describing embodiments of the present invention, problems of related technologies related to the present invention will be described. 1A to 1E are cross-sectional views showing a method for manufacturing a wiring board according to related art. In the related art wiring board manufacturing method, as shown in FIG. 1A, first, a silicon wafer 100 having a thickness of about 400 μm is prepared. The silicon wafer 100 is obtained by grinding the back surface of a silicon wafer having a thickness of 725 μm with a grinder.

  In the related art, a silicon wafer 100 having a thickness (for example, 400 μm or more) having an appropriate substrate strength is used so as to obtain stable handling properties.

  Next, as shown in FIG. 1B, a resist (not shown) having an opening is formed on the silicon wafer 100, and the silicon wafer 100 is penetrated by anisotropic dry etching using the resist as a mask. By doing so, the through hole TH is formed. Thereafter, the resist (not shown) is removed.

  Subsequently, as shown in FIG. 1C, the silicon wafer 100 is thermally oxidized to form insulating layers 120 made of a silicon oxide layer on both surfaces of the silicon wafer 100 and the inner surface of the through hole TH.

  Next, as shown in FIG. 1 (d), the silicon wafer 100 of FIG. 1 (c) is placed on the plating power supply member 140. Further, the through electrode 160 made of a copper plating layer is filled in the through hole TH of the silicon wafer 100 by electrolytic plating using the plating power supply member 140 as a plating power supply path. Thereafter, the plating power supply member 140 is removed from the silicon wafer 100.

  At this time, when the thickness of the silicon wafer 100 is 400 μm and the diameter of the through hole TH is 60 μm, the aspect ratio of the through hole TH (silicon wafer thickness / through hole diameter) is considerably large as 6.7. .

  For this reason, as shown in FIG. 1 (e), due to the large aspect ratio of the through-hole TH, a portion that becomes a bubble without being able to enter the plating solution among a large number of the through-holes TH tends to occur. Unfilled holes UH that are not subjected to copper plating are generated.

  Further, when the through-hole 160 is filled in the through hole TH by electrolytic plating, copper plating is performed from the lower side to the upper side of the through hole TH. Therefore, when the silicon wafer 100 is thick, the plating time is considerably long. Therefore, there is a problem that the production efficiency is lowered.

  In order to increase the production efficiency, there is a method of forming a through electrode by filling the through hole TH with a conductive paste. However, since a through electrode having a low electric resistance is required when mounting a high-performance electronic component, it is difficult to use a conductive paste having a considerably higher electric resistance than the copper plating layer.

  As described above, the silicon wiring substrate of the related art has a problem that the manufacturing yield is low and the production efficiency is low, although a stable handling property is obtained with an appropriate substrate strength.

  Embodiments of the present invention described below can solve the above-described problems.

(First embodiment)
2 to 8 are cross-sectional views showing a method for manufacturing a wiring board according to the first embodiment of the present invention, FIG. 9 is a cross-sectional view showing a wiring board of a modified example, and FIG. FIG. 11 is a cross-sectional view showing the probe substrate.

  In the method of manufacturing the wiring substrate according to the first embodiment, as shown in FIG. 2A, first, a first silicon wafer 10 (first wafer substrate) having a thickness of about 200 μm is prepared. The first silicon wafer 10 is obtained by grinding the back surface of a silicon wafer having a thickness of 725 μm with a grinder.

  In the present embodiment, the thin first silicon wafer 10 having a thickness of about 200 μm is temporarily used in the manufacturing process of the wiring board. However, as will be described later, another second silicon wafer is formed on the first silicon wafer 10. Are laminated to reinforce the substrate strength.

  Next, as shown in FIG. 2B, a resist 13 having a hole-like opening 13a provided on the upper surface of the first silicon wafer 10 is formed by photolithography. Subsequently, as shown in FIG. 2C, through holes TH are formed by penetrating the first silicon wafer 10 by anisotropic dry etching (RIE or the like) through the opening 13a using the resist 13 as a mask. To do. In the present embodiment, the diameter of the through hole TH is set to about 60 μm.

Next, as shown in FIG. 2D, the first silicon wafer 10 is thermally oxidized, whereby an insulating layer 12 made of a silicon oxide layer (SiO ₂ ) is formed on both surfaces of the first silicon wafer 10 and the inner surface of the through hole TH. Form. Alternatively, the insulating layer 12 may be formed by forming a silicon oxide layer by a CVD method. Further, instead of the silicon oxide layer, a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON) may be formed as the insulating layer 12.

  Subsequently, as shown in FIG. 2 (e), the first silicon wafer 10 of FIG. 2 (d) is disposed on a plating power supply member 16 such as a copper foil. Furthermore, the first through conductor portion 20 is obtained by filling a copper plating layer or the like from the lower part to the upper part of the through hole TH of the first silicon wafer 10 by electrolytic plating using the plating power supply member 16 as a plating power supply path. Thereafter, the plating power supply member 16 is removed from the first silicon wafer 10.

  At this time, the aspect ratio (thickness of the silicon wafer (200 μm) / diameter of the through hole TH (60 μm)) of the through hole TH of the first silicon wafer 10 is 3.3, and the aspect ratio of the through hole TH of the related technology described above. It is set much smaller than the ratio (6.7).

  As a result, unlike the related art, since the plating solution stably enters a large number of through holes TH, the generation of unfilled through holes TH is greatly improved, and the yield is increased in a large number of through holes TH. The first through conductor portion 20 is often formed.

  In addition, since the thickness of the first silicon wafer 10 is about half that of the silicon wafer 100 of the related technology, the plating time can be shortened to half or less of the related technology, and the production efficiency can be improved.

  As will be described later, in the present embodiment, a metal post serving as a second through conductor portion is formed on the first through conductor portion 20 in a divided manner. Electrolytic plating has the characteristic that the average plating rate is higher when the through-hole TH is lower. Therefore, when obtaining through conductor parts with a desired height, the plating time can be greatly reduced by forming the through-conductor part in a divided manner. It can be shortened.

  In the present embodiment, it is preferable to set the thickness of the first silicon wafer 10 and the diameter of the through hole TH so that the aspect ratio of the through hole TH is 4 or less. This is because if the aspect ratio of the through hole TH exceeds 4, there is a tendency that unfilled through holes are generated or the plating time becomes long and the production efficiency is lowered.

  Next, as illustrated in FIG. 3A, a resist 15 having an opening 15 a provided on the first through conductor 20 is formed on the first silicon wafer 10 by photolithography.

  Subsequently, as shown in FIG. 3B, the first silicon wafer 10 of FIG. Further, the metal post 40a is formed by filling the opening 15a of the resist 15 with a copper plating layer or the like by electrolytic plating using the plating power supply member 16 and the first through conductor portion 20 as a plating power supply path.

  Next, as shown in FIG. 3C, the plating power supply member 16 is removed, and the resist 15 is removed to expose the metal post 40a. The metal post 40 a is formed by being electrically connected to the first through conductor portion 20. The height of the metal post 40a can be adjusted by the film thickness of the resist 15, and is set to 50 to 200 μm.

  Next, a method for laminating a second silicon wafer or glass wafer on the first silicon wafer 10 will be described. In the present embodiment, there are first to fourth bonding methods.

  4A to 4C show the first bonding method. In the first bonding method, as shown in FIG. 4A, an adhesive resin layer 18 is formed on the first silicon wafer 10 except for the metal posts 40a. The adhesive resin layer 18 is an uncured resin, and an epoxy resin, a silicone resin, a polyimide resin, or the like is used. Such a resin functions as an adhesive layer when cured by heat treatment.

  As a method for forming the adhesive resin layer 18, an uncured resin sheet is stuck on the first silicon wafer 10, and the resin sheet is processed by a laser or the like to expose the metal post 40 a. Alternatively, the adhesive resin layer 18 may be formed by sticking a resin sheet provided with an opening in advance. Further, the adhesive resin layer 18 may be formed by applying a liquid resin by printing or the like.

  As will be described later, in the first bonding method, since the adhesive resin layer 18 is fluidized around the side surface of the metal post 40a, the adhesive resin layer 18 is formed with a relatively thick film thickness (volume).

  Next, a second silicon wafer 30 (second wafer substrate) as shown in FIG. 4B is prepared. A through hole TH is formed in the second silicon wafer 30 at a portion corresponding to the metal post 40a formed in the first silicon wafer 10 of FIG. Insulating layers 32 made of a silicon oxide layer or the like are formed on both surfaces of the second silicon wafer 30 and the inner surface of the through hole TH.

  The diameter of the through hole TH of the second silicon wafer 30 is set to be slightly larger than the diameter of the metal post 40 a formed on the first silicon wafer 10. Further, the thickness of the second silicon wafer 30 is set corresponding to the height of the metal post 40 a formed on the first silicon wafer 10.

  4B and 4C, the second silicon wafer 30 is inserted with the metal post 40a formed on the first silicon wafer 10 inserted into the through hole TH of the second silicon wafer 30. Is placed on the first silicon wafer 10. Furthermore, the 2nd silicon wafer 30 is pressurized to the 1st silicon wafer 20 side in 150-300 degreeC heating atmosphere.

  At this time, as shown in FIG. 4C and a partially enlarged view showing the process, the adhesive resin layer 18 under the second silicon wafer 30 is formed on the side surface of the through hole TH of the second silicon wafer 30 and the metal post 40a. It flows and fills the gap H. The adhesive resin layer 18 functions as an adhesive layer when cured, and the first silicon wafer 10 and the second silicon wafer 30 are bonded together by the adhesive resin layer 18.

  The metal post 40a disposed in the through hole TH of the second silicon wafer 30 is bonded to the second silicon wafer 30 by the adhesive resin layer 18 filled in a ring shape around the metal post 40a. As a result, the metal post 40 a becomes the second through conductor portion 40 disposed in the through hole TH of the second silicon wafer 30. The second through conductor portion 40 provided in the second silicon wafer 30 is electrically connected to the first through conductor portion 20 and is electrically insulated from the second silicon wafer 30 by the adhesive resin layer 18 and the insulating layer 32.

  Thereby, since the substrate strength of the first silicon wafer 10 is reinforced by the second silicon wafer 30, the first silicon wafer 10 has stable handling characteristics. The first through conductor portion 20 and the second through conductor portion 40 constitute a through electrode TH.

  In this way, the first wiring member 2 is obtained by laminating the second silicon wafer 30 on the first silicon wafer 10 by the first bonding method.

  Although the adhesive resin layer 18 is formed on the first silicon wafer 10 in FIG. 4A described above, the adhesive resin layer 18 may be formed on the lower surface of the second silicon wafer 30.

  5A to 5C show a second bonding method. In the second bonding method, the adhesive resin layer 18 is prevented from flowing around the metal post 40a. As shown in FIG. 5A, first, an adhesive resin layer 18 is formed on a portion of the first silicon wafer 10 excluding the metal post 40a. At this time, the thickness of the adhesive resin layer 18 is set to be relatively thin, and the adhesive resin layer 18 is not formed in the vicinity of the metal post 40a.

  Then, the same wafer as the second silicon wafer 30 described with reference to FIG.

  Subsequently, as shown in FIGS. 5A and 5B, the metal post 40a formed on the first silicon wafer 10 is inserted into the through hole TH of the second silicon wafer 30 as in the first bonding method. In this state, the second silicon wafer 30 is placed on the first silicon wafer. Further, the adhesive resin layer 18 is cured by heating / pressurizing the first and second silicon wafers 10 and 30.

  Thereby, as shown in FIG. 5B, the second silicon wafer 30 is bonded and laminated on the first silicon wafer 10 by the adhesive resin layer 18. In the second bonding method, the adhesive resin 18 is not filled between the side surface of the through hole TH of the second silicon wafer 30 and the metal post 40a in a state where the first and second silicon wafers 10 and 30 are bonded. A ring-shaped gap H remains.

  Next, as shown in FIG. 5C, the embedded resin 19 is filled in the gap H (FIG. 5B) between the side surface of the through hole TH of the second silicon wafer 30 and the metal post 40a.

  Thereby, the second wiring member 2a having substantially the same structure as that of the wiring member 2 shown in FIG. 4C is obtained.

  6A to 6C show a third bonding method. In the third bonding method, the insulating layers 12 and 32 of the first and second silicon wafers 10 and 30 are directly bonded to each other without using an adhesive resin layer.

  As shown in FIG. 6A, the first silicon wafer 10 obtained in FIG. 3C described above and the second silicon wafer 30 described in FIG. 4B described above are prepared. Then, the insulating layer 12 of the first silicon wafer 10 and the insulating layer 32 of the second silicon wafer 30 are washed with dilute hydrofluoric acid, ozone water, or dilute hydrochloric acid, respectively.

  Further, the insulating layer 12 on the metal post 40a side of the first silicon wafer 10 is treated with plasma such as argon gas. Similarly, the insulating layer 32 on the lower surface (bonding surface) side of the second silicon wafer 30 is treated with plasma such as argon gas.

  Next, as shown in FIG. 6B, the second silicon wafer 30 is moved to the first silicon with the metal post 40 a formed on the first silicon wafer 10 inserted in the through hole TH of the second silicon wafer 30. Place on the wafer.

  Further, the second silicon wafer 30 is pressurized toward the first silicon wafer 10 in a 200 ° C. heating atmosphere. Since the insulating layer 12 of the first silicon wafer 10 and the insulating layer 32 of the second silicon wafer 30 are activated by the plasma treatment, the first and second silicon wafers 10 and 30 are joined by heating / pressurizing. .

  In the third bonding method, when bonding is performed in a vacuum atmosphere, it is not necessary to heat, and bonding can be performed only by pressing the second silicon wafer 30 to the first silicon wafer 10.

  Thereafter, as shown in FIG. 6C, the embedded resin 19 is filled in the gap H (FIG. 6B) between the side surface of the through hole TH of the second silicon wafer 30 and the metal post 40a.

  In this way, the third wiring member 2b including the through electrode TE constituted by the first and second through conductor portions 20 and 40 is obtained by the third adhesion method.

  7A to 7E show the fourth bonding method. In the fourth bonding method, a glass wafer is bonded on the first silicon wafer 10 by anodic bonding instead of the second silicon wafer 30.

  As shown in FIG. 7A, first, the first silicon wafer 10 obtained in FIG. 3C described above is prepared. Further, as shown in FIG. 7B, the insulating layer 12 on the upper surface side of the first silicon wafer 10 is removed by a dry etching process or the like to expose the silicon surface. The insulating layer 12 (silicon oxide layer or the like) on the upper surface side is selectively etched with respect to the metal post 40a (copper) and the first silicon wafer 10 by dry etching using a fluorine-based gas.

  Next, as shown in FIG. 7C, a glass wafer 33 having a through hole TH in a portion corresponding to the metal post 40a formed on the first silicon wafer 10 in FIG. 7B is prepared. The glass wafer 33 has the same size as the second silicon wafer 30 in FIG. 4B described above, and is provided with a through hole TH at the same position. Borosilicate glass is preferably used as the glass wafer 33.

  Then, as shown in FIGS. 7C and 7D, the glass wafer 33 is placed in the first state with the metal post 40a formed on the first silicon wafer 10 being inserted into the through hole TH of the glass wafer 33. It is arranged on the silicon wafer 10. At this time, the silicon surface on the upper surface side of the first silicon wafer 10 contacts the glass surface on the lower surface side of the glass wafer 33.

  Thereby, the silicon surface on the upper surface side of the first silicon wafer 10 and the glass surface on the lower surface side of the glass wafer 33 can be bonded by anodic bonding.

  As conditions for the anodic bonding, for example, a voltage of 500 V to 1 KV is applied between the first silicon wafer 10 and the glass wafer 33 while being heated to 300 to 400 ° C. At this time, the first silicon wafer 10 becomes an anode and the glass wafer 33 becomes a cathode. As a result, as shown in FIG. 7 (d), a large electrostatic attraction is generated between the first silicon wafer 10 and the glass wafer 33, and they are bonded by chemical bonding at their interface.

  Next, as shown in FIG. 7E, the embedded resin 19 is filled into the gap H (FIG. 7D) between the side surface of the through hole TH of the glass wafer 33 and the metal post 40a.

  In this manner, the glass wafer 33 is bonded onto the first silicon wafer 10, and the fourth wiring member 2c having the through electrode TE constituted by the first and second through conductor portions 20 and 40 is obtained. .

  In the subsequent process, the first wiring member 2 obtained by the first bonding method described above will be described as an example. As shown in FIG. 8A, the wiring layer 50 connected to the second through conductor 40 is formed on the upper surface of the second silicon wafer 30 of the first wiring member 2 of FIG. 4C described above.

  The wiring layer 50 is formed by, for example, a semi-additive method. More specifically, first, a seed layer (not shown) is formed on the second silicon wafer 30. Next, a plating resist (not shown) provided with an opening in a portion where the wiring layer 50 is disposed is formed.

  Subsequently, a metal pattern layer (not shown) is formed in the opening of the plating resist by electrolytic plating using the seed layer as a plating power feeding path. Further, after removing the plating resist, the wiring layer 50 is obtained by etching the seed layer using the metal pattern layer as a mask.

  Further, the wiring layer 52 connected to the first through conductor portion 20 is formed on the lower surface of the first silicon wafer 10 by a similar method.

  Next, as shown in FIG. 8B, the protective insulating layer 54 in which openings 54 a are provided on the connection portions of the wiring layers 50 and 52 on the lower surface of the first silicon wafer 10 and the upper surface of the second silicon wafer 30. (Solder resist etc.) is formed respectively. Further, if necessary, a contact layer is provided by forming a Ni / Au plating layer or the like at the connection portion of the wiring layers 50 and 52.

Further, as shown in FIG. 8C, a bump electrode 56 is formed by mounting a solder ball on the connection portion of the wiring layer 50 on the upper surface side. Further, the external connection terminal 58 is formed by mounting a solder ball on the connection portion of the wiring layer 52 on the lower surface side. Thereafter, the first and second silicon wafers 10 and 30 are cut to obtain individual first terminals. The second silicon substrates 11 and 31 are separated. Thereby, the wiring board 1 of 1st Embodiment is obtained. The timing of cutting the first and second silicon wafers 10 and 30 may be before the bump electrodes 56 and the external connection terminals 58 are provided.

  In the present embodiment, an example in which two silicon wafers are stacked has been described. However, the process of bonding the second silicon wafer 30 from the process of forming the metal post 40a (FIG. 3A in the first bonding method). By repeating FIG. 4C), an arbitrary number of silicon wafers of n layers (n is an integer of 1 or more) can be stacked on the first silicon wafer 10 to constitute a wiring board.

  As shown in FIG. 8C, the wiring board 1 of the first embodiment is basically configured by bonding the second substrate portion 5b with the adhesive resin layer 18 on the first substrate portion 5a.

  The first substrate portion 5a includes a first silicon substrate 11 formed from a wafer, a through hole TH penetrating in the thickness direction, and an insulating layer 12 formed on both surfaces of the first silicon substrate 11 and the inner surface of the through hole TH. And a first through conductor portion 20 filled in the through hole TH.

  Similarly, the second substrate portion 5b is formed on the second silicon substrate 31 formed from the wafer, the through hole TH penetrating in the thickness direction, both surfaces of the second silicon substrate 31, and the inner surface of the through hole TH. And the second through conductor portion 40 filled in the through hole TH.

  An adhesive resin layer 18 (embedded resin) is filled in a gap between the insulating layer 32 formed on the inner surface of the through hole TH of the second silicon substrate 31 and the second through conductor portion 40.

  The second through conductor portion 40 is formed on the first through conductor portion 20 in an electrically connected state. The first through conductor portion 20 and the second through conductor portion 40 arranged above and below form a through electrode TE that penetrates the wiring board 1.

  Furthermore, a wiring layer 50 connected to the second through conductor portion 40 is formed on the upper surface side of the second substrate portion 5b. A wiring layer 52 connected to the first through conductor portion 20 is formed on the lower surface side of the first substrate portion 5a.

Further, protective insulating layers 54 each having an opening 54a are formed on the connection portions of the wiring layers 50 and 52 on the lower surface side of the first substrate portion 5a and the upper surface side of the second substrate portion 5b. Further, external connection terminals 58 connected to the wiring layer 52 are provided on the lower surface side of the first substrate portion 5a.
A bump electrode 56 connected to the wiring layer 50 is provided on the upper surface side of the second substrate portion 5b.

  When the third bonding method described above (FIGS. 6A to 6C) is adopted, the wiring board 1 shown in FIG. 8C has a space between the first substrate portion 5a and the second substrate portion 5b. The adhesive resin layer 18 is omitted. Then, the insulating layers 12 and 32 of the first and second substrate portions 5a and 5b are directly joined.

  When the above-described fourth bonding method (FIGS. 7A to 7E) is employed, the second substrate portion 5b of the wiring substrate 1 in FIG. 8C is replaced with the second silicon substrate 31. A glass substrate is used, and the insulating layer 12 on the upper surface, the lower surface, and the inner surface of the through hole TH is omitted, and the insulating layer 12 on the upper surface side of the first substrate portion 5a is omitted. Then, the glass surface on the lower surface side of the second substrate portion 5b (glass substrate) is bonded to the silicon surface on the upper surface side of the first substrate portion 5a by anodic bonding.

  Since the wiring substrate 1 of the first embodiment is manufactured based on the lamination of the thin first and second silicon wafers 10 and 30, the through hole of the first silicon wafer 10 to be plated in the manufacturing process. The aspect ratio of TH can be set small.

  Therefore, it is possible to greatly improve the generation of unfilled through holes TH when plating is performed on the through holes TH of the first silicon wafer 10, so that the manufacturing yield can be improved.

  Moreover, since the height of the through hole TH of the first silicon wafer 10 to be plated is also reduced, the plating time can be shortened and the production efficiency can be improved.

  In addition, since the second silicon substrate 31 is laminated on the thin first silicon substrate 11, the substrate strength is reinforced and stable handling is obtained. And since the penetration electrode TE is formed from the electroplating layer with low electrical resistance, the wiring board 1 excellent in the electrical property can be comprised rather than the case where an electrically conductive paste is used.

  In the present embodiment, the first and second substrate portions 5a and 5b have been described by taking silicon as an example, but a semiconductor substrate (wafer) such as gallium arsenide (GaAs) other than silicon may be used. Even when a semiconductor substrate other than silicon is used, the wiring substrate can be configured with the same structure as in FIG.

  Alternatively, an insulating substrate (wafer) such as silicon carbide (SiC) or glass may be used as the substrate of the first and second substrate portions 5a and 5b. FIG. 9 shows a modified wiring board 1a using an insulating substrate.

  In the wiring substrate 1a of the modified example, the first and second insulating substrates 11a and 31a are replaced by the adhesive resin layer 18 instead of the first and second silicon substrates 11 and 31 in the wiring substrate 1 of FIG. Bonded and laminated. It is not necessary to form insulating layers on both surfaces of the first and second insulating substrates 11a and 31a and the inner surface of the through hole TH.

  The first and second insulating substrates 11a and 31a are bonded by the adhesive resin layer 18, and the adhesive resin layer 18 (buried in the gap between the side surface of the through hole TH of the second insulating substrate 31a and the second through conductor portion 40 is also provided. Filling resin).

When a SiC wafer is used, a through hole is formed by drilling or the like, and when a glass wafer is used, a through hole is formed by a sandblast method or the like.
In FIG. 9, the other elements are the same as those shown in FIG.

  The wiring board 1 (FIG. 8C) of this embodiment is used as a mounting board for mounting electronic components. As shown in FIG. 10, the connection part of the electronic component 60 (semiconductor chip or the like) is flip-chip connected to the bump electrode 56 on the upper surface side of the wiring board 1 in FIG. As a result, the electronic component 60 is connected to the wiring board 1 by the connection electrode 57. Further, the underfill resin 62 is filled in the gap below the electronic component 60.

  Thereby, the electronic component device 3 of the first embodiment is obtained.

  FIG. 11 shows an example in which the wiring board of the first embodiment is applied to a probe board. As shown in FIG. 11, the probe substrate 4 of this embodiment is used for evaluating the electrical characteristics of a silicon wafer in which an integrated circuit is formed in each chip region.

  Probe pins 59 are attached to the wiring layer 50 on the upper surface of the wiring substrate in the wafer state shown in FIG. Further, external connection terminals 58 are provided on the wiring layer 52 on the lower surface side of the wiring substrate in the wafer state.

  Then, the external connection terminals 58 on the lower surface side of the probe substrate 4 are connected to a test board (not shown) or the like, and the connection pads of each chip region of the silicon wafer are connected to the probe pins 59 on the upper surface side of the probe substrate 4 for integration. The electrical characteristics of the silicon wafer provided with the circuit are evaluated.

(Second Embodiment)
12 and 13 are cross-sectional views showing a method of manufacturing a wiring board according to a second embodiment of the present invention, FIG. 14 is a cross-sectional view showing the electronic component device, and FIG. 15 is a cross-sectional view showing the probe substrate.

  The feature of the second embodiment is that a through silicon conductor is formed in a through hole of the second silicon wafer after the second silicon wafer is laminated on the first silicon wafer. In the second embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  In the method of manufacturing the wiring board of the second embodiment, as shown in FIG. 12A, first, the first silicon wafer is obtained by performing the steps of FIGS. 2A to 2E of the first embodiment. The first through conductor portion 20 is formed in the through hole TH of the 10 (first wafer substrate). The thickness of the first silicon wafer 10 is about 200 μm as in the first embodiment.

  Next, as shown in FIG. 12B, the adhesive resin layer 18 is formed on the portion of the first silicon wafer 10 excluding the first through conductor portion 20. Further, a second silicon wafer 30 (second wafer substrate) as shown in FIG. The second silicon wafer 30 is provided with through holes TH, and an insulating layer 32 is formed on both surfaces of the second silicon wafer 30 and the inner surface of the through hole TH.

  The through hole TH of the second silicon wafer 30 is arranged corresponding to the first through conductor portion 20 formed in the first silicon wafer 10. The thickness of the second silicon wafer 30 is set to 100 to 200 μm.

  In the second embodiment, since the through conductor portion is also formed by electrolytic plating in the through hole TH of the second silicon wafer 30, the aspect ratio of the through hole TH of the second silicon wafer 30 is the same as that of the first silicon wafer 10. Is preferably set to 4 or less.

  Then, as shown in FIGS. 12C and 12D, the second silicon wafer 30 is arranged such that the through hole TH of the second silicon wafer 30 is disposed on the first through conductor portion 20 of the second silicon wafer 30. A wafer 30 is placed on the first silicon wafer 10. Further, similarly to the first embodiment, the second silicon wafer 30 is bonded to the first silicon wafer 10 by curing the adhesive resin layer 18 by heating / pressing.

  Note that the insulating layer 12 formed on the first silicon wafer 10 and the second silicon wafer 30 were formed without using the adhesive resin layer 18 as in the third bonding method described in the first embodiment. It is also possible to join the insulating layer 32 based on performing plasma treatment.

  Alternatively, as in the fourth bonding method described in the first embodiment, the insulating layer 32 on the upper surface side of the first silicon wafer 10 is removed to expose the silicon surface, and glass is used instead of the second silicon wafer 30. A wafer may be used to anodically bond the silicon surface of the first silicon wafer 10 and the lower surface of the glass wafer.

  Next, as shown in FIG. 13A, the structure of FIG. 12D is disposed on the plating power supply member 16. Further, the second through conductor portion 40 is formed in the through hole TH of the second silicon wafer 30 by electrolytic plating using the plating power supply member 16 and the first through conductor portion 20 as a plating power supply path. Thereafter, the plating power supply member 16 is removed from the first and second silicon wafers 10 and 30.

  The second through conductor portion 40 is formed by being electrically connected to the first through conductor portion 20 therebelow. Also in the second silicon wafer 30, the thickness is set as thin as about 200 μm and the aspect ratio of the through hole TH is set as small as 4 or less, so that an unfilled through hole TH is generated or the plating time is increased. The problem is solved.

  This is because, as described in the first embodiment, the average plating rate is higher when the first and second through conductor portions 20 and 40 are divided and plated than when they are continuously formed by electrolytic plating.

  Subsequently, as shown in FIG. 13B, a wiring layer 50 connected to the second through conductor portion 40 is formed on the upper surface of the second silicon wafer 30 as in the first embodiment. Further, a wiring layer 52 connected to the first through conductor portion 20 is formed on the lower surface of the first silicon wafer 10.

  Thereafter, protective insulating layers 54 having openings provided on the connection portions of the wiring layers 50 and 52 are formed on the lower surface of the first silicon wafer 10 and the upper surface of the second silicon wafer 30, respectively.

  Next, as shown in FIG. 13C, bump electrodes 56 are formed on the wiring layer 50 on the upper surface side of the second silicon wafer 30 as in the first embodiment. Further, external connection terminals 58 are formed on the wiring layer 52 on the lower surface side of the first silicon wafer 10.

  Thereafter, the first and second silicon wafers 10 and 30 are cut to be separated into individual first and second silicon substrates 11 and 31.

  Thereby, the wiring board 1b of 2nd Embodiment is obtained.

  As shown in FIG. 13C, the wiring substrate 1b of the second embodiment is basically configured by bonding the second substrate portion 5b with the adhesive resin layer 18 on the first substrate portion 5a. As in the first embodiment, the first substrate portion 5a is filled with the first silicon substrate 11, the through hole TH, the insulating layer 12 formed on both surfaces and the inner surface of the through hole TH, and the through hole TH. The first through conductor portion 20 is provided.

  Similarly, the second substrate portion 5b includes the second silicon substrate 31, the through hole TH, the insulating layer 32 formed on both surfaces and the inner surface of the through hole TH, and the second through hole filled in the through hole TH. The conductor part 40 is provided.

  As in the first embodiment, the first and second through conductor portions 20 and 40 arranged above and below constitute the through electrode TE penetrating the wiring board 1b.

  In the second embodiment, no embedded resin is formed between the side surface of the through hole TH of the second silicon substrate 31 and the second through conductor portion 40, and the second through conductor portion 40 is 2 It is electrically insulated from the silicon substrate 31.

  Since other elements are the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted.

  Also in the wiring substrate 1b of the second embodiment, as with the wiring substrate 1 of the first embodiment, the substrate strength is reinforced and stable handling is obtained, and the through electrode TE (first electrode) is produced with high yield and high production efficiency. 1 and the 2nd penetration conductor parts 20 and 40) are formed. Furthermore, the through electrode TE having a low electric resistance can be formed by electrolytic plating.

  Also in the second embodiment, similarly to the first embodiment, a semiconductor substrate other than silicon, or an insulating substrate such as SiC or glass may be used instead of the first and second silicon substrates 11 and 31. Good.

  The wiring board 1b of the second embodiment is used as a mounting board for mounting electronic components, as in the first embodiment. As shown in FIG. 14, the connection part of the electronic component 60 (semiconductor chip or the like) is flip-chip connected to the bump electrode 56 on the upper surface side of the wiring board 1 b of FIG. 13C, and the electronic component 60 is wired by the connection electrode 57. Connected to the substrate 1b.

  Further, the underfill resin 62 is filled in the gap below the electronic component 60. Thereby, the electronic component device 3a of the second embodiment is obtained.

  As shown in FIG. 15, the wiring board of the second embodiment may be applied to the probe board as in the first embodiment. As shown in FIG. 15, in the probe substrate 4a of the second embodiment, probe pins 59 are attached to the wiring layer 50 on the upper surface of the wiring substrate in the wafer state of FIG. 13B described above.

  Further, external connection terminals 58 are provided on the wiring layer 52 on the lower surface side of the wiring substrate in the wafer state. Then, as in the first embodiment, the electrical characteristics of the silicon wafer provided with the integrated circuit are evaluated.

DESCRIPTION OF SYMBOLS 1, 1a, 1b ... Wiring board, 2, 2a, 2b, 2c ... Wiring member, 3, 3a ... Electronic component apparatus, 4, 4a ... Probe board, 5a ... 1st board | substrate part, 5b ... 2nd board | substrate part, 10 ... 1st silicon wafer, 11 ... 1st silicon substrate, 12, 32, 34 ... Insulating layer, 11a ... 1st insulating substrate, 13, 15 ... Resist, 13a, 15a, 34a, 54a ... Opening, 16 ... Plating Power feeding member, 18 ... adhesive resin layer, 19 ... embedded resin, 20 ... first through conductor, 30 ... second silicon wafer, 31 ... second silicon substrate, 31a ... second insulating substrate, 33 ... glass wafer, 40a ... metal post, 40 ... second through conductor portion, 50, 52 ... wiring layer, 54 ... protective insulating layer, 56 ... bump electrode, 57 ... connection electrode, 58 ... external connection terminal, 59 ... probe pin, H ... gap , TE ... through electrode, TH ... through Hall.

Claims (8)

A first silicon substrate comprising a first through hole and a first through conductor portion formed in the first through hole, and formed from a wafer;
A second through hole formed on the first silicon substrate, and a second through conductor formed in alignment with the first through conductor in the second through hole, formed from a wafer. A second silicon substrate formed;
A first insulating layer formed on both surfaces of the first silicon substrate and on the inner surface of the first through hole;
Having both surfaces of the second silicon substrate and a second insulating layer formed on the inner surface of the second through hole;
The first insulating layer on the upper surface side of the first silicon substrate and the second insulating layer on the lower surface side of the second silicon substrate are directly joined, and the inner surface of the second through hole and the second through conductor portion An adhesive resin layer is formed between
A wiring board, wherein a through electrode is integrally formed by the first through conductor portion and the second through conductor portion. A bump electrode is formed on the upper surface of the second silicon substrate on the second through conductor portion via a wiring layer,
2. The wiring board according to claim 1, wherein an external connection terminal is formed on the lower surface of the first silicon substrate on the first through conductor portion via a wiring layer. A silicon substrate comprising a first through hole and a first through conductor portion formed in the first through hole, and formed from a wafer;
Layered on the silicon substrate, comprising a second through hole, and a second through conductor portion formed in alignment with the first through conductor portion in the second through hole, and formed from a wafer A glass substrate;
An insulating layer formed on a lower surface of the silicon substrate and an inner surface of the first through hole;
The silicon surface on the upper surface side of the silicon substrate and the lower surface of the glass substrate are directly bonded, and an adhesive resin layer is formed between the inner surface of the second through hole and the second through conductor portion. ,
A wiring board, wherein a through electrode is integrally formed by the first through conductor portion and the second through conductor portion. A bump electrode is formed on the upper surface of the glass substrate via a wiring layer on the second through conductor portion,
The wiring board according to claim 3, wherein an external connection terminal is formed on the lower surface of the silicon substrate on the first through conductor via a wiring layer. Forming a first through hole penetrating in a thickness direction in the first silicon wafer;
Forming a first insulating layer on both surfaces of the first silicon wafer and on the inner surface of the first through hole;
Forming a through conductor portion in the first through hole by electrolytic plating;
Forming a metal post on the through conductor by electrolytic plating;
A second silicon wafer having a second through hole corresponding to the metal post and a second insulating layer formed on both surfaces and the inner surface of the second through hole is prepared, and the metal is provided in the second through hole. Directly bonding the first insulating layer on the upper surface side of the first silicon wafer and the second insulating layer on the lower surface side of the second silicon wafer with the post inserted;
And a step of filling an adhesive resin layer into a gap between the inner surface of the second through hole and the metal post. After the step of filling the adhesive resin layer,
Forming a bump electrode on the upper surface of the second silicon wafer on the metal post via a wiring layer;
6. The method of manufacturing a wiring board according to claim 5, further comprising a step of forming an external connection terminal on the bottom surface of the first silicon wafer via the wiring layer on the through conductor portion . Forming a first through hole penetrating in a thickness direction in a silicon wafer;
Forming an insulating layer on both sides of the silicon wafer and on the inner surface of the first through hole;
Forming a through conductor portion in the first through hole by electrolytic plating;
Forming a metal post on the through conductor by electrolytic plating;
Removing the insulating layer on the upper surface side of the silicon wafer to expose the silicon surface;
A glass wafer provided with a second through hole corresponding to the metal post is prepared, and the silicon surface on the upper surface side of the silicon wafer is inserted into the second through hole, and the glass substrate Directly joining the lower surface;
And a step of filling an adhesive resin layer in a gap between the inner surface of the second through hole and the metal post. After the step of filling the adhesive resin layer,
Forming a bump electrode on the upper surface of the glass wafer via a wiring layer on the metal post ; and
The method for manufacturing a wiring board according to claim 7, further comprising: forming an external connection terminal on the lower surface of the silicon wafer on the through conductor portion via a wiring layer.

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