1353030 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶圓之銅塾表面鐘錫方法，特別是關於 一種藉由在一晶圓之銅墊的上方穿過一金屬薄層形成一層緊 密結合之錫層，以供直接做為或選擇接合更小尺寸金屬凸塊的 晶圓之銅塾表面鍵錫方法。 【先前技術】 近年來’咼效能、南積集度、低成本、輕薄短小一直為長 久以來電子產品設計製造上所追尋之目標。為了達成上述目 標’積體電路封裝技術也跟著朝向微型化、高密度化發展，其 中常見的封裝技術包含雙列直插式封裝ipual blhe Package ’ DIP)、四方扁平封裝(Qua(j Fiat pack，qfp)、四方形 扁平無引腳封裝(Quad Flat No-lead，QFN)、針腳陣列式構裝 (Pin Grid Array ’ PGA)、球格陣列式構裝(Bau Grid ，BGA) 及晶片尺寸級構裝(Chip-Scale Package ’ CSP)等。以BGA或 PGA封裝構造為例，其係在一多層電路基板之上表面利用打 線技術(Wire Bonding，WB)或覆晶技術(Fiip chip，FC)固設至 少一晶片，並在其下表面固設數個銲球(s〇lderball)。特別是， 由於BGA或PGA封裝構造能以堆疊(stack die)方式或鄰接 (side-by-side)方式進一步整合數個晶片於同一封裝體中，因此 有利於構成具多功能的系統級封裝(SyStem^package，gjjp)， (s ) 5 1353030 , 是以成為近年來發展迅速之晶片構裝技術。另一方面，CSP封 裝構造則是能整合數個晶片至同一晶片中，以構成具多功能的 系統單晶月封裝(System On Chip，SOC)，故亦為發展迅速之 另一晶片構裝技術。如上所述，不論是BGA、PGA或CSP等 先進封裝技術皆會使用到覆晶技術(FlipChip，FC；|，以便在一 晶片之下表面固設數個凸塊(s〇lder bump)。因此，覆晶技術亦 成為先進封裝技術成敗與否之關鍵因素之一。 舉例而言，中華民國專利公告第5214〇6號則公開一種「凸 塊形成製程」，其包含下列步驟··提供一晶圓，具有數個銲墊； 於該晶圓之表面依序形成—黏著層、—轉層及—沾錫層，·定 義該沾錫;|及雜_，_成複數棘底金·卿聊 案，並暴露出該黏著層；形成數個鲜料層圖案於該球底金屬層 圖案之表面；去除暴露出之該黏著層；以及進行回焊使各該銲 料層圖案形成-凸塊。上述黏著層材f選自鉻、銅、銘、欽其 中之-；上述阻障層材質選自鈦鶴合金、欽、錄飢合金、絡銅 合金其中之-，及上述沾錫層材質選自銅、鎳、免、金、銀及 銘其中之-。在製程完成後，該晶圓之銲塾_)上依序存在 該黏著層、阻障層、沾錫層及簡凸塊之叠層 再者，令華民國專利公告第仍㈣號則公開一種「晶圓 級封裝之凸塊製造方法」，其包含下列步驟：提供一晶圓，其 上形成數條蝴道、’護層及數個銲墊；形成—導電層於該 1353030 曰B圓上’該導電層與該銲墊電性連接並填入該切割道；形成— 光阻層於該導電層上；圖案化該光阻層於該銲墊上方形成數個 路出該導電層之開口，並於銲墊以外之區域形成數個未露出該 導電層之開口；以及形成數個凸塊於該些銲墊上方之該些開口 以連接該導電層。上述導電層之材質係選自鈦、鈦鎢合金、鋁、 錄銳合金、鎳、銅及鉻的其中之一；或是，鈦/鎳釩合金/銅或 鋁/鎳釩合金/鋼之三層結構；或為欽/銅二層結構，亦可為鋁/ 鈦/錦銳合金/鋼之四層結構。在製程完成後，該晶圓之銲墊(叙 塾)上依序存在該導電層(一至四層)及銲料凸塊之疊層構造。 另外’令華民國專利公告第1283433號則公開一種「降低 晶圓上金屬凸塊表面粗糙度之方法」，其包含下列步驟：提供 一晶圓，具有一主動面；形成一金屬層於該晶圓之該主動面； 形成一光阻層於該金屬層’該光阻層係形成有數個開口以顯露 該金屬層；形成數個金屬凸塊於該光阻層之開口，該金屬凸塊 係具有數個顯露於該光阻層之接合面；研磨該金屬凸塊之接合 面，以降低其表面粗糙度；在研磨之後，移除該光阻層；以及 在移除該光阻層之後，蝕刻該金屬凸塊，以消除該接合面之研 磨痕跡。上述金屬層係選自單一金屬或合金組成之複合金屬 層，亦即UBM結構。在製程完成後，該晶圓之銲墊(鋁墊)上 依序存在該金屬層(單一層或複合層)及銲料凸塊之疊層構造。 除此之外’相關於覆晶(Flip Chip，FC)及凸塊底金屬層1353030 IX. Description of the Invention: [Technical Field] The present invention relates to a method for forming a copper beryllium surface on a wafer, and more particularly to forming a thin layer of metal through a metal pad over a wafer. A layer of tightly bonded tin layer for direct or selective bonding of copper-germanium surface bond tins to wafers of smaller size metal bumps. [Prior Art] In recent years, 'efficiency, south concentration, low cost, light weight and shortness have been the goals pursued for the long time in the design and manufacture of electronic products. In order to achieve the above goal, 'integrated circuit packaging technology is also moving towards miniaturization and high density. Common packaging technologies include dual-in-line package ipual blhe Package ' DIP) and quad flat package (Qua (j Fiat pack, Qfp), Quad Flat No-lead (QFN), Pin Grid Array 'PGA, Bau Grid (BGA) and wafer size (Chip-Scale Package 'CSP), etc. Take the BGA or PGA package structure as an example. It uses Wire Bonding (WB) or Flip Chip (FC) on the surface of a multi-layer circuit board. Fixing at least one wafer and fixing a plurality of solder balls on the lower surface thereof. In particular, since the BGA or PGA package structure can be stacked or stacked in a side-by-side manner Further integration of several wafers in the same package facilitates the formation of a multi-functional system-in-package (SyStem package, gjjp), (s) 5 1353030, which is a rapidly growing wafer assembly technology in recent years. On the one hand, the CSP package structure is able to Integrating several wafers into the same wafer to form a multi-functional system on-chip (SOC), it is also a rapidly growing wafer fabrication technology. As mentioned above, whether it is BGA or PGA. Or advanced packaging technologies such as CSP will use flip chip technology (FlipChip, FC; |, in order to fix a number of bumps on the surface of a wafer. Therefore, flip chip technology has become an advanced packaging technology. For example, the Republic of China Patent Publication No. 5214-6 discloses a "bump forming process" which includes the following steps: providing a wafer having a plurality of pads; The surface of the wafer is sequentially formed - an adhesive layer, a transfer layer, and a tin-plated layer, defining the dip tin; and the miscellaneous _, _ into a plurality of spines, and revealing the adhesive layer; Forming a plurality of fresh material layers on the surface of the bottom metal layer pattern; removing the exposed adhesive layer; and performing reflow soldering to form the solder layer to form a bump. The adhesive layer f is selected from the group consisting of chromium and copper. , Ming, Qin, among them; the above barrier material is selected from titanium Among the alloys of He alloy, Qin, recorded hunger alloy and copper alloy, and the above-mentioned tin-plated material is selected from the group consisting of copper, nickel, nickel, silver and silver. After the process is completed, the wafer is soldered. _) The stack of the adhesive layer, the barrier layer, the tin-plated layer and the simple bump is sequentially present, and the Republic of China Patent Publication No. (4) discloses a "bump-level package bump manufacturing method". The method comprises the steps of: providing a wafer on which a plurality of wafers, a protective layer and a plurality of solder pads are formed; forming a conductive layer on the 1353030 曰B circle. The conductive layer is electrically connected to the soldering pad And filling the dicing circuit; forming a photoresist layer on the conductive layer; patterning the photoresist layer to form a plurality of openings above the soldering pad to form the conductive layer, and forming a plurality of regions outside the bonding pad The opening of the conductive layer is not exposed; and the plurality of bumps are formed on the openings above the pads to connect the conductive layer. The material of the conductive layer is selected from one of titanium, titanium tungsten alloy, aluminum, recording alloy, nickel, copper and chromium; or titanium/nickel vanadium alloy/copper or aluminum/nickel vanadium alloy/steel The layer structure; or a Qin/Copper two-layer structure, or a four-layer structure of aluminum/titanium/cone/alloy/steel. After the process is completed, the conductive pads (one to four layers) and the solder bumps are laminated on the pads of the wafer. In addition, the method of reducing the surface roughness of a metal bump on a wafer is disclosed in the following method: providing a wafer having an active surface; forming a metal layer on the crystal Forming a photoresist layer on the metal layer 'the photoresist layer is formed with a plurality of openings to expose the metal layer; forming a plurality of metal bumps in the opening of the photoresist layer, the metal bump system Having a plurality of bonding surfaces exposed to the photoresist layer; grinding a bonding surface of the metal bump to reduce surface roughness thereof; removing the photoresist layer after polishing; and after removing the photoresist layer, The metal bump is etched to eliminate the abrasive trace of the joint. The above metal layer is selected from a composite metal layer composed of a single metal or alloy, that is, a UBM structure. After the process is completed, the metal pad (single layer or composite layer) and the solder bump are laminated on the pad (aluminum pad) of the wafer. In addition to 'Flip Chip (FC) and bump bottom metal layer
7 1353030 (Under Bump Metallurgy，UBM)之先前技術尚有中華民國專利 公告第5%293號「凸塊製程」、第1221334號「凸塊製程」、 第1225698號「晶圓級封裝凸塊製程」及第1239578號「凸塊 製程」等。在製程完成後，該晶圓之銲墊(銘塾)上依序亦皆存 在該凸塊底金屬層(複合層)及銲料凸塊之疊層構造。 另一方面，相對應於封裝技術之發展，半導體晶圓製程技 術亦朝微小化邁進。特別是’在0.13微米級晶圓技術進展至 90奈米級晶圓技術期間，銘製程將逐漸被銅製程取代，以往 晶圓表面上所形成之鋁墊(A1 pad)突然變成銅墊(Cupad)。此種 先進製程趨勢的演變立刻面臨到一技術問題，亦即這使得原本 應用於晶圓鋁墊之各種習用凸塊底金屬層（Under Bump Metallurgy ’ UBM)因金屬冶金相容性問題而不再完全適用於下 一世代的晶圓銅墊上。再者，由於上述習用凸塊底金屬層通常 需要複數金屬層’因此導致其製程較為繁複，且生產成本亦相 對較尚。另外，亦有必要思考要藉由何種先進技術，以進一步 縮小晶圓銅墊上之凸塊尺寸，以便相對減少凸塊間距，藉此提 高覆晶晶片在單位面積中可佈局之凸塊總量。 疋故，確實有必要提供一種晶圓之銅墊表面鐘錫方法，以 解決習知技術所存在的缺陷。 【發明内容】 本發明之主要目的在於提供—種晶圓之雜表面鍵錫方 8 法，其係在一晶圓上暫時全面性形成一半透性之金屬薄層，並 選擇利用化學浸鍍之方式穿過該金屬薄層形成一錫層於銅墊 上方’進而簡化凸塊製程/構造及降低製程成本。 本發明之次要目的在於提供一種晶圓之銅墊表面鍍錫方 法’其係將該金屬薄層裸露之銅墊部份表面選擇以化學浸鍵方 式置換成-錫層，因而得到緊密結合於銅塾表面之錫層，進而 增加凸塊結合強度。 本發明之另-目的在於提供—種晶圓之銅録面鑛錫方 法’其係在-晶圓之銅墊表面上方穿過—金屬薄層形成一緊密 、'’。合之錫層’以便直接做為小尺寸之凸塊，進崎低凸塊間 距、提高凸塊佈局密度及符合職域無錯標準。 、本發明之再_目的在於提供―種晶圓之鋪表面鑛錫方 法，其係在—晶圓之鋼墊表面上方穿過—金屬薄層形成一緊密 結合之錫層’以魏擇進—麵合触銲料之凸塊進而提供 無鉛覆晶技術及符合環保法規無鉛標準。 種晶圓之銅塾表面鍍錫方7 1353030 (Under Bump Metallurgy, UBM) has the prior art of the Republic of China Patent Notice No. 5% 293 "Bumping Process", No. 1221334 "Bumping Process", No. 1225698 "Wafer Level Package Bumping Process" And No. 1239578 "Bumping process" and so on. After the process is completed, the pad of the wafer (inscription) is also sequentially deposited on the bottom metal layer (composite layer) of the bump and the solder bump. On the other hand, semiconductor wafer processing technology is also moving toward miniaturization, corresponding to the development of packaging technology. In particular, during the progress of 0.13 micron wafer technology to 90 nanometer wafer technology, the process will be gradually replaced by copper. The aluminum pad (A1 pad) formed on the surface of the wafer suddenly becomes a copper pad (Cupad). ). The evolution of this advanced process trend immediately faced a technical problem, which meant that the Under Bump Metallurgy ' UBM, which was originally applied to wafer aluminum pads, was no longer due to metallurgical compatibility issues. Perfect for the next generation of wafer copper pads. Moreover, since the above-mentioned conventional bump metal layer usually requires a plurality of metal layers, the process is complicated and the production cost is relatively high. In addition, it is also necessary to consider what advanced technology to further reduce the bump size on the wafer copper pad to reduce the bump pitch, thereby increasing the total number of bumps that can be laid out in the unit area of the flip chip. . For this reason, it is indeed necessary to provide a copper pad surface tin-tin method for wafers to solve the defects of the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a hetero-surface bond tin-square method for a wafer, which is to temporarily form a semi-transparent metal thin layer on a wafer, and select to use chemical immersion plating. The method passes through the thin metal layer to form a tin layer over the copper pad', thereby simplifying the bump process/configuration and reducing the process cost. A secondary object of the present invention is to provide a method for tin plating a copper pad surface of a wafer, which is characterized in that the surface of the exposed copper pad portion of the metal thin layer is selectively replaced by a chemically immersed bond into a tin layer, thereby being closely bonded to The tin layer on the surface of the matte, which in turn increases the bond strength of the bump. Another object of the present invention is to provide a copper-plated surface ore method of a wafer which is formed over a surface of a copper pad of a wafer to form a tight, ''. The tin layer is combined to directly serve as a small-sized bump, to achieve a low bump pitch, to increase the bump layout density, and to meet the error-free standard of the job. Further, the present invention aims to provide a method for depositing a surface of a wafer, which is formed by passing a thin layer of metal over a surface of a steel pad of a wafer to form a tightly bonded tin layer. The solder bumps provide lead-free flip chip technology and lead-free standards in compliance with environmental regulations. Wax surface of copper matte wafer
將該銅墊之部份表面置換 為達上述之目的，本發明提供一 法，其包含··提供一晶圓，其表面具 表面形成一金屬薄層，以電性連接所 之部份表面；形成一光阻層於訪么s 成一錫層，並使該錫層沈積至該金屬薄層上方；去除該光阻 層；以及’去除未受該錫層遮蔽之金屬薄層。 接著，在該晶圓切割成數個晶片後，該錫層可直接做為小 尺寸之凸塊，以供媒介結合該晶片至一基板上，進而構成一 BGA或PGA封裝構造。或者，在該晶圓切割成數個晶片後， 該錫層可直接做為小尺寸之凸塊，且該晶片可直接使用做為一 CSP封裝構造。 再者，在本發明另一實施例之晶圓之銅墊表面鍍錫方法 中，於去除該光阻層的步驟之前，另可選擇包含：形成一銲料 層於該開口内之錫層上。接著，於去除該光阻層及去除未受該 錫層遮蔽之金屬薄層的步驟之後，另包含：對該銲料層進行回 焊’以形成一金屬凸塊。 另外’在本發明再一實施例之晶圓之銅墊表面鍍錫方法 中’於去除未受該錫層遮蔽之金屬薄層的步驟之後，另可進一 步包含：形成另一光阻層於該晶圓上，並圖案化該另一光阻 層’以形成數個開口裸露該銅墊上之錫層；在該開口内形成一 銲料層；去除該另一光阻層；以及，對該銲料層進行回焊，以 形成數個金屬凸塊。 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更明顯易 懂’下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 說明如下。 根據本發明之晶圓之銅塾表面_方法，其主要包含下列 步靜.提供一晶圓1，其表面具有數個鋼塾11 ;在該晶圓i之 表面形成-金層2，以電性連接所有該銅塾u且裸露各 該銅塾11之部份表面；形成一光阻層3於該金層2上， 並圖案化該光阻層3，以形成數個開口 31娜該銅塾U上之 金屬薄層2 ;在該開口 31内形成—錫層4 ;去除該光阻層3 ; 以及，去除未受該騎4遮蔽之金層2。本發明係可依需 求選擇藉由下述第-至第三實_之任—種方式進行該晶圓 之銅墊表面賴方法，該第-至第三實施例係分別作詳細說明 如下。 請參照第1至7圖所示，本發明第一實施例之晶圓之銅墊 表面錢錫方法主要包含下列步驟：提供—晶心，其表面具有 數個鋼墊11 ;在該晶圓i之表面形成一金屬薄層2，以紐連 接所有該銅墊11且裸露各該銅墊u之部份表面；形成一光阻 層3於該金屬薄層2上’並圖案化該光阻層3，以形成數個開 口 31裸露該銅塾11上之金屬薄層2 ;化學浸鐘處理該金屬薄 層2裸露出的銅墊η部份表面，將該銅墊u之部份表面置換 成一錫層4 ’並使該錫層4沈積至該金屬薄層2上方；去除該 光阻層3，以及，去除未受該錫層4遮蔽之金屬薄層2。 請參照第1圖所示，本發明第一實施例之晶圓之鋼塾表面 1353030 鑛錫方法第—步驟係：提供該晶® 1，其表面具有數個銅塾 11。在本步驟中，該晶圓1較佳係選自矽晶圓，且該晶圓1係 選擇使用0.18微米以下之銅製程進行加工，以便在該晶圓1 之表面形成數個該銅塾ll(Cu pad)及銅線路(未綠示）。接著， 該晶圓1之表面進一步形成一保護層12，且圖案化該保護層 12以疋義數個開口(未標示）’藉此裸露該銅塾η及包埋該銅 線路。該保護層12通常選自氧化砍或氮化硬等絕緣材質。 凊參照第2圖所示，本發明第一實施例之晶圓之銅墊表面 鑛錫方法第一步驟係、·在該晶圓1之表面形成該金屬薄層2， 以電性連接所有該銅墊η且裸露各該銅墊11之部份表面。在 本步驟中，本發明較佳在真空狀態下選擇利用濺鍍(印uttering deposition)、蒸鍍(evaporati〇n dep〇siti〇n)或無電鍍 plating)處理該晶圓〗之表面，以形成該金屬薄層2。該金屬薄 層2之厚度較佳控制在j奈来㈣至j微米㈣)之間特別是 在5奈米至800奈米之間，最佳是在1〇奈米至600奈米之間。 該金屬薄層2之厚度必需適當控制至極薄，以便使其具有半透 性能裸露各該婦11之部絲面’進而有利於後續利用化學 浸鐘方式雜下方的峨U之部絲面置換成闕層4。再 者，該金屬薄層2之材質較佳選自無法被錫置換之金屬 ，例如 銀或金等，其抑在製程巾暫時性且全_的電性連接所有該 銅墊11，其目的在於用以克服在後續進行化學浸鐘時 ，因該 (S ) 12 1353030 晶圓1之内部電路(未繪示)造成各鋼墊U之電位不相同的問 題，以確保能在所有之銅塾U上形成一致厚度的錫層4。 清參照第3及4圖所示’本發明第一實施例之晶圓之銅墊 表面鑛錫方法第三步驟係：形成該光_ 3於該金屬薄層2 上’並圖魏該光阻層3 ’以形絲健開口 31裸露該銅墊 11上之金屬薄層2。在本步驟中，本發曰月較佳選擇藉由塗佈液 態光阻(photoresist)或黏貼乾膜(dry film)而形成該光阻層3，且 其係可取材自貞型光喊正型光阻^接著，本發義利用一般 曝細影对·光阻層3進行_化_，_成數個該開 口 3卜該開口 31對應於該銅塾u之位i，因而可裸露該銅 墊11上之金屬薄層2。 請參照第5及5A圖所示，本發明第一實施例之晶圓之銅 墊表面麟方法細步獅：化學浸_理該金屬薄層2裸露 出的銅塾11部份表面，將該銅墊u之部份表面置換成一錫層 4，並使該錫層4沈積至該金屬薄層2上方。在本步驟中該 化學改鑛方式較佳顧自具有置換性之方式，特別是化學 浸錫製程(Immersion Tin Process)。該化學浸鍍處理之電鑛液係 較佳以錫電麟為主，彳物氣倾(SnCl2)加上錯合#KC〇mplex agent)之電錢液，其中該錯合劑較佳可選自硫脈(Thi〇urea)。藉 此’由於該電鑛液中之錫離子將逐漸置換該金屬薄層2裸露出 的銅墊11部份表面’因而沈獅成該錫層4，且最後該金屬 13 1353030 薄層2裸露出之銅墊n部份表面將被錫置換取代並填實。值 得/主意的是’如第5A圖所示，該金屬薄層2並未被錫所置換， 且該金屬薄層2裸露出之銅墊11部份表面的銅被錫所置換取 代’因而形成一粗糙凹面11丨緊密結合該錫層此時，若進 一步延長化學浸鍍反應時間，則錫離子可能進一步置換位於該 金屬薄層2下方原本未裸露出之銅墊u的其他鄰近部位，因 而擴大該錫層4的置換範圍及該粗糙凹面111之凹陷程度。再 者，該錫層4係持續沈積至該金屬薄層2上方，該錫層4之高 度(厚度)較佳控制在1〇〇奈米_)至100微米(腿)之間，特別 是在0.1微米至75微米之間，最佳是在丨微米至5〇微米之間。 再者’該錫層4之材質除了選自錫之外，亦可選自其他無鉛焊 料，例如錫銀合金或錫銀銅合金等。值得注意的是，當該金屬 薄層2選自銀時，該金屬薄層2將更有利於抑制銅與錫之間容 易形成介金屬化合物伽卿细脱⑸呵咖心^^之問題。 请參照第6圖所示，本發明第一實施例之晶圓之銅墊表面 鐘錫方法第五步驟係：去除該光阻層3。在本步驟中，可利用 一般顯影方式去除該光阻層3。當該光阻層3選自光阻乾膜 時’則亦可直接撕除之。在絲該絲層3後，將裸露該錫層 4以及未受該錫層4遮蔽之金屬薄層2。 請參照第7圖所示，本發明第一實施例之晶圓之銅塾表面 鍵錫方法第六步驟係：去除未受該錫層4遮蔽之金屬薄層2。 (S ; 14 在本步驟中，本發明較佳選用適當之餘刻液，以選擇性蝕刻去 除該金屬薄層2之銀、金或其他無法被錫置換之金屬，但不致 兹刻該錫層4。再者，在本發明之其他實施例巾，亦可另以形 成光阻、#光、顯影等步驟在該錫層4上形成另—光阻層做為 L(未繪示）’但曝露未受麟層4遮蔽之金屬薄層2， 以便利用侧祕刻去除該金屬薄層2之銀或金。接著，再利 用顯影液去除該錫層4上之另一光阻層。 藉由上述第一至第六步驟，本發明第一實施例即可在該晶 圓1之銅塾11上穿過該金屬薄層2形成緊密結合之該錫層4, 且該錫層4可直接做為小尺寸之凸塊。在完成本發明第一實施 例之晶圓之銅塾表面賴方法後，接著可將該晶目丨切割成數 個晶片（未繪不)’該⑼可糊該錫層4(小尺寸之凸塊)媒介結 合至一基板(未繪示)上，進而構成一 BGA或pGA封装構造。 或者，在該晶圓1切割成數個晶片（未繪示)後，隨即直接使用 做為一 CSP封裝構造。由於該錫層4定義之凸塊尺寸相對較 小，故有利於進一步縮減銅墊間距、降低凸塊間距，及提高單 位面積中之凸塊佈局密度。同時，亦能符合R〇HS及WEEE 等國際環保法規對無鉛標準的要求。 請參照第1至5及8至11圖所示，本發明第二實施例之晶 圓之銅墊表面錄錫方法係相似於本發明第一實施例，但該第二 實施例之晶圓之銅墊表面鐘錫方法係包含下列步驟：提供一晶 1353030 圓1，其表面具有數個銅墊11;在該晶圓1之表面形成一金屬 薄層2，以電性連接所有該銅墊11且裸露各該銅墊11之部份 表面；形成一光阻層3於該金屬薄層2上，並圖案化該光阻層 3，以形成數個開口 31裸露該銅墊u上之金屬薄層2 ;化學 浸鍍處理該金屬薄層2裸露出的銅墊11部份表面，將該銅墊 11之部份表面置換成一錫層4’並使該錫層4沈積至該金屬薄 層2上方；形成一銲料層5於該開口 31内之錫層4上；去除 該光阻層3，去除未受該錫層4遮蔽之金屬薄層2 ;以及，對 該銲料層5進行回焊，以形成一金屬凸塊5’。 相較於該第一較佳實施例，該第二較佳實施例較佳係形成 較厚之該光阻層3 ’使該光阻層3之開口 31具有較大空間， 以便在形成該錫層4之後，尚能進一步形成該銲料層5。該銲 料層5係可選用印刷、電鍍或蒸鍍等方式形成在該開口 31内 之錫層4上’其中該電鍍方式可選自有電電鍍(dectr〇plating) 或無電電鑛(electroless plating)等方式。該銲料層5之材質較佳 選自無鉛焊料，例如錫、錫銀合金或錫銀銅合金等，且其材質 及溶點可相同或相異於該錫層4之材質及熔點。惟，依實際需 求，該銲料層5之材質仍可選自含鉛焊料，例如錫鉛合金等。 該銲料層5經回焊後形成該金屬凸塊5,，該金屬凸塊5’之高 度(厚度)較佳控制在5微米(um)至300微米(um)之間，特別是 在10微求至250微求之間’最佳是在20微米至200微米之間。 16 1353030 藉由上述第一至第八步驟，本發明第二實施例即可在該晶 圓1之銅墊11上穿過該金屬薄層2形成緊密結合之該錫層4, 並藉由該錫層4進一步形成該金屬凸塊5，。在完成本發明第二 實施例之晶圓之銅墊表面鍵錫方法後，接著可將該晶圓丨切割 成數個晶片（未繪示），該晶片可利用該金屬凸塊5’媒介結合至 一基板(未繪示)上，進而構成一 BGA或PGA封裝構造。或者， 在該晶圓1切割成數個晶片（未繪示)後，隨即直接使用做為一 CSP封裝構造。由於該錫層4及金屬凸塊5,仍具相對較小之尺 寸’故亦有利於進一步縮減銅墊間距、降低凸塊間距，及提高 單位面積中之凸塊佈局密度。同時’亦能符合κ〇Η8&νΕΕΕ 等國際環保法規對無鉛標準的要求》 請參照第1至7及12至16圖所示，本發明第三實施例之 晶圓之銅墊表面鍍錫方法係相似於本發明第一實施例，但該第 二實施例之晶圓之銅塾表面鑛錫方法係包含下列步驟：提供一 晶圓1，其表面具有數個銅墊u;在該晶圓丨之表面形成一金 屬薄層2，以電性連接所有該銅塾n且裸露各該銅墊n之部 份表面；形成一光阻層3於該金屬薄層2上，並圖案化該光阻 層3，以形成數個開口 31裸露該銅墊u上之金屬薄層2 ;化 學浸鍵處賴鋪薄層2裸露$的銅塾n部絲面，將該銅 塾11之部份表面置換成—騎4，並使該騎4沈積至該金 屬薄層2上方；去除該光阻層3 ;去除未受該錫層4遮蔽之金 17 丄妁3030 屬薄層2 ;形成另-光阻層6於該晶圓丨上，並_化該光阻 層6 ’以形成數個開π 61裸露該轉u上之錫層4 ;在該開 口 61内形成-銲料層7 ;去除該光阻層6 ;以及對該鲜料層 7進行回焊’以形成數個金屬凸塊7,。 相較於該第-較佳實施例，該第三較佳實施例係進一步在 本發明第-實施例之第六步驟後增加第七至第十步驟，以形成 較厚之該光阻層6，使該光阻層6提供數個開口 61，以便進一 步在該錫層4上形成該銲料層7。本發明係可選擇藉由塗佈液 態光阻或黏貼乾膜而形成該光阻層6。再者，該鲜料層7係可 __ ittM(eleetrolessplating)或舰料式形成在該 開口 61内之錫層4上。該銲料層7較佳選自無鉛焊料，例如 錫、錫銀合金或錫銀銅合金等，且其材質及熔點可相同或相異 於該錫層4之材質及熔點。惟，依實際需求，該銲料層7之材 質仍可選自含錯焊料，例如錫鉛合金等。該銲料層7經回烊後 形成該金屬凸塊7’ ’該金屬凸塊7,之高度(厚度)較佳控制在1〇 微米(um)至300微米(um)之間，特別是在2〇微米至25〇微米 之間，最佳是在30微米至200微米之間。 藉由上述第一至第十步驟，本發明第三實施例即可在該晶 圓1之銅墊11上穿過該金屬薄層2形成緊密結合之該錫層4, 並藉由該錫層4進一步形成該金屬凸塊7，β在完成本發明第三 實施例之晶圓之銅墊表面鑛錫方法後，接著可將該晶圓1切割 18 1353030 成數個晶片（未繪示），該晶片可利用該金屬凸塊7,媒介結合至 一基板(未纟會示)上，進而構成—BGA或PGA封裝構造。或者， 在該晶圓1切割成數個晶片（未綠示)後，隨即直接使用做為一 CSP封裝構造。由於該錫層4及金屬凸塊7’仍具相對較小之尺 寸，故亦有利於進一步縮減銅墊間距、降低凸塊間距，及提高 單位面積中之凸塊佈局密度。同時，亦能符合R〇HS& ^ΕΕ 等國際環保法規對無鉛標準的要求β 如上所述，相較於習用凸塊底金屬層(UBM)因金屬冶金相 容性問題而不再完全適用於下一世代的晶圓銅墊上，且由凸塊 底金屬層長出之凸塊亦具有凸塊尺寸過大等缺點，第7、11及 16圖之本發明藉由先在該晶圓丨上暫時全面性形成該金屬薄 層2，接著再穿過該金屬薄層2將其裸露之銅墊u部份表面 進一步化學浸鍍置換成該錫層4，因而使該錫層4直接緊密結 合至該晶圓1之鋼墊u表面上，其確實可有效簡化凸塊製程、 降低製程成本、增加凸塊結合強度、降低凸塊間距、提高凸塊 佈局密度及符合環保法規無鉛標準。 雖然本發明已以較佳實施例揭露，然其並非用以限制本發 明，任何熟習此項技藝之人士，在不脫離本發明之精神和範圍 内，當可作各種更動與修飾，因此本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 【圖式簡單說明】 19 1353030 第1圖：本發明第一實施例之晶圓之銅墊表面鍍錫方法第一步 戰之示意圖。 · 第2圖：本發明第一實施例之晶圓之銅墊表面鐘錫方法第二步 驟之示意圖。 第3及4圖：本發明第一實施例之晶圓之銅墊表面鍍錫方法第 三步驟之示意圖。 第5及5A圖：本發明第一實施例之晶圓之銅墊表面鑛錫方法 第四步驟之示意圖及局部放大圖。 第6圖·本㈣第—實施例之晶®之銅墊表面麟方法第五步 驟之示意圖。 第7圖·本發明第—實施例之晶®之銅墊表©賴方法第六步 驟之示意圖。 第8、9、10及U圖：本發明第二實施例之晶圓之銅塾表面锻 錫方法第五至第八步驟之示意圖。 第12、13、14、15及16圖：本發明第三實施例之晶圓之銅墊 表面麟方法第七至第十步驟之示意圖。 【主要元件符號說明】 1 晶圓 111粗縫凹面 2 金屬薄層 31開口 11銅墊 12保護層 3 光阻層 4 錫層 20 1353030 5 銲料層 5, 金屬凸塊 6 光阻層 61 開口 7 銲料層 7, 金屬凸塊Disposing a part of the surface of the copper pad for the above purpose, the present invention provides a method comprising: providing a wafer having a surface formed with a thin metal layer to electrically connect a portion of the surface; Forming a photoresist layer to form a tin layer, and depositing the tin layer over the metal thin layer; removing the photoresist layer; and 'removing a thin metal layer not covered by the tin layer. Then, after the wafer is diced into a plurality of wafers, the tin layer can be directly used as a small-sized bump for the medium to bond the wafer to a substrate to form a BGA or PGA package structure. Alternatively, after the wafer is diced into a plurality of wafers, the tin layer can be directly used as a small-sized bump, and the wafer can be directly used as a CSP package. Furthermore, in the tin plating method of the copper pad surface of the wafer according to another embodiment of the present invention, before the step of removing the photoresist layer, the method further includes: forming a solder layer on the tin layer in the opening. Then, after the step of removing the photoresist layer and removing the thin metal layer not covered by the tin layer, the method further comprises: reflowing the solder layer to form a metal bump. In addition, after the step of removing the thin metal layer not covered by the tin layer in the method of tin plating the surface of the copper pad of the wafer according to the further embodiment of the present invention, the method further includes: forming another photoresist layer in the And patterning the other photoresist layer ′ on the wafer to form a plurality of openings to expose a tin layer on the copper pad; forming a solder layer in the opening; removing the other photoresist layer; and, the solder layer Reflow is performed to form a plurality of metal bumps. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The copper beryllium surface method of the wafer according to the present invention mainly comprises the following steps: providing a wafer 1 having a plurality of steel crucibles 11 on its surface; forming a gold layer 2 on the surface of the wafer i to be electrically Sexually connecting all of the copper ruthenium and exposing portions of the surface of the copper ruthenium 11; forming a photoresist layer 3 on the gold layer 2, and patterning the photoresist layer 3 to form a plurality of openings 31 a thin metal layer 2 on the U; a tin layer 4 is formed in the opening 31; the photoresist layer 3 is removed; and the gold layer 2 not covered by the ride 4 is removed. In the present invention, the copper pad surface grading method of the wafer can be selected by any of the following first to third embodiments, and the first to third embodiments are respectively described in detail below. Referring to FIGS. 1 to 7, the method for depositing the copper pad surface of the wafer according to the first embodiment of the present invention mainly comprises the following steps: providing a crystal core having a plurality of steel pads 11 on the surface thereof; Forming a thin metal layer 2, connecting all the copper pads 11 with a button and exposing a part of the surface of the copper pad u; forming a photoresist layer 3 on the metal thin layer 2 and patterning the photoresist layer 3, forming a plurality of openings 31 to expose the thin metal layer 2 on the copper crucible 11; chemical immersion clock processing the surface of the n-shaped portion of the copper pad exposed by the metal thin layer 2, replacing a part of the surface of the copper pad u with a surface The tin layer 4' and the tin layer 4 are deposited over the metal thin layer 2; the photoresist layer 3 is removed, and the thin metal layer 2 not covered by the tin layer 4 is removed. Referring to Fig. 1, a steel crucible surface of a wafer according to a first embodiment of the present invention is shown in the first step of the method. The first step is to provide the crystal® 1, which has a plurality of copper crucibles 11 on its surface. In this step, the wafer 1 is preferably selected from a germanium wafer, and the wafer 1 is selectively processed using a copper process of 0.18 micron or less to form a plurality of the copper bumps on the surface of the wafer 1. (Cu pad) and copper lines (not shown in green). Then, a surface of the wafer 1 is further formed with a protective layer 12, and the protective layer 12 is patterned to define a plurality of openings (not labeled) to thereby expose the copper germanium and embed the copper wiring. The protective layer 12 is typically selected from insulating materials such as oxidized or nitrided hard. Referring to FIG. 2, in the first step of the method for depositing the surface of the copper pad of the wafer according to the first embodiment of the present invention, the metal thin layer 2 is formed on the surface of the wafer 1 to electrically connect all of the The copper pad η and exposes a part of the surface of each of the copper pads 11. In this step, the present invention preferably selects the surface of the wafer by sputtering, evaporation, or electroless plating to form a surface under vacuum. The thin metal layer 2. The thickness of the metal thin layer 2 is preferably controlled between jna (4) and j micron (four)), particularly between 5 nm and 800 nm, and most preferably between 1 nm and 600 nm. The thickness of the thin metal layer 2 must be appropriately controlled to be extremely thin so that it has a semi-transparent property to expose the silk surface of each of the women 11 and further facilitates the subsequent replacement of the silk surface of the 峨U under the chemical immersion clock.阙 layer 4. Furthermore, the material of the metal thin layer 2 is preferably selected from a metal that cannot be replaced by tin, such as silver or gold, etc., which is electrically connected to all the copper pads 11 temporarily and completely in the process towel. In order to overcome the problem that the potential of each steel pad U is different due to the internal circuit (not shown) of the wafer 1 (S) 12 1353030 in the subsequent chemical immersion clock, to ensure that all the copper 塾 U can be used. A tin layer 4 of uniform thickness is formed thereon. Referring to FIGS. 3 and 4, the third step of the method for depositing the surface of the copper pad surface of the wafer according to the first embodiment of the present invention is to form the light _3 on the thin metal layer 2 and to form the photoresist. The layer 3' exposes the thin metal layer 2 on the copper pad 11 with a wire opening 31. In this step, it is preferred to form the photoresist layer 3 by coating a liquid photoresist or a dry film, and the film is self-squeezing. Photoresistance ^ Next, the present invention uses a general exposure to the photoresist layer 3 to _ _, _ into a plurality of openings 3, the opening 31 corresponds to the position i of the copper 塾 u, thus the copper pad can be exposed Thin metal layer 2 on 11. Referring to FIG. 5 and FIG. 5A, the surface of the copper pad of the wafer of the first embodiment of the present invention is a fine step lion: chemical immersion: the exposed surface of the copper enamel 11 of the thin metal layer 2, A portion of the surface of the copper pad u is replaced with a tin layer 4, and the tin layer 4 is deposited over the metal thin layer 2. In this step, the chemical upgrading method is preferably in a manner of substitution, in particular, the Immersion Tin Process. The electroless ore plating process of the chemical immersion plating is preferably a tin-electric lining, a sputum gas sloping (SnCl 2 ) plus a miscellaneous #KC 〇mplex agent), wherein the wrong agent is preferably selected from the group consisting of Thi〇urea. Thereby, because the tin ions in the electro-mineral liquid will gradually replace the partial surface of the copper pad 11 exposed by the thin metal layer 2, the lion is formed into the tin layer 4, and finally the thin layer 2 of the metal 13 1353030 is exposed. The n-part surface of the copper pad will be replaced by tin replacement and filled. It is worthwhile or not to say that, as shown in Fig. 5A, the thin metal layer 2 is not replaced by tin, and the copper on the surface of the portion of the copper pad 11 exposed by the thin metal layer 2 is replaced by tin. A rough concave surface 11 丨 tightly bonds the tin layer. At this time, if the chemical immersion plating reaction time is further extended, the tin ions may further replace other adjacent portions of the copper pad u which are not originally exposed under the metal thin layer 2, thereby expanding The replacement range of the tin layer 4 and the degree of depression of the rough concave surface 111. Furthermore, the tin layer 4 is continuously deposited over the metal thin layer 2, and the height (thickness) of the tin layer 4 is preferably controlled between 1 nanometer _) and 100 micrometers (leg), especially in Between 0.1 microns and 75 microns, preferably between 丨 microns and 5 〇 microns. Further, the material of the tin layer 4 may be selected from other lead-free solders other than tin, such as tin-silver alloy or tin-silver-copper alloy. It is worth noting that when the thin metal layer 2 is selected from silver, the thin metal layer 2 will be more advantageous for suppressing the problem that the formation of the intermetallic compound gamma fine between the copper and the tin. Referring to FIG. 6, the fifth step of the copper pad surface of the wafer of the first embodiment of the present invention is: removing the photoresist layer 3. In this step, the photoresist layer 3 can be removed by a general development method. When the photoresist layer 3 is selected from a photoresist dry film, it can be directly removed. After the silk layer 3 is silked, the tin layer 4 and the thin metal layer 2 which is not shielded by the tin layer 4 are exposed. Referring to FIG. 7, the sixth step of the method for bonding the copper matte surface of the wafer according to the first embodiment of the present invention is to remove the thin metal layer 2 which is not shielded by the tin layer 4. (S; 14 In this step, the present invention preferably uses a suitable residual liquid to selectively etch away the silver, gold or other metal that cannot be replaced by tin, but does not inscribe the tin layer. 4. In another embodiment of the present invention, a photoresist layer may be formed on the tin layer 4 as a L (not shown) by forming a photoresist, #光, development, and the like. The metal thin layer 2 not covered by the lining layer 4 is exposed to remove the silver or gold of the metal thin layer 2 by side etching. Then, another photoresist layer on the tin layer 4 is removed by using a developing solution. In the first to sixth steps, the first embodiment of the present invention can form the tin layer 4 tightly bonded through the thin metal layer 2 on the copper germanium 11 of the wafer 1, and the tin layer 4 can be directly a bump of a small size. After completing the copper ruthenium surface immersion method of the wafer of the first embodiment of the present invention, the crystal enamel can be subsequently cut into a plurality of wafers (not shown). 4 (small-sized bumps) medium is bonded to a substrate (not shown) to form a BGA or pGA package structure. Alternatively, in the wafer 1 After being cut into several wafers (not shown), it is directly used as a CSP package structure. Since the size of the bump defined by the tin layer 4 is relatively small, it is advantageous to further reduce the copper pad pitch and reduce the bump pitch, and Improve the density of bump layout per unit area. At the same time, it can meet the requirements of lead-free standards in international environmental regulations such as R〇HS and WEEE. Please refer to Figures 1 to 5 and 8 to 11 for the second embodiment of the present invention. The copper pad surface recording method of the wafer is similar to the first embodiment of the present invention, but the copper pad surface tin-tin method of the wafer of the second embodiment comprises the following steps: providing a crystal 1353030 circle 1, the surface thereof a plurality of copper pads 11 are formed on the surface of the wafer 1 to electrically connect all of the copper pads 11 and expose portions of the surface of the copper pads 11; a photoresist layer 3 is formed thereon. On the thin metal layer 2, the photoresist layer 3 is patterned to form a plurality of openings 31 to expose the thin metal layer 2 on the copper pad u; the portion of the copper pad 11 exposed by the metal thin layer 2 is chemically etched Surface, replacing part of the surface of the copper pad 11 with a tin layer 4' a tin layer 4 is deposited over the metal thin layer 2; a solder layer 5 is formed on the tin layer 4 in the opening 31; the photoresist layer 3 is removed to remove the thin metal layer 2 not covered by the tin layer 4; The solder layer 5 is reflowed to form a metal bump 5'. Compared with the first preferred embodiment, the second preferred embodiment preferably forms a thicker photoresist layer 3'. The opening 31 of the photoresist layer 3 has a large space, so that the solder layer 5 can be further formed after the formation of the tin layer 4. The solder layer 5 can be formed by printing, plating or evaporation. The tin layer 4 in the opening 31 may be selected from the group consisting of electroplating or electroless plating. The material of the solder layer 5 is preferably selected from lead-free solders such as tin, tin-silver alloy or tin-silver-copper alloy, and the material and melting point thereof may be the same or different from the material and melting point of the tin layer 4. However, according to actual needs, the material of the solder layer 5 can still be selected from lead-containing solders, such as tin-lead alloys. The solder layer 5 is reflowed to form the metal bump 5, and the height (thickness) of the metal bump 5' is preferably controlled between 5 micrometers (um) and 300 micrometers (um), especially at 10 micrometers. Finding the best between 250 micro-questions is between 20 microns and 200 microns. 16 1353030, in the first to eighth steps, the second embodiment of the present invention can form a tightly bonded tin layer 4 through the thin metal layer 2 on the copper pad 11 of the wafer 1 and The tin layer 4 further forms the metal bumps 5. After the copper pad surface bond tin method of the wafer of the second embodiment of the present invention is completed, the wafer defect can be subsequently cut into a plurality of wafers (not shown), and the wafer can be bonded to the metal bump 5' medium. A substrate (not shown) further constitutes a BGA or PGA package structure. Alternatively, after the wafer 1 is diced into a plurality of wafers (not shown), it is directly used as a CSP package structure. Since the tin layer 4 and the metal bumps 5 are still relatively small in size, it is also advantageous to further reduce the copper pad pitch, reduce the bump pitch, and increase the bump layout density per unit area. At the same time, it can also meet the requirements of the international environmental protection regulations such as κ〇Η8&νΕΕΕ for the lead-free standard. Please refer to the figures 1 to 7 and 12 to 16 for the tin plating method of the copper pad surface of the wafer according to the third embodiment of the present invention. Similar to the first embodiment of the present invention, the copper beryllium surface tinning method of the wafer of the second embodiment comprises the steps of: providing a wafer 1 having a plurality of copper pads on its surface; Forming a thin metal layer 2 on the surface of the crucible to electrically connect all of the copper crucibles n and expose a portion of the surface of each of the copper pads n; forming a photoresist layer 3 on the thin metal layer 2, and patterning the light The resist layer 3 is formed to expose a plurality of openings 31 to expose the thin metal layer 2 on the copper pad u; the chemical immersion bond is disposed on the thin layer 2 of the bare copper n-side silk surface, and a part of the surface of the copper bead 11 Substituting - riding 4, and depositing the ride 4 above the thin metal layer 2; removing the photoresist layer 3; removing the gold 17 丄妁 3030 which is not covered by the tin layer 4 is a thin layer 2; forming another light The resist layer 6 is on the wafer stack, and the photoresist layer 6' is formed to form a plurality of tin layers 4 exposed on the turn π 61; and formed in the opening 61 - 7 layers; removing the photoresist layer 6; and the fresh material layer is reflowed 7 'to form a plurality of metal bumps 7 ,. Compared with the first preferred embodiment, the third preferred embodiment further adds seventh to tenth steps after the sixth step of the first embodiment of the present invention to form a thicker photoresist layer 6 The photoresist layer 6 is provided with a plurality of openings 61 to further form the solder layer 7 on the tin layer 4. In the present invention, the photoresist layer 6 can be formed by coating a liquid photoresist or adhering a dry film. Furthermore, the fresh layer 7 can be formed on the tin layer 4 in the opening 61 by eletictroless plating or ship-forming. The solder layer 7 is preferably selected from lead-free solders such as tin, tin-silver alloy or tin-silver-copper alloy, and the material and melting point thereof may be the same or different from the material and melting point of the tin layer 4. However, depending on the actual needs, the material of the solder layer 7 can still be selected from mis-soldered solders such as tin-lead alloys. After the solder layer 7 is returned, the metal bump 7 is formed, and the height (thickness) of the metal bump 7 is preferably controlled between 1 〇 micrometer (um) and 300 micrometers (um), especially at 2 Between microns and 25 microns, preferably between 30 microns and 200 microns. With the first to tenth steps, the third embodiment of the present invention can form a tightly bonded tin layer 4 through the thin metal layer 2 on the copper pad 11 of the wafer 1 and the tin layer is formed by the tin layer. 4 further forming the metal bumps 7, β after completing the method of depositing the surface of the copper pad of the wafer of the third embodiment of the present invention, and then cutting the wafer 1 into 18 1353030 into a plurality of wafers (not shown), The wafer can utilize the metal bumps 7, and the medium is bonded to a substrate (not shown) to form a BGA or PGA package structure. Alternatively, after the wafer 1 is diced into a plurality of wafers (not shown in green), it is directly used as a CSP package structure. Since the tin layer 4 and the metal bumps 7' are still relatively small in size, it is also advantageous to further reduce the copper pad pitch, reduce the bump pitch, and increase the bump layout density per unit area. At the same time, it can also meet the requirements of lead-free standards in international environmental regulations such as R〇HS& ^ΕΕ. As mentioned above, it is no longer fully applicable to the metallurgical compatibility of conventional bump metallization (UBM). The next generation of wafer copper pads, and the bumps grown from the bottom metal layer of the bumps also have the disadvantages of excessive bump size, and the inventions of Figures 7, 11 and 16 are temporarily placed on the wafer. Forming the thin metal layer 2 comprehensively, and then further chemically immersing the surface of the exposed copper pad u through the thin metal layer 2 to replace the tin layer 4, thereby directly bonding the tin layer 4 to the On the surface of the steel pad u of the wafer 1, it can effectively simplify the bump process, reduce the process cost, increase the bond strength of the bump, reduce the bump pitch, increase the bump layout density, and comply with the environmental protection regulations lead-free standard. The present invention has been disclosed in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS 19 1353030 FIG. 1 is a first schematic diagram of a tin plating method for a copper pad surface of a wafer according to a first embodiment of the present invention. Fig. 2 is a schematic view showing the second step of the method for forming a copper pad surface of a wafer according to the first embodiment of the present invention. 3 and 4 are schematic views showing the third step of the tin plating method on the surface of the copper pad of the wafer according to the first embodiment of the present invention. 5 and 5A are diagrams showing a fourth step of the method for depositing tin on the surface of a copper pad of a wafer according to the first embodiment of the present invention and a partial enlarged view thereof. Fig. 6 is a schematic view showing the fifth step of the copper pad surface lining method of the crystal of the fourth embodiment of the present invention. Fig. 7 is a schematic view showing the sixth step of the method of the crystal pad of the crystal according to the first embodiment of the present invention. Figures 8, 9, 10 and U are schematic views of the fifth to eighth steps of the method for forging tin on the copper beryllium of the wafer according to the second embodiment of the present invention. Figures 12, 13, 14, 15 and 16 are schematic views of the seventh to tenth steps of the copper pad of the wafer according to the third embodiment of the present invention. [Main component symbol description] 1 Wafer 111 rough concave surface 2 Metal thin layer 31 opening 11 Copper pad 12 Protective layer 3 Photoresist layer 4 Tin layer 20 1353030 5 Solder layer 5, Metal bump 6 Photoresist layer 61 Opening 7 Solder Layer 7, metal bump
21twenty one