CN116072548A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN116072548A
CN116072548A CN202211013137.1A CN202211013137A CN116072548A CN 116072548 A CN116072548 A CN 116072548A CN 202211013137 A CN202211013137 A CN 202211013137A CN 116072548 A CN116072548 A CN 116072548A
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China
Prior art keywords
layer
gold
seed layer
nickel
seed
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Pending
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CN202211013137.1A
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Inventor
郑湘宁
许文政
王晨聿
郭志明
陈传迢
何荣华
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Chipbond Technology Corp
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Chipbond Technology Corp
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Publication of CN116072548A publication Critical patent/CN116072548A/zh
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Abstract

本发明是半导体装置的制造方法。所述半导体装置的制造方法包含：封装结构包含第一载板、种子层、多个线路、晶粒及封胶材料，将第二载板设置于该封胶材料后，移除该第一载板以显露该种子层，接着移除该种子层以显露所述线路，再以浸金方式沉积金层于各该线路上，以形成半导体装置，该金层用以避免各该线路氧化，并可提供良好焊接可靠度。

Description

半导体装置的制造方法
技术领域
本发明关于一种半导体装置的制造方法，特别是一种提高半导体装置焊接可靠度的制造方法。
背景技术
为了避免线路接触空气后氧化，可在线路上形成表面处理层，以阻隔空气接触线路，表面处理层一般为化镍浸金(ENIG,Electroless Nickel Immersion Gold)或化镍钯浸金(ENEPIG,Electroless Nickel Electroless Palladium Immersion Gold)，化镍浸金是通过还原剂将镍离子还原成镍金属，使镍沉积于铜线路上形成镍层，再通过置换反应于镍层上镀金，镍沉积过程产生的氢气气泡会造成气孔问题，而化镍钯浸金是通过化学反应将铜表面置换为钯后，在钯核的基础上以化学镀方式形成镍磷合金层，再通过置换反应于镍磷合金层上镀金，除了气孔问题，镍磷合金层在浸金过程中会被过度蚀刻，进而影响到焊接可靠度。
发明内容
本发明的目的在于提供一种半导体装置的制造方法，以浸金方式形成金层于封装结构的线路上，可避免线路氧化，亦可提升其焊接可靠度。
本发明的一种半导体装置的制造方法，首先提供封装结构，该封装结构包含第一载板、种子层、多个线路、晶粒及封胶材料，该种子层形成于该第一载板上，所述线路形成于该种子层上，该晶粒接合于所述线路，该封胶材料覆盖该晶粒及所述线路，设置第二载板于该封胶材料上，接着移除该第一载板以显露该种子层，并移除该种子层以显露所述线路，再以浸金方式沉积金层于各该线路上。
较佳地，各该线路包含镍层及铜层，该镍层以纯镍电镀方式形成于该种子层，该铜层形成于该镍层，移除该种子层后，显露该镍层，再以浸金方式沉积该金层于该镍层上。
较佳地，各该线路包含铜层，该铜层形成于该种子层，移除该种子层后，显露该铜层，再以浸金方式沉积该金层于该铜层上。
较佳地，是以等离子体蚀刻方式移除该种子层。
较佳地，所述线路是借由图案化介电层形成于该种子层上，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露各该线路的顶面及侧面。
较佳地，该金层沉积于各该线路的该顶面及该侧面。
较佳地，所述线路是借由图案化介电层形成于该种子层，各该线路包含镍层及铜层，该镍层以纯镍电镀方式形成于该种子层，该铜层形成于该镍层，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露该镍层的顶面及侧面。
较佳地，该金层沉积于该镍层的该顶面及该侧面。
较佳地，所述线路是借由图案化介电层形成于该种子层，各该线路包含铜层，该铜层形成于该种子层，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露该铜层的顶面及侧面。
较佳地，该金层沉积于该铜层的该顶面及该侧面。
较佳地，该图案化介电层的蚀刻厚度不大于1.5μm。
较佳地，该第一载板包含基板及离型层，该离型层形成于该基板表面，该种子层形成于该离型层上，移除该基板及该离型层后，显露该种子层。
较佳地，该种子层为钛钨/铜层或钛/铜层。
较佳地，该铜层为重分布线路结构。
较佳地，在沉积该金层后，形成焊球于该金层上。
借由上述技术方案，本发明至少具有以下优点效果：本发明半导体装置的制造方法可避免线路氧化，亦可提升其焊接可靠度。
附图说明
图1：依据本发明的第一实施例，封装结构的剖视图。
图2至图7：依据本发明的第一实施例，半导体装置的制造方法的剖视示意图。
图8及图9：依据本发明的第二实施例，半导体装置的制造方法的剖视示意图。
图10及图11：依据本发明的第三实施例，半导体装置的制造方法的剖视示意图。
图12及图13：依据本发明的第四实施例，半导体装置的制造方法的剖视示意图。
【主要元件符号说明】
100：封装结构                    110：第一载板
111：第一基板                    112：第一离型层
120：种子层                      130：线路
130a：顶面                       130b：侧面
131：镍层                        132：铜层
140：图案化介电层                150：晶粒
160：封胶材料                    200：第二载板
210：第二基板                    220：第二离型层
300：金层                        400：焊球
具体实施方式
请参阅图1，在半导体装置的制造方法中，首先提供封装结构100，该封装结构100包含第一载板110及种子层120，该种子层120形成于该第一载板110上，较佳地，该第一载板110包含第一基板111及第一离型层112，该第一离型层112形成于该第一基板111表面，该种子层120形成于该第一离型层112上，其中该第一基板111的材质可为玻璃、硅晶圆或陶瓷，该第一离型层112的材质可为聚酰亚胺(PI)或无机离型剂(卤素-金属化合物)，该种子层120可为钛钨/铜(TiW/Cu)层或钛/铜(Ti/Cu)层，较佳地，是以溅镀(sputtering)方式在该第一离型层112镀上该种子层120。
请参阅图1，该封装结构100另包含多个线路130、至少一个晶粒150及封胶材料160，所述线路130形成于该种子层120上，该晶粒150接合于所述线路130，该封胶材料160覆盖该晶粒150及所述线路130，较佳地，该晶粒150借由凸块覆晶接合于所述线路130上，所述线路130是借由图案化介电层140形成于该种子层120上，在该种子层120上形成介电层后，图案化该介电层以形成多个开口，所述开口显露该种子层120，而所述线路130分别形成于所述开口中，该介电层材料可为聚酰亚胺(PI,polyimide)、苯并环丁烯(BCB,benzocyclobutene)或环氧树脂(epoxy)，在本实施例中，该介电层的材质为聚酰亚胺。
在第一实施例中，各该线路130包含镍层131及铜层132，该镍层131以纯镍电镀方式形成于该种子层120，该镍层131的材料为不含磷的纯镍金属，不会产生气孔及磷沉积的问题，因此该镍层131的孔隙率(porosity)低于化学镀形成的镍层，且该镍层131的致密性(density)高于化学镀形成的镍层，该铜层132为形成于该镍层131上的重分布线路结构(RDL,redistributionlayer)。
请参阅图2，接着设置第二载板200于该封胶材料160上，较佳地，该第二载板200包含第二基板210及第二离型层220，该第二基板210的材质可为玻璃、硅晶圆、陶瓷、不锈钢或硅胶/玻璃纤维，该第二离型层220的材质可为感压胶(PSA,pressure sensitiveadhesive)、环氧树脂(epoxy)或硅胶(silicon glue)，该第二基板210及该第一基板111可为相同材质或不同材质，本发明不以此为限制。
请参阅图3，设置该第二载板200于该封胶材料160后，翻转半导体装置，使该第一载板110位于上方而该第二载板200位于下方，请参阅图4，接着移除该第一载板110，以显露该第一载板110下方的该种子层120，在本实施例中，是以机械分离(mechanicaldebonding)方式使该第一离型层112自该种子层120剥离，借此移除该第一基板111及该第一离型层112。
请参阅图5，移除该第一载板110后，接着移除该种子层120，以显露所述线路130，较佳地，是以蚀刻方式移除该种子层120，以显露各该线路130的顶面130a，在第一实施例中，是以等离子体蚀刻(plasma etching)方式移除该种子层120，以显露各该线路130的该镍层131。
请参阅图6，移除该种子层120后，接着以浸金(immersion gold plating)方式沉积金层300于显露的各该线路130上，该金层300为表面处理层或钝化层，用以保护所述线路130，避免所述线路130氧化，相较于电镀金层，浸金方式形成的该金层300厚度均匀性及覆盖程度较佳，因此厚度较薄的该金层300与厚度较厚的电镀金层抗氧化防护效果相近，可达到降低成本的效益。
在第一实施例中，移除该种子层120后，显露各该线路130的该镍层131，接着以浸金方式使该金层300沉积于该镍层131上，由于以纯镍电镀方式形成的该镍层131不含磷且致密性高，沉积该金层300时，该镍层131表面不会被过度蚀刻，亦不易产生黑垫(blackpad)，因此该金层300具有较佳的抗氧化防护效果，可有效提升焊接可靠度。
请参阅图7，若该半导体装置为球栅阵列封装(BGA,ball grid array)，则在沉积该金层300后，形成焊球400于该金层300上，完成后续制程后即可得BGA，后续制程包含移除该第二载板200、切割及形成电磁干扰屏蔽罩(EMI shielding layer)等现有习知制程，在此不赘述，反之，若该半导体装置为平面网格阵列封装(LGA,land grid array)，则无须形成焊球于该金层300，可直接进行后续制程，以取得该半导体装置。
请参阅图8及图9，其为本发明的第二实施例，较佳地，使用等离子体蚀刻方式移除该种子层120时，可借由调整等离子体蚀刻参数，同时移除该种子层120及部份该图案化介电层140，而显露出各该线路130的顶面130a及侧面130b，因此以浸金方式沉积该金层300时，该金层300会沉积于各该线路130的该顶面130a及该侧面130b，借此增加该金层300面积，以提高焊接可靠度，在第二实施例中，以等离子体蚀刻方式移除该种子层120及部份该图案化介电层140后，各该线路130显露的该顶面130a及该侧面130b为该镍层131的顶面及侧面，因此该金层300是沉积于该镍层131的顶面及侧面。
较佳地，在等离子体蚀刻该种子层120及部份该图案化介电层140时，可借由调整等离子体蚀刻参数，使该图案化介电层140的蚀刻厚度不大于1.5μm，借此显露出该镍层131的该顶面及该侧面，亦同时保有足够厚度的介电层，以避免失去介电层效果。
图10及图11为本发明的第三实施例，第三实施例与第一实施例的差异在于各该线路130未包含镍层，仅包含铜层132，该铜层132为形成于该种子层120上的重分布线路结构，移除该种子层120后，显露该铜层132，再以浸金方式沉积该金层300于该铜层132上。
请参阅图12及图13，在第四实施例中，以等离子体蚀刻方式移除该种子层120及部份该图案化介电层140后，各该线路130显露的该顶面130a及该侧面130b为该铜层132的顶面及侧面，因此该金层300是沉积于该铜层132的顶面及侧面。
以上所述，仅是本发明的较佳实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (15)

1.一种半导体装置的制造方法，其特征在于，包含：
提供封装结构，该封装结构包含第一载板、种子层、多个线路、晶粒及封胶材料，该种子层形成于该第一载板上，所述线路形成于该种子层上，该晶粒接合于所述线路，该封胶材料覆盖该晶粒及所述线路；
设置第二载板于该封胶材料上；
移除该第一载板，以显露该种子层；
移除该种子层，以显露所述线路；以及
以浸金方式沉积金层于各该线路上。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，各该线路包含镍层及铜层，该镍层以纯镍电镀方式形成于该种子层，该铜层形成于该镍层，移除该种子层后，显露该镍层，再以浸金方式沉积该金层于该镍层上。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于，各该线路包含铜层，该铜层形成于该种子层，移除该种子层后，显露该铜层，再以浸金方式沉积该金层于该铜层上。
4.根据权利要求1所述的半导体装置的制造方法，其特征在于，是以等离子体蚀刻方式移除该种子层。
5.根据权利要求1所述的半导体装置的制造方法，其特征在于，所述线路是借由图案化介电层形成于该种子层上，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露各该线路的顶面及侧面。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于，该金层沉积于各该线路的该顶面及该侧面。
7.根据权利要求1所述的半导体装置的制造方法，其特征在于，所述线路是借由图案化介电层形成于该种子层，各该线路包含镍层及铜层，该镍层以纯镍电镀方式形成于该种子层，该铜层形成于该镍层，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露该镍层的顶面及侧面。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，该金层沉积于该镍层的该顶面及该侧面。
9.根据权利要求1所述的半导体装置的制造方法，其特征在于，所述线路是借由图案化介电层形成于该种子层，各该线路包含铜层，该铜层形成于该种子层，以等离子体蚀刻方式移除该种子层及部份该图案化介电层后，显露该铜层的顶面及侧面。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于，该金层沉积于该铜层的该顶面及该侧面。
11.根据权利要求5或7或9所述的半导体装置的制造方法，其特征在于，该图案化介电层的蚀刻厚度不大于1.5μm。
12.根据权利要求1所述的半导体装置的制造方法，其特征在于，该第一载板包含基板及离型层，该离型层形成于该基板表面，该种子层形成于该离型层上，移除该基板及该离型层后，显露该种子层。
13.根据权利要求1所述的半导体装置的制造方法，其特征在于，该种子层为钛钨/铜层或钛/铜层。
14.根据权利要求2或3所述的半导体装置的制造方法，其特征在于，该铜层为重分布线路结构。
15.根据权利要求1所述的半导体装置的制造方法，其特征在于，在沉积该金层后，形成焊球于该金层上。
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