US20190035718A1 - Semiconductor device and method of forming a curved image sensor - Google Patents

Semiconductor device and method of forming a curved image sensor Download PDF

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Publication number
US20190035718A1
US20190035718A1 US16/148,563 US201816148563A US2019035718A1 US 20190035718 A1 US20190035718 A1 US 20190035718A1 US 201816148563 A US201816148563 A US 201816148563A US 2019035718 A1 US2019035718 A1 US 2019035718A1
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Prior art keywords
semiconductor device
base material
curved surface
substrate
semiconductor
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US16/148,563
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Michael J. Seddon
Francis J. Carney
Eric Woolsey
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Priority to US16/148,563 priority Critical patent/US20190035718A1/en
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CARNEY, FRANCIS J., SEDDON, MICHAEL J., WOOLSEY, ERIC
Publication of US20190035718A1 publication Critical patent/US20190035718A1/en
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAIRCHILD SEMICONDUCTOR CORPORATION, SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, FAIRCHILD SEMICONDUCTOR CORPORATION reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 048327, FRAME 0670 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
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    • H01L2924/30—Technical effects
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    • H01L2924/3511—Warping

Definitions

  • the present subject matter relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a curved image sensor.
  • Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Semiconductor devices perform a wide range of functions such as analog and digital signal processing, sensors, transmitting and receiving electromagnetic signals, controlling electronic devices, power management, and audio/video signal processing. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, diodes, rectifiers, thyristors, and power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, application specific integrated circuits (ASIC), standard logic, amplifiers, clock management, memory, interface circuits, and various signal processing circuits.
  • ASIC application specific integrated circuits
  • An image sensor is a type of semiconductor device that detects and records an image by converting the variable attenuation of light waves or electromagnetic radiation into electric signals.
  • An image sensor can be implemented with semiconductor charge-coupled devices (CCD) and active pixel sensors in complementary metal-oxide-semiconductor (CMOS) or N-type metal-oxide-semiconductor (NMOS) technologies with applications in digital cameras, video recorders, medical imaging equipment, night vision equipment, thermal imaging devices, radar, sonar, and other image detecting devices.
  • CCD semiconductor charge-coupled devices
  • CMOS complementary metal-oxide-semiconductor
  • NMOS N-type metal-oxide-semiconductor
  • the light source is typically focused onto a flat or planar image sensor surface through one or more optical lenses, e.g., up to four lenses.
  • the optical focusing lenses add cost, complexity, and height to the semiconductor package. Even with optical lenses, the focus is often better in the center region and less on the edges of the image sensor. Image sensors are continually driving towards higher resolution, faster focus times, better focus depth, lower profile, and lower cost.
  • FIG. 1 a shows a known image sensor die 50 with active imaging surface 52 disposed over substrate 54 having a curved surface 56 .
  • Image sensor die 50 is attached to curved surface 56 of substrate 54 with an epoxy.
  • Image sensor die 50 conforms to curved surface 56 with application of pressure and heat.
  • the epoxy is cured under pressure leaving image sensor die 50 molded to surface 56 a curved form factor, as shown in FIG. 1 b .
  • Image sensor die 50 in FIG. 1 b is difficult to manufacture in high volume due in part to the curved nature of substrate 54 , the curing process under pressure for the epoxy, the need to angle interconnecting bond wires, and lack of economies of scale.
  • the process of FIGS. 1 a -1 b is high cost and not amenable with batch processing or mass production.
  • FIGS. 1 a -1 b illustrate a known image sensor conforming to a curved surface of a substrate
  • FIGS. 2 a -2 b illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street
  • FIGS. 3 a -3 j illustrate a process of forming a concave surface image sensor area on a semiconductor die
  • FIG. 4 illustrates the semiconductor die with a concave surface image sensor area
  • FIG. 5 illustrates the semiconductor die with an image sensor area having a partial concave surface and partial planar surface
  • FIGS. 6 a -6 b illustrate a process of forming the concave surface image sensor area on substrate having a curved surface
  • FIGS. 7 a -7 b illustrate a process of forming the concave surface image sensor area on substrate having a recessed surface.
  • semiconductor die refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
  • Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer.
  • Each die on the wafer may contain active and passive electrical components and optical devices, which are electrically connected to form functional electrical circuits.
  • Active electrical components such as transistors and diodes, have the ability to control the flow of electrical current.
  • Passive electrical components such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
  • the optical device detects and records an image by converting the variable attenuation of light waves or electromagnetic radiation into electric signals.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation.
  • the wafer is singulated using plasma etching, laser cutting tool, or saw blade along non-functional regions of the wafer called saw streets or scribes.
  • the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package.
  • the electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds.
  • An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation.
  • the finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
  • FIG. 2 a shows semiconductor wafer 100 with a base substrate material 102 , such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support.
  • a plurality of semiconductor die 104 is formed on wafer 100 separated by a non-active, inter-die wafer area or saw street 106 , as described above.
  • Saw street 106 provides cutting areas to singulate semiconductor wafer 100 into individual semiconductor die 104 .
  • semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm) and thickness of 50-100 micrometers ( ⁇ m) or 15-250 ⁇ m.
  • FIG. 2 b shows a cross-sectional view of a portion of semiconductor wafer 100 .
  • Each semiconductor die 104 has a back or non-active surface 108 and an active surface or region 110 containing an image sensor area 112 implemented as CCD or active pixel sensors in CMOS or NMOS.
  • Active surface 110 with image sensor area 112 is a flat or planar surface in FIG. 2 b.
  • FIGS. 3 a -3 j illustrate a process of forming a concave surface image sensor area on semiconductor die 104 .
  • a masking layer 120 is formed over back surface 108 of each semiconductor die 104 while in the wafer form of FIG. 2 a .
  • Masking layer 120 can be made with photoresist or patterned oxide layer having openings 122 of varying width.
  • the width of openings 122 is larger in a center region of masking layer 120 and smaller toward the edges of masking layer 120 over each semiconductor die 104 .
  • the variable width of openings 122 in masking layer 120 exposes a larger area in the center region base substrate material 102 and exposes a decreasing area toward the edges of the base substrate material.
  • FIG. 3 b shows a top view of masking layer 120 with openings 122 of varying width disposed over base substrate material 102 .
  • semiconductor wafer 100 with masking layer 120 is mounted to film frame or backing tape 126 .
  • a plasma etching process is applied through openings 122 in masking layer 120 to remove a portion of back surface 108 of each semiconductor die 104 .
  • the plasma process uses a plasma die singulation tool. The plasma etching removes more base substrate material 102 in the wider openings 122 in the center region of semiconductor die 104 and less base substrate material in the smaller openings 122 toward the edges of the semiconductor die.
  • a higher volume of gas passes through the larger openings 122 in the center region of masking layer 120 , resulting in a higher degree of ion exposure and deeper etching in the center region of base substrate material 102 .
  • a lower volume of gas passes through the smaller openings 122 toward the edges of masking layer 120 , resulting in less ion exposure and shallower etching toward the edges of base substrate material 102 .
  • Masking layer 120 is removed by in-situ ashing in FIG. 3 d leaving deeper trenches 128 in the center region of base substrate material 102 and shallower trenches 128 toward the edges of the base substrate material, corresponding to the varying width openings 122 .
  • Trenches 128 are separated by peaks 130 of base substrate material 102 remaining after the plasma etching process through openings 122 and aligned with the solid portions of masking layer 120 , i.e., between openings 122 .
  • trenches 128 can be formed by laser direct ablation (LDA) or other wet or dry chemical etching process.
  • the plasma etching and in-situ ashing processes continue with lower intensity and without masking layer 120 to smooth out peaks 130 of base substrate material 102 .
  • Surface 132 of base substrate material 102 has reduced peaks and is beginning to exhibit a curved shape.
  • FIG. 3 f shows surface 134 of base substrate material 102 with the peaks substantially removed and exhibiting a generally curved or concave shape.
  • the plasma etching and in-situ ashing process on the back side of semiconductor die 104 is complete.
  • the thickness of base substrate material 102 at the low point of the curved surface 134 is 20-50 ⁇ m.
  • an optional metal layer 136 is conformally applied over curved or concave surface 134 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process.
  • metal layer 136 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), silver (Ag), titanium (Ti), titanium tungsten (TiW), or alloy or combination thereof.
  • Metal 136 can be solder, eutectic Sn/Pb, high-lead solder, or lead-free solder.
  • an adhesive such as an epoxy, is conformally applied to concave surface 134 .
  • Surface 134 and metal layer 136 have curved or concave shape.
  • semiconductor wafer 100 is singulated through saw street 106 into individual semiconductor die 104 using plasma etching.
  • Film frame 126 is removed.
  • Plasma etching has advantages of removing base substrate material 102 to form precision surfaces, while retaining the structure and integrity of the base substrate material.
  • the individual semiconductor die 104 can be inspected and electrically tested for identification of known good die post singulation.
  • semiconductor die 104 is inverted with the curved or concave surface 134 and metal layer 136 oriented toward substrate 140 .
  • the flat or planar active surface 110 is oriented away from substrate 140 .
  • Substrate 140 includes a flat or planar surface 142 and contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support.
  • a force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against planar surface 142 of substrate 140 .
  • Metal layer 136 reflows above 260° C.
  • base substrate material 102 exhibits a pliable property for asserting movement, bending, or flexing of the base substrate material.
  • metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product.
  • the force F asserts movement or flexing of base substrate material 102 to cause curved or concave surface 134 of base material 102 to switch or change orientation of surface 134 and metal layer 136 to a planar surface and active surface 110 to a concave surface.
  • the surface tension of metal layer 136 assists with drawing the center of base substrate material 102 to planar surface 142 of substrate 140 .
  • FIG. 3 j shows the resulting movement, bending, or flexing of base substrate material 102 and change of orientation to surface 134 and metal layer 136 exhibiting a flat or planar against substrate 140 and active surface 110 with image sensor area 112 now having a curved or concave surface.
  • the force F pressing surface 134 and metal layer 136 against planar surface 142 of substrate 140 , as well as the surface tension of metal layer 136 causes the movement or flexing of base substrate material 102 and change of orientation of planar active surface 110 in FIG. 3 i to the concave active surface 110 in FIG. 3 j . Vibration can also be used to enhance flexing of base substrate material 102 .
  • Metal layer 136 helps planarize and strengthen planar surface 134 after the change in orientation of base substrate material 102 . After the movement or flexing of base substrate material 102 under pressure and temperature, surface 134 and metal layer 136 is a planar surface and image sensor area 112 in active surface 110 now has the curved or concave shape. Base substrate material 102 with the curved or concave image sensor area 112 can be ultraviolet cured.
  • FIG. 4 shows semiconductor die 104 removed from substrate 140 by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping.
  • Image sensor area 112 in active surface 110 exhibits the curved or concave shape to reduce or eliminate the need for optical lenses.
  • Metal layer 136 is optionally removed. The process described in FIGS.
  • the light source focuses onto a curved or concave image sensor area 112 , without or with a reduced number of optical lenses, to provide higher resolution, faster focus times, better focus depth, lower profile, and lower cost.
  • FIG. 5 shows an alternate embodiment with the concave shape formed in a portion of active surface 110 .
  • Area 150 of active surface 110 remains a flat or planar surface and area 152 of the active surface is formed with the curved or concave shape, as described in FIGS. 3 a - 3 j.
  • FIG. 6 a shows an alternate embodiment with a curved shape 160 formed in substrate 162 .
  • Semiconductor die 104 is positioned over substrate 162 with concave metal layer 136 aligned with curved shape 160 , similar to FIG. 2 k .
  • Curved shape 160 assists with alignment of semiconductor die over substrate 162 .
  • a force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against curved surface 160 of substrate 162 .
  • Metal layer 136 reflows above 260° C. to provide flexibility and base substrate material 102 exhibits a pliable property for asserting movement, bending, or flexing of the base substrate material.
  • metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product.
  • the force F causes movement or flexing of base substrate material 102 and change of orientation of surface 134 and metal layer 136 to a convex shape and active surface 110 to a concave shape, as shown in FIG. 6 b.
  • FIG. 7 a shows an alternate embodiment with a recessed surface 170 formed in substrate 172 .
  • Semiconductor die 104 is positioned over substrate 172 and aligned with recessed surface 170 in substrate 172 , similar to FIG. 2 k .
  • a force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against recessed surface 170 of substrate 172 .
  • Metal layer 136 reflows above 260° C. to provide flexibility and base substrate material 102 exhibits a pliable property for asserting movement or flexing of the base substrate material. Once metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product.
  • the force F causes movement, bending, or flexing of base substrate material 102 in FIG. 7 b and change of orientation of surface 134 and metal layer 136 to a planar surface and active surface 110 to a curved or concave shape.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
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  • Plasma & Fusion (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Dicing (AREA)
  • Drying Of Semiconductors (AREA)
  • Led Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

Description

    CLAIM TO DOMESTIC PRIORITY
  • The present application claims the benefit of U.S. Provisional Application No. 62/219,666, filed Sep. 17, 2015, entitled “SEMICONDUCTOR PACKAGES AND METHODS” invented by Francis J. CARNEY and Michael J. SEDDON, and which is incorporated herein by reference and priority thereto for common subject matter is hereby claimed.
  • This application is a divisional application of the earlier U.S. Utility Patent Application to Michael J. Seddon entitled “Semiconductor Device and Method of Forming a Curved Image Sensor,” application Ser. No. 15/218,777, filed Jul. 25, 2016 now pending, the disclosure of which is hereby incorporated entirely herein by reference.
    • TECHNICAL FIELD
  • The present subject matter relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a curved image sensor.
    • BACKGROUND
  • Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Semiconductor devices perform a wide range of functions such as analog and digital signal processing, sensors, transmitting and receiving electromagnetic signals, controlling electronic devices, power management, and audio/video signal processing. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, diodes, rectifiers, thyristors, and power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, application specific integrated circuits (ASIC), standard logic, amplifiers, clock management, memory, interface circuits, and various signal processing circuits.
  • An image sensor is a type of semiconductor device that detects and records an image by converting the variable attenuation of light waves or electromagnetic radiation into electric signals. An image sensor can be implemented with semiconductor charge-coupled devices (CCD) and active pixel sensors in complementary metal-oxide-semiconductor (CMOS) or N-type metal-oxide-semiconductor (NMOS) technologies with applications in digital cameras, video recorders, medical imaging equipment, night vision equipment, thermal imaging devices, radar, sonar, and other image detecting devices.
  • The light source is typically focused onto a flat or planar image sensor surface through one or more optical lenses, e.g., up to four lenses. The optical focusing lenses add cost, complexity, and height to the semiconductor package. Even with optical lenses, the focus is often better in the center region and less on the edges of the image sensor. Image sensors are continually driving towards higher resolution, faster focus times, better focus depth, lower profile, and lower cost.
  • One approach to reducing the number of optical focusing lenses or eliminating the need for optical lenses is to make the image sensor with a curved surface. FIG. 1a shows a known image sensor die 50 with active imaging surface 52 disposed over substrate 54 having a curved surface 56. Image sensor die 50 is attached to curved surface 56 of substrate 54 with an epoxy. Image sensor die 50 conforms to curved surface 56 with application of pressure and heat. The epoxy is cured under pressure leaving image sensor die 50 molded to surface 56 a curved form factor, as shown in FIG. 1b . Image sensor die 50 in FIG. 1b is difficult to manufacture in high volume due in part to the curved nature of substrate 54, the curing process under pressure for the epoxy, the need to angle interconnecting bond wires, and lack of economies of scale. The process of FIGS. 1a-1b is high cost and not amenable with batch processing or mass production.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1a-1b illustrate a known image sensor conforming to a curved surface of a substrate;
  • FIGS. 2a-2b illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;
  • FIGS. 3a-3j illustrate a process of forming a concave surface image sensor area on a semiconductor die;
  • FIG. 4 illustrates the semiconductor die with a concave surface image sensor area;
  • FIG. 5 illustrates the semiconductor die with an image sensor area having a partial concave surface and partial planar surface;
  • FIGS. 6a-6b illustrate a process of forming the concave surface image sensor area on substrate having a curved surface; and
  • FIGS. 7a-7b illustrate a process of forming the concave surface image sensor area on substrate having a recessed surface.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
  • Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer may contain active and passive electrical components and optical devices, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions. The optical device detects and records an image by converting the variable attenuation of light waves or electromagnetic radiation into electric signals.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. The wafer is singulated using plasma etching, laser cutting tool, or saw blade along non-functional regions of the wafer called saw streets or scribes. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
  • FIG. 2a shows semiconductor wafer 100 with a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material for structural support. A plurality of semiconductor die 104 is formed on wafer 100 separated by a non-active, inter-die wafer area or saw street 106, as described above. Saw street 106 provides cutting areas to singulate semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm) and thickness of 50-100 micrometers (μm) or 15-250 μm.
  • FIG. 2b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface or region 110 containing an image sensor area 112 implemented as CCD or active pixel sensors in CMOS or NMOS. Active surface 110 with image sensor area 112 is a flat or planar surface in FIG. 2 b.
  • FIGS. 3a-3j illustrate a process of forming a concave surface image sensor area on semiconductor die 104. In FIG. 3a , a masking layer 120 is formed over back surface 108 of each semiconductor die 104 while in the wafer form of FIG. 2a . Masking layer 120 can be made with photoresist or patterned oxide layer having openings 122 of varying width. The width of openings 122 is larger in a center region of masking layer 120 and smaller toward the edges of masking layer 120 over each semiconductor die 104. The variable width of openings 122 in masking layer 120 exposes a larger area in the center region base substrate material 102 and exposes a decreasing area toward the edges of the base substrate material. FIG. 3b shows a top view of masking layer 120 with openings 122 of varying width disposed over base substrate material 102.
  • In FIG. 3c , semiconductor wafer 100 with masking layer 120 is mounted to film frame or backing tape 126. A plasma etching process is applied through openings 122 in masking layer 120 to remove a portion of back surface 108 of each semiconductor die 104. In one embodiment, the plasma process uses a plasma die singulation tool. The plasma etching removes more base substrate material 102 in the wider openings 122 in the center region of semiconductor die 104 and less base substrate material in the smaller openings 122 toward the edges of the semiconductor die. A higher volume of gas passes through the larger openings 122 in the center region of masking layer 120, resulting in a higher degree of ion exposure and deeper etching in the center region of base substrate material 102. A lower volume of gas passes through the smaller openings 122 toward the edges of masking layer 120, resulting in less ion exposure and shallower etching toward the edges of base substrate material 102. Masking layer 120 is removed by in-situ ashing in FIG. 3d leaving deeper trenches 128 in the center region of base substrate material 102 and shallower trenches 128 toward the edges of the base substrate material, corresponding to the varying width openings 122. Trenches 128 are separated by peaks 130 of base substrate material 102 remaining after the plasma etching process through openings 122 and aligned with the solid portions of masking layer 120, i.e., between openings 122. Alternatively, trenches 128 can be formed by laser direct ablation (LDA) or other wet or dry chemical etching process.
  • In FIG. 3e , the plasma etching and in-situ ashing processes continue with lower intensity and without masking layer 120 to smooth out peaks 130 of base substrate material 102. Surface 132 of base substrate material 102 has reduced peaks and is beginning to exhibit a curved shape.
  • Alternatively, a wet or dry chemical etch or LDA can be used to remove peaks 130. FIG. 3f shows surface 134 of base substrate material 102 with the peaks substantially removed and exhibiting a generally curved or concave shape. The plasma etching and in-situ ashing process on the back side of semiconductor die 104 is complete. The thickness of base substrate material 102 at the low point of the curved surface 134 is 20-50 μm.
  • In FIG. 3g , an optional metal layer 136 is conformally applied over curved or concave surface 134 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. In one embodiment, metal layer 136 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), silver (Ag), titanium (Ti), titanium tungsten (TiW), or alloy or combination thereof. Metal 136 can be solder, eutectic Sn/Pb, high-lead solder, or lead-free solder. Alternatively, an adhesive, such as an epoxy, is conformally applied to concave surface 134. Surface 134 and metal layer 136 have curved or concave shape.
  • In FIG. 3h , semiconductor wafer 100 is singulated through saw street 106 into individual semiconductor die 104 using plasma etching. Film frame 126 is removed. Plasma etching has advantages of removing base substrate material 102 to form precision surfaces, while retaining the structure and integrity of the base substrate material. The individual semiconductor die 104 can be inspected and electrically tested for identification of known good die post singulation.
  • In FIG. 3i , semiconductor die 104 is inverted with the curved or concave surface 134 and metal layer 136 oriented toward substrate 140. The flat or planar active surface 110 is oriented away from substrate 140. Substrate 140 includes a flat or planar surface 142 and contains sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. A force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against planar surface 142 of substrate 140. Metal layer 136 reflows above 260° C. to provide flexibility and base substrate material 102 exhibits a pliable property for asserting movement, bending, or flexing of the base substrate material. Once metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product. As the concave surface 134 and metal layer 136 contact planar surface 142 of substrate 140, the force F asserts movement or flexing of base substrate material 102 to cause curved or concave surface 134 of base material 102 to switch or change orientation of surface 134 and metal layer 136 to a planar surface and active surface 110 to a concave surface. The surface tension of metal layer 136 assists with drawing the center of base substrate material 102 to planar surface 142 of substrate 140.
  • FIG. 3j shows the resulting movement, bending, or flexing of base substrate material 102 and change of orientation to surface 134 and metal layer 136 exhibiting a flat or planar against substrate 140 and active surface 110 with image sensor area 112 now having a curved or concave surface. The force F pressing surface 134 and metal layer 136 against planar surface 142 of substrate 140, as well as the surface tension of metal layer 136, causes the movement or flexing of base substrate material 102 and change of orientation of planar active surface 110 in FIG. 3i to the concave active surface 110 in FIG. 3j . Vibration can also be used to enhance flexing of base substrate material 102. Metal layer 136 helps planarize and strengthen planar surface 134 after the change in orientation of base substrate material 102. After the movement or flexing of base substrate material 102 under pressure and temperature, surface 134 and metal layer 136 is a planar surface and image sensor area 112 in active surface 110 now has the curved or concave shape. Base substrate material 102 with the curved or concave image sensor area 112 can be ultraviolet cured.
  • FIG. 4 shows semiconductor die 104 removed from substrate 140 by chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical grinding, thermal bake, UV light, laser scanning, or wet stripping. Image sensor area 112 in active surface 110 exhibits the curved or concave shape to reduce or eliminate the need for optical lenses. Metal layer 136 is optionally removed. The process described in FIGS. 3a-3j , using plasma etching to form a concave surface in the back side of the base substrate material and then asserting movement, bending, or flexing of base substrate material 102 to change orientation of the base substrate material from a planar image sensor area to a concave image sensor area, provides a low cost, repeatable solution manufactureable in wafer form to mass produce a concave curved image sensor on a semiconductor die. The light source focuses onto a curved or concave image sensor area 112, without or with a reduced number of optical lenses, to provide higher resolution, faster focus times, better focus depth, lower profile, and lower cost.
  • FIG. 5 shows an alternate embodiment with the concave shape formed in a portion of active surface 110. Area 150 of active surface 110 remains a flat or planar surface and area 152 of the active surface is formed with the curved or concave shape, as described in FIGS. 3a -3 j.
  • FIG. 6a shows an alternate embodiment with a curved shape 160 formed in substrate 162. Semiconductor die 104 is positioned over substrate 162 with concave metal layer 136 aligned with curved shape 160, similar to FIG. 2k . Curved shape 160 assists with alignment of semiconductor die over substrate 162. A force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against curved surface 160 of substrate 162. Metal layer 136 reflows above 260° C. to provide flexibility and base substrate material 102 exhibits a pliable property for asserting movement, bending, or flexing of the base substrate material. Once metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product. As the concave surface 134 and metal layer 136 contact curved surface 160 of substrate 162, the force F causes movement or flexing of base substrate material 102 and change of orientation of surface 134 and metal layer 136 to a convex shape and active surface 110 to a concave shape, as shown in FIG. 6 b.
  • FIG. 7a shows an alternate embodiment with a recessed surface 170 formed in substrate 172. Semiconductor die 104 is positioned over substrate 172 and aligned with recessed surface 170 in substrate 172, similar to FIG. 2k . A force F is applied to planar active surface 110 of semiconductor die 104 with an elevated temperature of 260° C. or higher to press the concave surface 134 and metal layer 136 against recessed surface 170 of substrate 172. Metal layer 136 reflows above 260° C. to provide flexibility and base substrate material 102 exhibits a pliable property for asserting movement or flexing of the base substrate material. Once metal layer 136 is reflowed, it should not reflow again when the semiconductor package is mounted to the end product. As the concave surface 134 and metal layer 136 contact recessed surface 170 of substrate 172, the force F causes movement, bending, or flexing of base substrate material 102 in FIG. 7b and change of orientation of surface 134 and metal layer 136 to a planar surface and active surface 110 to a curved or concave shape.
  • While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.

Claims (20)

What is claimed:
1. A semiconductor device comprising:
a semiconductor die including a base material, the base material comprising a first planar surface and a second curved surface opposite the first planar surface;
wherein the second curved surface includes an image sensor area.
2. The semiconductor device of claim 1, wherein the first planar surface includes a metal layer thereon.
3. The semiconductor device of claim 1, wherein a portion of the second curved surface is planar.
4. The semiconductor device of claim 1, wherein the device is coupled to a substrate.
5. The semiconductor device of claim 4, wherein the substrate comprises a recessed surface.
6. The semiconductor device of claim 5, wherein the recessed surface is planar.
7. A semiconductor device comprising:
a semiconductor die including a base material, the base material comprising a first curved surface and a second curved surface opposite the first planar surface;
wherein the second curved surface includes an image sensor area.
8. The semiconductor device of claim 7, wherein the first planar surface includes a metal layer thereon.
9. The semiconductor device of claim 7, wherein a portion of the second curved surface is planar.
10. The semiconductor device of claim 1, wherein the device is coupled to a substrate.
11. The semiconductor device of claim 10, wherein the substrate comprises a recessed surface.
12. The semiconductor device of claim 11, wherein the recessed surface is curved.
13. A semiconductor device made by a process comprising the steps of:
providing a semiconductor die including a base material comprising a first surface and a second surface opposite the first surface;
applying a masking layer over the first surface of the base material, wherein the masking layer includes openings of varying width;
removing a portion of the first surface of the semiconductor die to form a first curved surface; and
asserting movement of the base material to change orientation of the second surface into a second curved surface.
14. The semiconductor device of claim 13, wherein the second surface of the base material includes an image sensor area.
15. The semiconductor device of claim 13, further including utilizing plasma etching to remove the portion of the first surface of the base material.
16. The semiconductor device of claim 13, wherein the masking layer is formed through one of a photoresist layer or a patterned oxide layer.
17. The semiconductor device of claim 13, further including disposing the semiconductor die on a substrate with the first curved surface oriented toward the substrate.
18. The semiconductor device of claim 13, further including:
providing a substrate;
disposing the semiconductor die over the substrate with the first curved surface oriented toward the substrate; and
applying pressure and temperature to assert movement of the base material to change orientation of the second surface into the second curved surface.
19. The semiconductor device of claim 18, wherein the substrate includes a curved surface
20. The semiconductor device of claim 18, wherein the substrate includes a recessed surface.
US16/148,563 2015-09-17 2018-10-01 Semiconductor device and method of forming a curved image sensor Abandoned US20190035718A1 (en)

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US15/218,777 Expired - Fee Related US10115662B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming a curved image sensor
US15/218,717 Abandoned US20170084545A1 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming an alignment structure in backside of a semiconductor die
US15/218,974 Active US10090233B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming micro interconnect structures
US15/218,848 Active US9852972B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of aligning semiconductor wafers for bonding
US15/231,025 Active US9935045B2 (en) 2015-09-17 2016-08-08 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
US15/244,979 Active US10014245B2 (en) 2015-09-17 2016-08-23 Method for removing material from a substrate using in-situ thickness measurement
US15/244,737 Active US10079199B2 (en) 2015-09-17 2016-08-23 Through-substrate via structure and method of manufacture
US15/614,840 Active US10163772B2 (en) 2015-09-17 2017-06-06 Stacked semiconductor device structure and method
US15/817,423 Active US10199316B2 (en) 2015-09-17 2017-11-20 Semiconductor device and method of aligning semiconductor wafers for bonding
US15/903,704 Active US10453784B2 (en) 2015-09-17 2018-02-23 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
US15/957,731 Abandoned US20180240742A1 (en) 2015-09-17 2018-04-19 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
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US15/218,777 Expired - Fee Related US10115662B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming a curved image sensor
US15/218,717 Abandoned US20170084545A1 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming an alignment structure in backside of a semiconductor die
US15/218,974 Active US10090233B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of forming micro interconnect structures
US15/218,848 Active US9852972B2 (en) 2015-09-17 2016-07-25 Semiconductor device and method of aligning semiconductor wafers for bonding
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US15/614,840 Active US10163772B2 (en) 2015-09-17 2017-06-06 Stacked semiconductor device structure and method
US15/817,423 Active US10199316B2 (en) 2015-09-17 2017-11-20 Semiconductor device and method of aligning semiconductor wafers for bonding
US15/903,704 Active US10453784B2 (en) 2015-09-17 2018-02-23 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
US15/957,731 Abandoned US20180240742A1 (en) 2015-09-17 2018-04-19 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
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