KR20060066952A - Ic chip having embedded bump and chip stack structure using the same - Google Patents

Abstract

The present invention relates to a bump embedded integrated circuit chip and a chip stack structure using the same. The bump embedded chip includes a circuit surface on which a predetermined circuit is formed, a recess formed on an opposite surface of the circuit surface, and a plurality of conductive bumps embedded in the recess. The chip stack structure is formed by the junction between the circuit surface of the first chip and the bump of the second chip. A protrusion may be formed on the circuit surface of the first chip, and the protrusion may be inserted into the recess of the second chip. The built-in bump structure, which places bumps in the recess, protects the bumps from external mechanical shocks, reducing bump size, absorbing bump thickness into the chip, making the chip stack structure thin and increasing the number of stacked chips. have.

Chip Lamination, Embedded Bumps, Wafer Surface Machining

Description

Integrated IC chip and chip stack structure using same {IC chip having embedded bump and chip stack structure using the same}

1 is a cross-sectional view illustrating a schematic structure of a bump embedded integrated circuit chip according to an exemplary embodiment of the present invention.

2 is a cross-sectional view illustrating a stacked structure of a bump embedded integrated circuit chip according to an exemplary embodiment of the present invention.

3 is a cross-sectional view comparing a conventional chip stack structure with the present invention.

4A through 4E are cross-sectional views illustrating a method of manufacturing a bump-embedded integrated circuit chip according to an exemplary embodiment of the present invention.

5 is a cross-sectional view illustrating a stacked structure of a bump embedded integrated circuit chip according to another exemplary embodiment of the present invention.

<Description of Reference Number Used in Drawing>

10, 10a, 10b, 40, 50, 60, 70: integrated circuit chip with bump

11, 11a, 11b, 41, 51, 61, 71: circuit surface

12, 12a, 12b, 42, 52a, 52b, 62, 72: conductive bump

13, 13a, 13b, 43, 53, 73a, 73b: recessed portion                 

14, 14a, 53a, 54, 64a, 64b: protrusions

20, 30, 80: chip stack structure

21: adhesive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacking technology for semiconductor integrated circuit devices, and more particularly, to a chip stacking technology using conductive bumps.

In order to achieve high integration of the system, researches for stacking integrated circuit chips using conductive bumps, particularly solder ball bumps, have been actively conducted. One of the issues in chip stacking technology is the problem of thinning of the laminated structure and the mechanical strength of bump bonding. In connection with this, researches on back lapping techniques for reducing the thickness of integrated circuit chips, techniques for reducing the size of conductive bumps, and techniques for improving the strength of bump junctions have been actively conducted.

The conventional chip stacking technique is to polish the back side of the wafer, cut it into individual chips, and then implement the interconnection between the upper and lower chips using solder ball bumps. However, since the solder ball bumps are vulnerable in terms of mechanical strength, they are frequently disconnected due to mechanical shocks from the outside and cracks from the inside.

In order to solve this problem, recently, a technique for improving bump bond strength by forming fine protrusions inside the bumps in advance has been proposed. However, because the size of the protrusions is relatively small compared to the bumps, the bumps containing the protrusions show a limit to the strong mechanical impact. This technique also has a fundamental disadvantage of not being able to reduce the size of the bump itself.

As described above, the conventional chip stack structure requires a reduction in the bump size in order to realize a thinning, but faces a problem in that the bump size cannot be reduced due to the decrease in the bump bonding strength.

Accordingly, an object of the present invention is to provide an integrated circuit chip and a chip stack structure using the same, which can reduce the size of the conductive bumps while improving the mechanical strength of the conductive bumps.

Another object of the present invention is to realize the thinning of the entire chip stack structure by minimizing the thickness of bumps in the chip stack structure.

It is still another object of the present invention to provide a chip stack structure capable of applying bumps of various sizes and suitable for multi-pin implementation.

In order to achieve these objects, the present invention provides a bump-embedded integrated circuit chip and a chip stack structure using the same.

An integrated circuit chip with a bump according to the present invention includes a circuit surface on which a predetermined circuit is formed, a recess formed at a predetermined depth on an opposite surface of the circuit surface, and a plurality of conductive bumps formed in the recess. do.                     

In the chip stack structure according to the present invention, a second integrated circuit chip is stacked on a first integrated circuit chip, and each of the integrated circuit chips includes a circuit surface on which a predetermined circuit is formed and a surface opposite to the circuit surface. And a plurality of conductive bumps formed in the concave portion, wherein the concave portion is formed to a depth of the concave portion, wherein the circuit surface of the first integrated circuit chip and the conductive bump of the second integrated circuit chip are bonded to each other. do.

In the chip stack structure according to the present invention, the first integrated circuit chip may further include a protrusion formed on the circuit surface, and the protrusion may be inserted into the recess of the second integrated circuit chip.

In addition, in the chip stack structure according to the present invention, a second integrated circuit chip is stacked on a first integrated circuit chip, and each of the integrated circuit chips has a circuit surface on which a predetermined circuit is formed and an opposite surface to the circuit surface. And a plurality of conductive bumps formed in the first integrated circuit chip, the first integrated circuit chip further comprising a first recess formed in the circuit surface, and a second recess formed in the conductive bumps. The chip further includes a protrusion in which the conductive bump is formed, the protrusion of the second integrated circuit chip is inserted into the first recess of the first integrated circuit chip, and the conductive of the second integrated circuit chip is formed. A bump and the circuit surface of the first integrated circuit chip are bonded.

Example

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

In describing the embodiments, descriptions of technical contents which are well known in the technical field to which the present invention belongs and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

For the same reason, some components in the accompanying drawings are exaggerated, omitted, or schematically illustrated, and the size of each component does not entirely reflect the actual size. The same or corresponding components in each drawing are given the same reference numerals.

1 is a cross-sectional view illustrating a schematic structure of a bump embedded integrated circuit chip 10 according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the integrated circuit chip 10 of the present exemplary embodiment includes a circuit surface 11 on which a circuit is formed, and a recess 13 in which bumps 12 are embedded. The integrated circuit chip 10 may be in a wafer state or in an individual chip state separated from the wafer. The circuit surface 11 means a circuit design surface formed through a general wafer manufacturing process. The circuit surface 11 may be of a flat surface, but when used in a chip stack structure, it may have a suitable protrusion 14, or may have a recess, as shown in other embodiments.

The bump 12 is formed of solder or a conductive material such as gold (Au) or nickel (Ni). The bump 12 is disposed in the recess 13 and may be formed to a size smaller than the depth of the recess 13. In the present specification, such an arrangement structure of the bump 12 is referred to as an embedded bump structure, and the integrated circuit chip 10 having the embedded bump structure is referred to as a bump embedded integrated circuit chip. The recessed part 13 points to the site | part formed in the predetermined | prescribed depth on the opposite surface of the circuit surface 11. The position, shape, and size of the recess 13 are not specified and may vary depending on the chip stack structure.

In this way, the built-in bump structure in which the bump 12 is disposed in the recess 13 can effectively protect the bump 12 from an external mechanical impact. Therefore, since the mechanical strength of the bump 12 is improved, the size of the bump 12 can be reduced. In addition, the built-in bump structure may absorb the thickness occupied by the bump 12 into the chip 10. Therefore, it is possible to reduce the overall thickness of the chip 10 in which the bumps 12 are formed, and this effect is more prominent in the chip stack structure described later. In addition, since the built-in bump structure can reduce the size of the bump 12, it is suitable for implementing a multi-pin, and can form bumps 12 of various sizes.

The bump embedded integrated circuit chip 10 having such a configuration is used for a chip stack structure. 2 is a cross-sectional view illustrating a stacked structure 20 of bump-embedded integrated circuit chips 10a and 10b according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a chip stack structure 20 using two bump embedded integrated circuit chips 10a and 10b is illustrated. The lower chip 10a and the upper chip 10b each include circuit surfaces 11a and 11b in which circuits are formed, and recesses 13a and 13b in which bumps 12a and 12b are embedded. The circuit surface 11a of the lower chip 10a has a protrusion 14a, and the circuit surface 11b of the upper chip 10b is a flat surface without the protrusion.

Further, the bump 12a of the lower chip 10a is somewhat larger than the depth of the recess 13a, while the bump 12b of the upper chip 10b is somewhat smaller than the depth of the recess 13b. . The reason why the bump 12a of the lower chip 10a is large is that the chip stack structure 20 serves as a final terminal when the chip stack structure 20 is mounted on an external substrate (not shown). On the other hand, the bump 12b size of the upper chip 10b is smaller than the depth of the recess 13b because the protrusion 14a of the lower chip 10a is inserted into the recess 13b of the upper chip 10b. can do.

As described above, the lower chip 10a and the upper chip 10b are stacked in such a manner that the protrusion 14a of the lower chip 10a is inserted into the recess 13b of the upper chip 10b. The bump 12b of the upper chip 10b is directly bonded to the circuit surface 11a of the lower chip 10a, and the bottom surface outside the recess 13b of the upper chip 10b is the circuit of the lower chip 10a. It adhere | attaches on the surface 11a through the adhesive layer 21.

In the chip stack structure 20 according to the present embodiment, bumps 12a and 12b of the respective chips 10a and 10b are not only embedded in the recesses 13a and 13b, but also the protrusions 14a of the lower chip 10a are upper part. Since the chip 10b is inserted into the recess 13b of the chip 10b, the thickness of the entire chip stack structure 20 is greatly reduced. Accordingly, the present invention can realize a thin chip stack structure 20 and increase the number of stacked chips 10a and 10b constituting the chip stack structure 20.

To illustrate this, FIG. 3 is illustrated. 3 is a cross-sectional view comparing the conventional chip stack structure 30 and 20 according to the present invention.

As shown in FIG. 3, the chip stack structure 30 according to the related art is a structure in which all four integrated circuit chips 31 having bumps are stacked. On the other hand, in the chip stack structure 20 according to the present invention, since the bump-embedded integrated circuit chip 10 absorbs the thickness occupied by the bumps, the individual chip thicknesses can be reduced by half as compared with the conventional technology. Therefore, the chip stack structure 20 of the present invention can implement the chip stack structure 20 having the same thickness as the prior art by using all eight chips 10.

Next, a method of manufacturing the bump embedded integrated circuit chip 10 according to the exemplary embodiment of the present invention will be described with reference to the accompanying drawings. The structure of the bump embedded integrated circuit chip 10 will also be clearer from the following description of the manufacturing method. 4A through 4E are cross-sectional views illustrating a method of manufacturing the bump-embedded integrated circuit chip 10 according to an exemplary embodiment of the present invention.

First, as shown in FIG. 4A, an integrated circuit chip 10 in a wafer state is prepared. The integrated circuit chip 10 includes a first surface 15 and a second surface 16, with no circuit formed yet. The integrated circuit chip 10 may be in a separate chip state separated from the wafer, but it is more preferable to proceed with the manufacturing process in the wafer state.

Subsequently, as shown in FIG. 4B, the first surface 15 of the integrated circuit chip 10 is processed into a predetermined pattern to form the protrusion 14. The machining process of the first surface 15 may be carried out using conventional surface etching techniques. That is, the protrusion 14 can be formed by etching away a portion 15a of the first surface 15. The protrusion 14 pattern is not specified and may be appropriately selected according to the chip stack structure.

Next, as shown in FIG. 4C, a general wafer fabrication process is performed to form the circuit surface 11 on the first surface 15. Of course, the circuit of the integrated circuit chip 10 is formed inside the chip, where the circuit surface 11 means a circuit design surface in a general sense.                     

When the wafer fabrication process is complete, as shown in FIG. 4D, the second surface 16 of the integrated circuit chip 10 is processed into a pattern to form a recess 13. The machining process of the second surface 16 may also be carried out using a general surface etching technique, and the recess 13 may be formed by etching and removing a portion 16a of the second surface 16. The recess pattern is also not specified and may be appropriately selected according to the chip stack structure.

Subsequently, as shown in FIG. 4E, a plurality of conductive bumps 12 are formed in the recess 13. As the bump 12 may be formed, electroplating or the like may be used as is well known. Although not shown in the drawing, an area, such as a bump pad, is formed in advance on the second surface 16a in the recess 13 to form the bump 12, and the bump pad is formed with the circuit of the integrated circuit chip 10. It is electrically connected. The electrical connection method may use existing techniques such as vias penetrating the inside of the chip or rerouting formed along the chip surface.

The stacked structure of the bump embedded integrated circuit chip of the present invention described above may have various aspects. 5 is one such example, and FIG. 5 is a cross-sectional view illustrating a stacked structure 80 of a bump embedded integrated circuit chip according to another exemplary embodiment of the present invention.

Referring to FIG. 5, the chip stack structure 80 of the present embodiment includes four stacked chips 40, 50, 60, and 70. Each of the stacked chips 40, 50, 60, and 70 has a slightly different form, but they are all the same in terms of using the bump embedded technology proposed in the present invention.                     

First, the first chip 40 located at the top includes a circuit surface 41 formed of a flat surface and a recess 43 in which the bumps 42 are embedded. The bumps 42 are somewhat smaller in size than the depths of the recesses 43 and all have a uniform size.

The second chip 50 located directly below the first chip 40 includes a protrusion 54 formed in the circuit surface 51 and a recess 53 in which bumps 52a and 52b are embedded. The circuit surface 51 above the protrusion 54 of the second chip 50 is joined to the bump 42 of the first chip 40, and the outside of the protrusion 54 is connected to the first chip through the adhesive 21. It is adhered to the bottom of the 40.

The recess 53 of the second chip 50 has a protrusion 53a that protrudes in some areas. Therefore, the bumps 52a and 52b embedded in the recess 53 of the second chip 50 have different sizes. Even if the bumps 52a and 52b of the second chip 50 have different sizes, all of them have a size smaller than the depth of the recess 53.

The third chip 60 located directly below the second chip 50 includes a first protrusion 64a formed on the circuit surface 61 and a second protrusion 64b on which the bump 62 is disposed. The circuit surface 61 above the first protrusion 64a of the third chip 60 is bonded to the bumps 52a and 52b of the second chip 50, and the outside of the first protrusion 64a is adhesive 21. ) Is adhered to the bottom surface of the second chip 50.

As shown in the example of the third chip 60, the integrated circuit chip itself used in the chip stack structure of the present invention does not necessarily have a recess for embedding bumps. Instead, it is possible to maintain a bump embedded form by forming recesses in neighboring integrated circuit chips.

The fourth chip 70 located directly below the third chip 60 includes a first recess 73b formed in the circuit surface 71 and a second recess 73a in which the bumps 72 are disposed. do. The first recess 73b of the fourth chip 70 accommodates the second protrusion 64b of the third chip 60, and the circuit surface 71 above the first recess 73b is the third chip. It is joined with the bump 62 of 60. The outer side of the first recess 73b is attached to the bottom surface of the third chip 60 through the adhesive 21.

The bump 72 of the fourth chip 70 located at the bottom serves as a final terminal when the chip stack structure 80 is mounted on an external substrate (not shown) or the like, so that the depth of the second recess 73a is greater than the depth of the second recess 73a. It is desirable to form a rather large size.

As can be seen from the embodiment described above, in the chip stack structure of the present invention, it is not important on which chip the recesses incorporating the bumps are formed. It is only sufficient if the result is that the bumps are accommodated in the recesses in the laminated structure.

As described through the embodiments up to now, the chip stack structure using the bump embedded chip according to the present invention can expect various effects as follows by using wafer surface processing and bump embedded.

First, the built-in bump structure, which places the bumps in the recesses, can effectively protect the bumps from external mechanical impacts. Therefore, the mechanical strength of the bumps is improved, so that the size of the bumps can be greatly reduced.

Second, the built-in bump structure can absorb the thickness occupied by the bump into the chip. Therefore, the entire thickness of the chip on which the bumps are formed can be reduced, and the thickness of the entire chip stack structure can be greatly reduced. Therefore, the chip stack structure can be reduced, and the number of stacked chips can be increased.                     

Third, the built-in bump structure can reduce the size of the bumps, which makes it suitable for multi-pin implementation.

Fourth, since various types of recesses or protrusions can be formed using surface processing, bumps of various sizes can be applied.

In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (4)

A bump embedded integrated circuit chip comprising a circuit surface on which a predetermined circuit is formed, a recess formed in a predetermined depth on an opposite surface of the circuit surface, and a plurality of conductive bumps formed in the recess. In a chip stack structure in which a second integrated circuit chip is stacked on a first integrated circuit chip, Each of the integrated circuit chips includes a circuit surface on which a predetermined circuit is formed, a recess formed at a predetermined depth on an opposite surface of the circuit surface, and a plurality of conductive bumps formed in the recess, And the circuit surface of the first integrated circuit chip and the conductive bump of the second integrated circuit chip are bonded. The method of claim 2, And the first integrated circuit chip further includes a protrusion formed on the circuit surface, wherein the protrusion is inserted into the recess of the second integrated circuit chip. In a chip stack structure in which a second integrated circuit chip is stacked on a first integrated circuit chip, Each of the integrated circuit chips includes a circuit surface on which a predetermined circuit is formed and a plurality of conductive bumps formed on opposite surfaces of the circuit surface, The first integrated circuit chip further includes a first recessed portion formed on the circuit surface, and a second recessed portion formed with the conductive bumps. The second integrated circuit chip further includes a protrusion on which the conductive bumps are formed. The protrusion of the second integrated circuit chip is inserted into the first recess of the first integrated circuit chip, and the conductive bump of the second integrated circuit chip and the circuit surface of the first integrated circuit chip are joined. Chip stack structure, characterized in that.

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