CN102543911A - 半导体装置 - Google Patents
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
本发明公开一种半导体装置,其包括一硅基板、多个硅纳米线束、一第一线路层以及一第二线路层。硅基板具有相对的一第一表面与一第二表面及多个贯孔。这些硅纳米线束分别配置于硅基板上的贯孔。第一线路层配置于第一表面并电连接硅纳米线束。第二线路层配置于第二表面并电连接硅纳米线束。
Description
技术领域
本发明涉及一种半导体装置,且特别是涉及一种具有热电冷却机制的半导体装置。
背景技术
未来封装制作工艺的趋势将朝向高功率、高密度、低成本、轻、薄、短、小等高精密度制作工艺发展,而三维堆叠式芯片(3D stacked IC)的技术便是以此为目的,其中最严重的挑战之一就是热的问题。三维堆叠式芯片内局部高温区的形成与热点(hot spot),造成温度与应力集中现象并衍生热应力问题,进而影响其产品可靠度,成为三维堆叠式芯片技术的瓶颈。根据研究指出,热点问题会造成芯片的散热需求大幅提升,使得散热元件的热阻值需要更为降低,甚至高达2~3倍,造成严重的散热效率不足的问题。然而,三维堆叠式芯片中所面临的散热效率不足的问题更为严重。由于芯片堆叠时发热密度提高,所以单位面积所产生的热量也加大。因此,如何在三维堆叠式芯片内细微的尺度中将芯片产生的热迅速导出是很重要的议题。
利用热电半导体材料制作的热电元件由于不需使用任何液体、气体作为冷却剂,且具有可连续工作、无污染、无动件、无噪音、寿命长、且体积小重量轻等优点。因此此种热电元件被广泛的应用在冷却或加热装置上。然而,传统热电元件体积较大,且需独立的供电线路,因此仅能附加在三维堆叠式芯片的外部,仍然难以有效地帮助内部的高温区进行散热。
发明内容
本发明的目的在于提供一种半导体装置,可解决高密度封装元件的散热效率不足的问题。
本发明的半导体装置包括一硅基板、多个硅纳米线束、一第一线路层以及一第二线路层。硅基板具有相对的一第一表面与一第二表面及多个贯孔。这些硅纳米线束分别配置于这些贯孔。第一线路层配置于第一表面并电连接硅纳米线束。第二线路层配置于第二表面并电连接硅纳米线束。
基于上述,在本发明的半导体装置中,利用直接形成在硅基板内的硅纳米线束构成热电冷却机制,易于对三维堆叠式芯片内部的高温区散热。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1是本发明一实施例的半导体装置的剖示图;
图2A至图2G说明形成硅纳米线束与穿硅通孔的制作工艺;
图3是本发明另一实施例的半导体装置的示意图;
图4是本发明再一实施例的半导体装置的示意图;
图5是本发明又一实施例的半导体装置的示意图;
图6是本发明另一实施例的半导体装置的示意图;
图7是本发明再一实施例的半导体装置的示意图;
图8是本发明又一实施例的半导体装置的示意图。
主要元件符号说明
100、200、300、400、500、600、700:半导体装置
110、320、710:硅基板
112:第一表面
114:第二表面
116、P12、P14:贯孔
120:硅纳米线束
122:纳米银粒子
130:第一线路层
140:第二线路层
150:绝缘填充材
160、312、322、712:穿硅通孔
170:集成电路单元
180:绝缘层
L10、L12:二氧化硅层
50:承载基板
210、310:芯片
212、222、224、232、314、316、324、326:线路层
220:有机载板
230:电路板
240:凸块
328:导线
510:底胶材
610:散热片
612:导热件
714:重布线路
具体实施方式
图1是本发明一实施例的半导体装置的剖示图。请参照图1,本实施例的半导体装置100包括一硅基板110、多个硅纳米线束120、一第一线路层130以及一第二线路层140。硅基板110具有相对的一第一表面112与一第二表面114及多个贯孔116。每个硅纳米线束120配置于一个贯孔116。第一线路层130配置于第一表面112并电连接硅纳米线束120。第二线路层140配置于第二表面114并电连接硅纳米线束120。
在本实施例中,硅纳米线束120例如是直接以硅基板110制作而成。每个硅纳米线束120例如是P型纳米线束或N型纳米线束。电流通过第一线路层130、第二线路层140以及P型与N型的硅纳米线束120后,可产生热电效应而带走靠近第一线路层130或第二线路层140的一侧的热量,用于达成散热的目的。由于本实施例的硅纳米线束120直接配置于硅基板110内,并可利用硅基板110表面的线路层构成所需的电流路径,因此本实施例的半导体装置100可在有限体积中获得极佳的散热效率。甚至,本实施例的半导体装置100可应用在三维堆叠式芯片中,将硅纳米线束120配置在三维堆叠式芯片内部的高温区周围,有效地对高温区进行散热而提升三维堆叠式芯片的可靠度。本实施例中的所有硅纳米线束120都彼此串连而构成单一热电元件。然而,硅纳米线束120也可分成多组而构成各自独立的多个热电元件,且每个热电元件的冷端可以是靠近第一线路层130或第二线路层140,以尽量靠近热源为主,在设计上具有极大的灵活性。
本实施例的半导体装置100还包括一绝缘填充材150,其填充于贯孔116。具体而言,绝缘填充材150是填充在贯孔116的孔壁以及硅纳米线束120的各条硅纳米线之间,用于适当地固定硅纳米线束120。绝缘填充材150例如是二氧化硅或其他绝缘材质。然而,硅纳米线束120的各条硅纳米线之间并不一定要填入绝缘填充材150,也可以通过空气达到绝缘效果。本实施例的半导体装置100还包括至少一穿硅通孔(through silicon via,TSV)160,贯穿硅基板110并电连接第一线路层130与第二线路层140。本实施例以多个穿硅通孔160为例。穿硅通孔160用以电连接第一线路层130与第二线路层140,不仅可用于信号传递,也可用电连接硅纳米线束120以作为硅纳米线束120的供电线路。因此,即使硅纳米线束120被配置在三维堆叠式芯片的内部,也可通过穿硅通孔160获得所需的电力而不需难以整合在三维堆叠式芯片中的附加式供电线路,大幅提高了实用性。利用内埋的硅纳米线束120进行散热,还减少了传统散热元件需外加或贴附于外部所造成的接触热阻等问题。
本实施例的半导体装置100还包括至少一集成电路单元170与一绝缘层180,本实施例以两个集成电路单元170与两个绝缘层180为例。两个集成电路单元170都配置于第一表面112,且一个绝缘层180覆盖170集成电路单元。第一线路层130配置于绝缘层170上,并经由绝缘层170的几个开口电连接集成电路单元170与硅纳米线束120。另一绝缘层180则配置于第二表面114与第二线路层140之间。本实施例的集成电路单元170可以是逻辑电路单元、记忆体单元或其他集成电路单元。换言之,本实施例的半导体装置100可以是各种具有单一功能或多功能的芯片。每个集成电路单元170并不限定如图1所示般集中在特定区域,也可能散布在第一表面112上的许多区域。
图2A至图2G说明形成硅纳米线束与穿硅通孔的制作工艺。请参照图2A,首先在硅基板110上利用光刻蚀刻制作工艺形成图案化的二氧化硅层L10,并以二氧化硅层L10为掩模而蚀刻出两种深度的贯孔P12与P14。硅基板110通常已在晶片厂完成所需的集成电路单元,并预留部分区域未配置集成电路单元或其他线路,以便在后续制作工艺中可形成贯孔。接着参照图2B,在贯孔P12中依序填入绝缘材料(例如二氧化硅)与金属,并在贯孔P14涂布多个纳米银粒子122。接着参照图2C,利用氢氟酸等溶液对贯孔P14内的纳米银粒子122(绘示于图2B)下方的硅基板110进行无电镀化学蚀刻,即可形成许多硅纳米线所构成的硅纳米线束120。
接着参照图2D,移除贯孔P14内的纳米银粒子122(绘示于图2C),并利用光刻蚀刻及电镀制作工艺形成第一线路层130。第一线路层130同时连接贯孔P12中的金属与贯孔P14内的硅纳米线束120。接着参照图2E,将一承载基板50配置于硅基板110上并与第一线路层130接合。接着参照图2F,从硅基板110的底部薄化硅基板110,直到露出贯孔P12中的金属与贯孔P14内的硅纳米线束120。接着参照图2G,在硅基板110的第二表面114形成第二线路层140。在形成第二线路层140前,还可在硅基板110的第二表面114上形成图案化的二氧化硅层L12。二氧化硅层L12用以避免第二线路层140直接接触硅基板110。其中,第二线路层140连接贯孔P12中的金属与贯孔P14内的硅纳米线束120,而贯孔P12中的金属就是图1的穿硅通孔160。之后,只要移除承载基板50就可形成类似图1的半导体装置。若有需要,也可在移除承载基板50之前进行凸块制作工艺以形成凸块(未绘示)。应注意的是,以上制作工艺中所采用的制作工艺方法及材料都仅用于举例,并非用以限定本发明。
前述实施例采用化学蚀刻所形成的纳米线结构具有粗糙表面,有助于降低热传导系数,而可提升热电材料的热电优质系数(thermoelectric figure ofmerit,ZT值)。由于纳米线结构带有粗糙表面,能大幅增加声子(phonon)在材料中传递的散射机率,降低声子的自由平均路径,因此可以大幅降低热传导系数,提升热电材料的ZT值。
一般而言,传统的硅材料具有极高的导热系数,约为150W/m-K,但热电特性不佳。然而,线径为50纳米且具有粗糙表面的低尺度纳米线结构,其热传导系数可达到硅块材的1/100,ZT值可达0.6以上。因此,低尺度的纳米线结构具有提升热电性能的潜力。虽然单一纳米线在热电性能上有其优势,但是单一纳米线在实际应用上有其困难度与限制。本实施例以硅基板(如硅晶片)直接进行化学蚀刻即可获得包含硅纳米线束的热电元件组。经实验量测得知,目前尚未经线径均匀性控制的纳米线结构,其热传导系数为55~68W/m-K,约为硅块材的1/2。
简言之,采用本实施例的硅纳米线束可以达到以下优点。首先,硅纳米线束可以提供较佳的热电转换效率与输出功率。再者,由于基板与硅纳米线束是以同一硅基板制作而成,因此基材与硅纳米线束之间具有较低的介面电阻与热阻。此外,硅材质的P型与N型掺杂技术成熟,易于控制。另外,以无电镀化学蚀刻法来制作纳米线结构,可在硅基板上同时制作大面积与大量的硅纳米线束,且相容于穿硅通孔的制作工艺,有助于降低制作成本。
以下,举例说明数种应用本发明的技术的三维堆叠式芯片的架构,但其中各种增加的元件当可依需求而以其他方式进行组合。
图3是本发明另一实施例的半导体装置的示意图。请参照图3,本实施例的半导体装置200包括大致相同于图1的半导体装置100、一芯片210、一有机载板220与一电路板230。电路板230具有一线路层232。有机载板220具有线路层222与224。芯片210具有一线路层212。半导体装置100的第一线路层130可经由多个凸块240或其他元件而电连接芯片210的线路层212。半导体装置100的第二线路层140经由多个凸块240或其他元件而电连接有机载板220的线路层222。有机载板220的线路层222电连接线路层224。有机载板220的线路层224经由多个凸块240或其他元件而电连接电路板230的线路层232。本实施例的半导体装置100的硅纳米线束120可将集成电路单元170所产生的热量带走,并经由线路层与凸块向外带出。而且,本实施例的半导体装置100的硅纳米线束120还可以帮忙对芯片210进行散热。硅纳米线束120所需的电力可从电路板230处供应。
图4是本发明再一实施例的半导体装置的示意图。请参照图4,本实施例的半导体装置300包括大致相同于图1的半导体装置100、芯片310、有机载板220、一硅基板320与电路板230。本实施例的半导体装置300与图3的半导体装置200的差异在于芯片310与硅基板320。芯片310具有穿硅通孔312、线路层314与线路层316,穿硅通孔312电连接线路层314与线路层316。硅基板320具有穿硅通孔322、线路层324与线路层326,穿硅通孔322电连接线路层324与线路层326。半导体装置100的第二线路层140经由凸块240或其他元件而电连接硅基板320的线路层324。硅基板320的线路层326经由凸块240或其他元件而电连接有机载板220的线路层222。有机载板220的线路层222电连接线路层224。有机载板220的线路层224经由多个凸块240或其他元件而电连接电路板230的线路层232。
图5是本发明又一实施例的半导体装置的示意图。请参照图5,本实施例的半导体装置400与图4的半导体装置300相似,差异在于硅基板320的线路层324是利用至少一条导线328电连接有机载板220的线路层222。
图6是本发明另一实施例的半导体装置的示意图。请参照图6,本实施例的半导体装置500与图4的半导体装置300相似,差异在于半导体装置500中没有有机载板。硅基板320的线路层326经由凸块240或其他元件而电连接电路板230的线路层232,且硅基板320与电路板230之间填充有底胶材510。
图7是本发明再一实施例的半导体装置的示意图。请参照图7,本实施例的半导体装置600与图6的半导体装置500相似,差异在于半导体装置600还增加一散热片610。散热片610配置于芯片310上。半导体装置100的硅纳米线束120将集成电路单元170所产生的热量带走后,可经由芯片310的穿硅通孔312而将热量传递至散热片610以提升散热效率。散热片610与芯片310的穿硅通孔312之间可利用线路层314与导热件612进行热传递。线路层314用于热传递的部分例如仅用于传递热量而不用于传递电力或电信号,导热件612可以跟凸块240以同一制作工艺形成。
图8是本发明又一实施例的半导体装置的示意图。请参照图8,本实施例的半导体装置700与图6的半导体装置500相似,但穿硅通孔712的一端仅连接到硅基板710的一侧的重布线路714。
综上所述,在本发明的半导体装置中,是将构成热电冷却机制的硅纳米线束直接形成在硅基板内,亦即可直接形成在芯片内。因此,可对单一芯片或三维堆叠式芯片内部的高温区散热。此外,利用穿硅通孔做为硅纳米线束所需的供电路径,可让硅纳米线束配置在三维堆叠式芯片的内部而不需烦恼如何设计供电路径。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (17)
1.一种半导体装置,包括:
第一硅基板,具有相对的一第一表面与一第二表面及多个贯孔;
多个硅纳米线束,分别配置于该些贯孔;
第一线路层,配置于该第一表面并电连接该些硅纳米线束;以及
第二线路层,配置于该第二表面并电连接该些硅纳米线束。
2.如权利要求1所述的半导体装置,还包括绝缘填充材,其填充于该些贯孔。
3.如权利要求1所述的半导体装置,其中该些硅纳米线束分别为P型纳米线束或N型纳米线束。
4.如权利要求1所述的半导体装置,还包括至少一穿硅通孔,贯穿该第一硅基板并电连接该第一线路层与该第二线路层。
5.如权利要求4所述的半导体装置,其中该穿硅通孔电连接该些硅纳米线束。
6.如权利要求1所述的半导体装置,还包括至少一集成电路单元与绝缘层,配置于该第一表面,其中该绝缘层覆盖该集成电路单元,该第一线路层配置于该绝缘层上并电连接该集成电路单元。
7.如权利要求1所述的半导体装置,还包括电路板,具有第三线路层,其中该第二线路层电连接该第三线路层。
8.如权利要求7所述的半导体装置,其中该第二线路层经由多个凸块电连接该第三线路层。
9.如权利要求8所述的半导体装置,还包括有机载板,其中该第二线路层依序经由部分该些凸块、该有机载板与其他该些凸块电连接该第三线路层。
10.如权利要求8所述的半导体装置,还包括第二硅基板,其中该第二线路层依序经由部分该些凸块、该第二硅基板与其他该些凸块电连接该第三线路层。
11.如权利要求10所述的半导体装置,其中该第二硅基板具有至少一穿硅通孔,该第二线路层依序经由部分该些凸块、该穿硅通孔与其他该些凸块电连接该第三线路层。
12.如权利要求10所述的半导体装置,还包括有机载板,其中该第二线路层依序经由部分该些凸块、该第二硅基板、该有机载板与其他该些凸块电连接该第三线路层。
13.如权利要求12所述的半导体装置,其中该第二硅基板具有至少一穿硅通孔,该第二线路层依序经由部分该些凸块、该穿硅通孔、另一部分该些凸块、该有机载板与其他该些凸块电连接该第三线路层。
14.如权利要求12所述的半导体装置,其中该第二硅基板具有至少一导线,该第二线路层依序经由部分该些凸块、该导线、该有机载板与其他该些凸块电连接该第三线路层。
15.如权利要求1所述的半导体装置,还包括芯片,配置于该第一硅基板的该第一表面,并电连接该第一线路层。
16.如权利要求15所述的半导体装置,还包括散热片,其中该芯片位于该第一硅基板与该散热片之间且具有至少一穿硅通孔,该穿硅通孔热接触该些硅纳米线束与该散热片。
17.如权利要求1所述的半导体装置,还包括散热片,配置于该第一硅基板的该第一表面并热接触该些硅纳米线束。
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TWI441305B (zh) | 2014-06-11 |
US8674491B2 (en) | 2014-03-18 |
US20120153454A1 (en) | 2012-06-21 |
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