WO2017107480A1 - 一种热电制冷模块、集成光接口芯片和通信设备 - Google Patents

一种热电制冷模块、集成光接口芯片和通信设备 Download PDF

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Publication number
WO2017107480A1
WO2017107480A1 PCT/CN2016/091088 CN2016091088W WO2017107480A1 WO 2017107480 A1 WO2017107480 A1 WO 2017107480A1 CN 2016091088 W CN2016091088 W CN 2016091088W WO 2017107480 A1 WO2017107480 A1 WO 2017107480A1
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Prior art keywords
substrate
pad
chip
guiding block
guiding
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PCT/CN2016/091088
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English (en)
French (fr)
Inventor
杨成鹏
付星
李泉明
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华为技术有限公司
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Publication of WO2017107480A1 publication Critical patent/WO2017107480A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/82—Connection of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects

Definitions

  • the present invention relates to the field of optoelectronic communication technologies, and in particular, to a thermoelectric cooler (TEC), an integrated optical interface (IOI) chip, and a communication device.
  • TEC thermoelectric cooler
  • II integrated optical interface
  • the IOI chip that is, the opto-electronic hybrid chip, integrates the optical chip and the electric chip, realizes the logic processing of the data through the electric chip, and realizes the high-speed interconnection through the light output of the optical chip.
  • a side view of an IOI chip is shown in FIG. 1 , wherein the IOI chip in FIG. 1 includes a main substrate, an optical chip, and an electric chip, the electric chip is located above the optical chip, between the electric chip and the optical chip, and the electric chip
  • the substrate may be connected to the substrate by solder balls; in addition, the IOI chip further includes a chip cover or the like.
  • the temperature of the shell of the IOI chip is generally low.
  • the junction temperature of the optical chip generally does not exceed 85 ° C, due to the thermal resistance of the heat transfer path, the shell temperature of the IOI chip is only about 70 ° C; wherein, as a comparison, the junction temperature of the electric chip reaches 105 ° C, the same work
  • the temperature of the shell of the same size can reach 90 °C. Due to the complex function of the IOI chip, its power consumption is relatively large. The large power consumption makes the IOI chip difficult to dissipate heat.
  • Embodiments of the present invention provide a TEC, an IOI chip, and a communication device for achieving rapid heat dissipation.
  • an embodiment of the present invention provides a TEC, including: a first substrate and a second substrate, wherein the first substrate and the second substrate are oppositely disposed;
  • At least one first pad is disposed on an outer surface of the first substrate, and at least one second pad is disposed on an outer surface of the second substrate;
  • At least one first guiding block is embedded on the first substrate, and at least one second guiding block is embedded in the second substrate;
  • At least one connecting member is disposed between the first substrate and the second substrate; the first pad is signal-connected to the connecting member via the first guiding block, and the second pad is signal-connected to the connecting member via the second guiding block;
  • thermoelectric refrigeration module further includes at least one thermoelectric element; the at least one thermoelectric element is fixed between the first substrate and the second substrate; wherein the at least one thermoelectric element is used to exotherm one end of the heat absorption end when energized, so that the first A temperature difference is generated between the substrate and the second substrate; any one of the thermoelectric elements and any one of the connecting members are not electrically connected to each other.
  • the TEC provided by the embodiment of the invention includes a thermoelectric element fixed between the first substrate and the second substrate.
  • the thermocouple When the thermocouple is energized, one end absorbs heat at one end, so that a temperature difference is generated between the first substrate and the second substrate. (ie, forming the hot end and the cold end of the TEC, or forming the hot side and the cold side of the TEC); through the first guiding block embedded in the first substrate, the connecting member fixed between the first substrate and the second substrate, And a second guiding block embedded in the second substrate, implementing a signal connection between the first pad disposed on the outer surface of the first substrate and the second pad disposed on the outer surface of the second substrate, thereby implementing TEC Signal interconnection between the two ends.
  • the TEC when the TEC is set in the IOI chip, the heat dissipation speed of the IOI chip can be increased.
  • thermoelectric element is fixed between the first substrate and the second substrate by a baffle attached to an inner surface of the first substrate and a baffle attached to an inner surface of the second substrate.
  • the embodiment of the present invention provides the following An optional technical solution:
  • the first pad and the first guiding block can be directly connected; similarly, the second pad and the second guiding block can be directly connected.
  • the first pad is connected to the connecting component via the first guiding block, and specifically includes: the first pad passing through the first routing and the first guiding The block has a signal connection, and the first guide block has a signal connection with the connecting member.
  • the second pad is connected to the connecting component via the second guiding block, and may include: the second pad passing through the second trace and the second lead, in the optional implementation 2
  • the block has a signal connection
  • the second guide block has a signal connection with the connecting member.
  • connection pads and the connection components are connected by wires, so that the same pads can be connected to the connection components through different traces, and the specific implementation can be implemented according to Actual layout layout is required.
  • surface wiring or multilayer wiring can be performed according to actual conditions. The wiring width and spacing can be adjusted according to the rate of the transmitted electrical signal. Therefore, it has the beneficial effect of achieving flexibility.
  • the first pad is connected to the connecting component via the first guiding block, and specifically includes: a first pad and a first guiding block have signals Connected, the first guiding block has a signal connection with the connecting component.
  • a first pad and a first guiding block are connected to a signal, and specifically, a first pad passes through the first The line is signaled to a first lead block.
  • the second pad is connected to the connecting component via the second guiding block, and specifically includes: a second pad and a second guiding block have signals Connected, the second guide block has a signal connection with the connecting member.
  • a second pad is connected to a second guiding block, and specifically, a second pad passes through the second The line is signaled to a second lead block.
  • a signal connection is provided between a pad and a guiding block, so that the utility model has the advantages of simple implementation and convenient maintenance.
  • the first pad is connected to the connecting component via the first guiding block, and specifically includes: a plurality of first pads and a first level of the same level A guiding block has a signal connection, and the first guiding block has a signal connection with the connecting component.
  • first pads of the same level are connected to a first conductive block, which may be: the same level.
  • the plurality of first pads are signally coupled to one of the first vias via one or more first traces.
  • the second pad is connected to the connecting component via the second guiding block, and specifically includes: a plurality of second pads and a first level of the same level
  • the two guiding blocks have a signal connection
  • the second guiding block has a signal connection with the connecting member.
  • multiple second pads of the same level are connected to a second conductive block, which may be: the same level.
  • the plurality of second pads are signally coupled to one of the second vias via one or more second traces.
  • a signal connection is provided between the plurality of pads and one of the guiding blocks, so that the number of the connecting members can be reduced, and the TEC heat backflow can be reduced, thereby reducing the TEC. Power consumption.
  • the first pad is connected to the connecting component via the first guiding block, and specifically includes: a plurality of first pads of the same level Or a plurality of first guiding blocks are connected to one connecting member.
  • the second pad is connected to the connecting component via the second guiding block, and specifically includes: a plurality of second pads of the same level Or a plurality of second guiding blocks are connected to one connecting member.
  • At least one connecting member is distributed around the periphery of at least one of the thermoelectric elements.
  • thermoelectric element is distributed around the periphery of at least one of the connecting members.
  • thermoelectric element is staggered with at least one connecting member.
  • the first option reduces the amount of thermal backflow between the TEC ends, which reduces the TEC's own power consumption.
  • the second alternative can reduce the propagation path of the high frequency electrical signal flowing into the first pad (or the second pad) through the TEC, thereby reducing the delay and attenuation caused by the high frequency signal.
  • the third alternative method can combine the advantages of the first mode and the second mode described above, and can effectively utilize the space of the TEC substrate to reduce the area of the TEC.
  • At least one third guiding block is embedded on the first substrate and/or the second substrate further comprises at least one third guiding block; at least one thermoelectric element power supply. At least one thermoelectric element is supplied via the third guiding block.
  • the optional implementation provides the third conductive block on the first substrate and/or the second substrate, thereby supplying the at least one thermoelectric element through the third guiding block, and the prior art through the first substrate
  • the wires are guided outwardly between the second substrates, so that the utility model has the advantages of simple implementation and convenient operation compared with the power supply of the thermoelectric elements.
  • the first base station is embedded There are a plurality of first guiding blocks, and any two first guiding blocks are not electrically connected to each other; and/or a plurality of second guiding blocks are embedded in the second substrate, and any two second guiding blocks are mutually interposed No, and/or a plurality of connecting members are disposed between the first substrate and the second substrate, and any two connecting members are not electrically connected to each other.
  • the first trace is embedded on the first substrate, and/or the second trace is embedded on the second substrate.
  • the signal connection may include: an electrical connection or an optical connection.
  • a portion of the first pad is directly connected to a portion of the first guiding block, and another portion of the first pad is connected to the other portion of the first guiding block by a first wiring or the like.
  • an embodiment of the present invention provides an integrated optical interface chip 101, including:
  • An electric chip is disposed on a surface of the main substrate and has a signal connection with the main substrate;
  • the optical chip is embedded in the main substrate and disposed opposite to the electric chip;
  • thermoelectric refrigeration module provided by any one of the foregoing technical solutions provided by the first aspect is further disposed between the optical chip and the electrical chip; wherein at least one first pad disposed on the first substrate of the thermoelectric refrigeration module and the electrical chip are disposed
  • the pin has a signal connection; at least one second pad disposed on the second substrate of the thermoelectric refrigeration module is in signal connection with the pin of the optical chip; and the thermoelectric refrigeration module is configured to absorb heat emitted by the optical chip.
  • the integrated optical interface chip may further include a chip cover; the chip cover covers the electrical chip and is fixedly connected to the main substrate.
  • the IO provided by the embodiment of the present invention includes the TEC provided by the above first aspect, and thus the same technical effects as the above TEC can be achieved, and details are not described herein again.
  • an embodiment of the present invention provides a communications device, including:
  • the integrated optical interface chip provided by any one of the foregoing second aspects; the integrated optical chip is disposed on the circuit board; and the integrated optical interface chip includes the thermoelectric refrigeration module;
  • thermoelectric refrigeration module a heat sink for dissipating heat from the hot end of the thermoelectric refrigeration module
  • Power supply module power supply module is used to supply power to the thermoelectric cooling module and the circuit board.
  • the communication device provided by the embodiment of the present invention includes the TEC provided by the above first aspect, and thus the same technical effects as the above TEC can be achieved, and details are not described herein again.
  • FIG. 1 is a side view 1 of an IOI chip provided in the prior art
  • FIG. 2 is a side view 1 of a TEC according to an embodiment of the present invention.
  • FIG. 3 is a top plan view of a TEC based on FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a side view 2 of a TEC according to an embodiment of the present invention.
  • FIG. 5 is a top view of a TEC based on FIG. 4 according to an embodiment of the present invention.
  • Figure 6 is a side view 3 of a TEC according to an embodiment of the present invention.
  • FIG. 7 is a top view of a TEC based on FIG. 6 according to an embodiment of the present invention.
  • Figure 8 is a side view of a TEC according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view along MM′ of the TEC shown in FIG. 8 according to an embodiment of the present invention.
  • Figure 10 is a side view 5 of a TEC according to an embodiment of the present invention.
  • Figure 11 is a cross-sectional view along MM' of the TEC shown in Figure 10 according to an embodiment of the present invention.
  • Figure 12 is a side view of a TEC according to an embodiment of the present invention.
  • Figure 13 is a cross-sectional view along MM' of the TEC shown in Figure 11 according to an embodiment of the present invention
  • FIG. 14 is a side view of an IOI chip according to an embodiment of the present invention.
  • Figure 15 is a side view two of an IOI chip provided in the prior art.
  • the TEC provided by the embodiments of the present invention can be applied to a high junction temperature specification chip (also referred to as a high junction temperature heat source) and a low junction temperature specification chip (also referred to as a low junction temperature heat source) integrated package, and the optical chip
  • the device conforming to the transmission path of the electric chip may be specifically disposed between the high junction temperature specification chip and the low junction temperature specification chip.
  • the transmission path of the optical chip and the electric chip is the same as that of the optical chip and the main heat of the electric chip. For example, in the IOI chip shown in FIG. 1, the main heat of the optical chip and the electric chip are in accordance with Transfer from bottom to top.
  • junction temperature and “low junction temperature” are relative concepts.
  • an electrical chip having a junction temperature of 95 ° C an electrical chip having a junction temperature of 100 ° C is a high junction temperature specification chip; for an electrical chip having a junction temperature of 105 ° C, the junction temperature is 100 ° C.
  • the chip is a low junction temperature specification chip.
  • high junction temperature specification chip and "low junction temperature specification chip” may be the same or different, for example, may be two electric chips having different junction temperatures; or two optical chips having different junction temperatures; It is also possible that one is an optical chip having a first junction temperature, and the other is an electrical chip having a second junction temperature, wherein the first junction temperature and the second junction temperature are not equal.
  • junction temperature specification chip one of the high junction temperature specification chip and the low junction temperature specification chip is hereinafter referred to as a first junction temperature specification chip, and the other is referred to as a second junction temperature specification chip.
  • a plurality of connecting members means two or more connecting members.
  • A/B can be understood as A or B.
  • first and second and the like in this application are used to distinguish different objects, rather than to describe a particular order of the objects.
  • first substrate and the second substrate are intended to distinguish different substrates, rather than to describe a particular order of the substrates.
  • thermoelectric refrigeration module TEC is a side view of a thermoelectric refrigeration module TEC according to an embodiment of the present invention.
  • the TEC shown in FIG. 2 includes a first substrate 1 and a second substrate 2, and the first substrate 1 and the second substrate 2 are disposed opposite to each other.
  • At least one first pad 11 is disposed on an outer surface of the first substrate 1, and at least one second pad 21 is disposed on an outer surface of the second substrate 2.
  • At least one first guiding block 12 is embedded in the first substrate 1, and at least one second guiding block 22 is embedded in the second substrate 2.
  • At least one connecting member 3 is disposed between the first substrate 1 and the second substrate 2; the first pad 11 is signal-connected to the connecting member 3 via the first guiding block 12, and the second pad 21 is passed through the second guiding block 22
  • the connecting member 3 has a signal connection.
  • the TEC further includes at least one thermoelectric element 4; the at least one thermoelectric element 4 is fixed between the first substrate 1 and the second substrate 2; wherein the at least one thermoelectric element is used At the end of the energization, one end of the endothermic heat is radiated to cause a temperature difference between the first substrate 1 and the second substrate 2; any one of the thermoelectric elements 4 and any one of the connecting members 3 does not conduct each other.
  • the SOC includes an upper substrate and a lower substrate.
  • the first substrate 1 in the embodiment of the present invention may be an upper substrate of the TEC.
  • the second substrate 2 is a lower substrate of the TEC.
  • the first substrate 1 may also be The lower substrate of the TEC, in which case the second substrate 2 is the upper substrate of the TEC.
  • a surface on the first substrate 1 that is closer to the second substrate 2 is referred to as an inner surface of the first substrate 1, and a surface farther from the second substrate 2 is referred to as a first surface.
  • the number of the first pads 11 disposed on the outer surface of the first substrate 1 and the number of the second pads 21 disposed on the outer surface of the second substrate 2 are related to the practical application scenario of the TEC.
  • the first substrate 1 is connected to the first junction temperature specification chip
  • the second substrate 2 is connected to the second junction temperature specification chip.
  • a first pad 11 disposed on the outer surface of the first substrate 1 may be connected to the first junction.
  • a pin/solder ball on the temperature gauge chip that needs to be interconnected with the second junction temperature specification chip;
  • a second pad 21 disposed on the outer surface of the second substrate 2 can be connected to the second junction
  • a pin/bump on the temperature specification chip that is interconnected with the first junction temperature specification chip is signaled.
  • one solder ball may be connected to each of the first pads 11 to be connected to the first junction temperature specification chip; each of the second pads 21 may also be connected with a solder ball to meet the second junction temperature specification. Chip connection.
  • the guiding block (including the first guiding block 12 and the second guiding block 22) may specifically be a via or the like.
  • the embedded guide block in the substrate can be understood as: an insulating layer is attached to the inner sidewall of a through hole included in the substrate, and then the conductive hole (for example, copper or the like) is filled in the through hole, and the conductive material is a guide block. .
  • the shape and size of the first guiding block 12 and the second guiding block 22 are not limited in the embodiment of the present invention.
  • the positional relationship and the number relationship between the first via block 12 (or the second via block 22) and the first pad 11 (or the second pad 21) can be referred to below.
  • any two first guiding blocks 12 are not electrically connected to each other.
  • a plurality of second guiding blocks 22 are embedded in the second substrate 2, and any two second guiding blocks 22 are not electrically connected to each other.
  • the connecting member 3 which may be referred to as a connecting conductor, is used to implement a signal connection between the first pad 11 and the second pad 21.
  • the connecting member 3 is a solder ball and a pad attached to the inner surface of the first substrate 1 for soldering the solder ball and a pad attached to the inner surface of the second substrate 2 are
  • the specific implementation is not limited to this.
  • it may be a bump/a notch included on the first substrate and/or the second substrate, and a pad attached to the inner surface of the first substrate 1 for soldering the bump/cavity and A pad on the inner surface of the second substrate 2.
  • it may be any one of conductive members or the like provided between the first substrate 1 and the second substrate 2.
  • any two connecting members 3 are not electrically connected to each other.
  • At least one thermoelectric element 4 is used to exotherm one end of the endothermic heat when energized, so that a temperature difference is generated between the first substrate 1 and the second substrate 2, thereby forming a hot end and a cold end of the TEC, or a hot surface called TEC Or cold noodles to achieve the basic functions of TEC.
  • the at least one thermoelectric element may be fixed on the first substrate 1 and the second substrate 2 by the baffle 5 attached to the inner surface of the first substrate 1 and the baffle 5 attached to the inner surface of the second substrate 2. between.
  • the number of the thermoelectric elements 4 disposed between the first substrate 1 and the second substrate 2 and the series-parallel relationship between the plurality of the thermoelectric elements 4 may be set according to actual use scenarios.
  • the connection between the at least one thermoelectric element 4 and the at least one connecting member 3 can be referred to below.
  • any one of the connecting members 3 and any one of the pyroelectric elements 4 are not electrically connected to each other.
  • the baffle 5 coincides with the pads of the partial connecting member 3; In the meantime, the two are staggered.
  • the TEC provided by the embodiment of the present invention includes two sets of conductive systems, wherein one set is a power supply circuit of the thermoelectric element 4, and is implemented on the first substrate 1 and the second substrate 2 by supplying power to the pyroelectric element 4. A temperature difference is generated between the other; the other is a conduction circuit between the first pad 11 and the second pad 21 for implementing signal connection at both ends of the TEC.
  • the two conductive systems exist independently and do not interfere with each other.
  • the signal connection may include: an electrical connection or an optical connection.
  • the TEC provided by the embodiment of the invention includes a thermoelectric element fixed between the first substrate and the second substrate.
  • the thermocouple When the thermocouple is energized, one end absorbs heat at one end, so that a temperature difference is generated between the first substrate and the second substrate.
  • Realizing the outer surface of the first substrate by a first guiding block embedded in the first substrate, a connecting member fixed between the first substrate and the second substrate, and a second guiding block embedded in the second substrate A signal connection between the first pad disposed and the second pad disposed on the outer surface of the second substrate is performed to achieve signal interconnection between the two ends of the TEC.
  • the TEC when the TEC is set in the IOI chip, the heat dissipation speed of the IOI chip can be increased.
  • the positional relationship between the first guiding block 12 (or the second guiding block 22) and the first pad 11 (or the second pad 21) may include, but is not limited to, the following manners 1, 2;
  • the first pad 11 is disposed at a position of the outer surface of the first substrate 1 that can partially or completely cover the first guiding block 12, in which case the first pad 11 can directly pass through the first guiding block 12 and The connecting member 3 is connected.
  • the second pad 21 is disposed at a position of the outer surface of the second substrate 2 that can partially or completely cover the second guide block 22, in which case the second pad 21 can directly pass through the second guide block 22
  • the connecting member 3 is connected. as shown in picture 2.
  • the first guiding block 12 is directly under the first pad 11; the first pad 11 may be sequentially connected to the second pad 21 through the first guiding block 12, the connecting member 3, and the second guiding block 22.
  • a top view of the TEC shown in FIG. 2 is shown in FIG. 3 , wherein FIG. 3 is only an example, and the specific implementation is not limited thereto. This optional implementation 1 has the advantage of achieving simplicity.
  • the first pad 11 is disposed at a position of the outer surface of the first substrate 1 that cannot cover the first guiding block 12, in which case the first pad 11 has a signal via the first guiding block 12 and the connecting member 3.
  • the connection may include: the first pad 11 is connected to the first guiding block 12 via the first routing 13 , and the first guiding block 12 is connected to the connecting component 3 .
  • the second pad 21 is disposed at a position of the outer surface of the second substrate 2 that cannot cover the second guide block 22, in which case the second pad 21 has a signal via the second guide block 22 and the connecting member 3.
  • the connection may include: the second pad 21 is connected to the second guiding block 22 via the second routing 23, and the second guiding block 22 is connected to the connecting component 3.
  • a first trace 13 is connected to the first pad 11
  • a second trace 23 is connected to the second pad 21 .
  • the first pad 11 may sequentially pass through the first trace 13 .
  • the first guiding block 12, the connecting member 3, the second guiding block 22, and the second wiring 23 are connected to the second pad 21.
  • connection pad and the connecting component are connected by a wire, so that the same pad can be connected to different connecting components through different wires, and the wire can be laid according to actual needs when the specific implementation is realized, and the actual pad can also be arranged according to actual needs.
  • the wiring width, pitch, and the like can be adjusted according to the rate of the transmitted electrical signal. Therefore, it has the beneficial effect of achieving flexibility.
  • the traces may be embedded on the substrate.
  • the first traces 13 may be embedded on the first substrate 1 and the second traces 23 may be embedded on the second substrate 2.
  • FIG. 5 A top view of the TEC shown in Figure 4 is shown in Figure 5.
  • a first pad 11 is signally coupled to a first via 12.
  • the specific implementation is not limited to this.
  • the positionsal relationship of a portion of the first guiding block 12 and a portion of the first pad 11 is set in an optional manner 1, and the other portion of the first guiding block 12 and the other portion are first.
  • the positional relationship of the pads 11 is set in an alternative manner 2.
  • First guiding block 12 (or second guiding block 22) and first pad 11 (or second pad 21)
  • the quantitative relationship between them may include, but is not limited to, the following alternative modes 3, 4.
  • the first pad 11 is connected to the connecting component 3 via the first guiding block 12, and specifically includes: a first pad 11 is connected to a first guiding block 12, and the first guiding block 12 is connected.
  • Component 3 has a signal connection.
  • the second pad 21 is connected to the connecting component 3 via the second guiding block 22, and specifically includes: a second pad 21 is connected to a second guiding block 22, and the second guiding block 22 is connected.
  • Component 3 has a signal connection.
  • the optional implementation has the advantages of simple implementation and convenient maintenance.
  • a first pad 11 and a first guiding block 12 are connected to a signal, and specifically, a first pad 11 passes through the first trace 13 and a first A lead block 12 has a signal connection.
  • a second pad 21 is connected to a second guiding block 22, and specifically, a second pad 21 is connected to a second guiding block 22 via the second routing 23.
  • the first pad 11 is connected to the connecting component 3 via the first guiding block 12, and specifically includes: a plurality of first pads 11 of the same level and a first guiding block 12 have a signal connection, first The guide block 12 is signally connected to the connecting member 3.
  • the second pad 21 is connected to the connecting component 3 via the second guiding block 22, and specifically includes: a plurality of second pads 21 of the same level and a second guiding block 22 having a signal connection, and second The guide block 22 is in signal connection with the connecting member 3.
  • a plurality of first pads 11 of the same level are connected to a first guiding block 12, and specifically may be: a plurality of first pads of the same level.
  • 11 is signally coupled to a first pilot block 12 via one or more first traces 13.
  • the plurality of second pads 21 of the same level are connected to the second conductive block 22, and specifically, the plurality of second pads 21 of the same level may pass through the one or more second traces 23 It has a signal connection with a second guiding block 22.
  • This method can save the guide block (including the first guide block 12 and the second guide block 22) and the connection
  • the number of components 3 therefore, the more the number of connecting components 3, the more thermal backflow on the TEC (ie, the phenomenon of heat transfer from the hot end to the cold end of the TEC), which requires more power consumption.
  • the temperature difference across the TEC is maintained constant; therefore, this alternative embodiment can reduce TEC thermal backflow and reduce TEC power consumption by reducing the number of connecting components 3.
  • the first pad 11 and the second pad 21 are both used to connect the pins of the chip, and thus have a certain voltage.
  • a fixed voltage is a fixed voltage that can be either a high voltage or a low voltage compared to a variable voltage (or voltage to be regulated).
  • a fixed voltage is a certain high voltage
  • a plurality of pads having the fixed high voltage may be signal-connected to the same via, in which case each pad having a variable voltage may be used with one
  • the hole has a signal connection as shown in Figure 7.
  • 7 is a partial plan view of the TEC shown in FIG. 6; in FIG.
  • a plurality of first pads 11a having the same fixed high voltage are signal-connected to the same first via 12a, the plurality of first pads 11a
  • a first trace 13 between the first via 12a and the first via 12a is labeled 13a;
  • a first pad 11b having a variable low voltage is signally connected to a first via 12b, the first pad 11b and the first lead
  • the first trace 13 between the blocks 12b is labeled 13b.
  • the quantitative relationship (or the correspondence relationship) between a portion of the first guiding block 12 and a portion of the first pads 11 is set in an optional manner 3.
  • the number relationship of the other portion of the first guiding block 12 and the other portion of the first pad 11 is set in an optional manner 4.
  • the quantitative relationship between the first pad 11 (or the second pad 21) and the connecting member 3 may include, but is not limited to, the following manners 5, 6:
  • the first pad 11 is connected to the connecting component 13 via the first guiding block 12, and may specifically include: a first pad 11 or a plurality of first pads 11 and a first guiding block of the same level. 12 has a signal connection, and a first guiding block 12 has a signal connection with a connecting member 13; that is, a plurality of first pads 11 and a connecting member 13 of the same level. There is a signal connection.
  • the second pad 21 is connected to the connecting component 13 via the second guiding block 22, and may specifically include: a second pad 21 or a plurality of second pads 21 and a second guiding block of the same level. 22 has a signal connection, and a second guiding block 22 is signally connected to a connecting member 13; that is, a plurality of second pads 21 of the same level are connected to a connecting member 13.
  • the first pad 11 is connected to the connecting component 13 via the first guiding block 12, and may specifically include: a plurality of first pads 11 of the same level are connected to one via the one or more first guiding blocks 12.
  • the components 13 are connected.
  • the second pad 21 is connected to the connecting component 13 via the second guiding block 22, and may specifically include: a plurality of second pads 21 of the same level and one or more second guiding blocks 22 connected to one The components 13 are connected.
  • the first substrate 1 further has at least one third guiding block embedded therein and/or the second substrate 2 further includes at least one third guiding block; the power supply of the at least one thermoelectric element 4 The power supply supplies power to the at least one thermoelectric element 4 via the third guide block.
  • the third guiding block may be embedded on the first substrate 1 or embedded on the second substrate 2.
  • the third guiding block may be inside. Embedded on the first substrate 1; if the chip connected to the first substrate 2 is an electric chip, the third guiding block may be embedded on the second substrate 2.
  • the number of third guiding blocks can be determined according to actual needs. Generally, the number of third guiding blocks is greater than or equal to 2.
  • a TEC is provided for the optional implementation, the third guiding block in the TEC is embedded on the first substrate 1 and is labeled as 14 on the first substrate 1
  • Two third guiding blocks 14 are embedded as an example for description.
  • the connection member 3 is distribute
  • the connecting member 3 and the thermoelectric element 4 are disposed between the first substrate 1 and the second substrate 2, and at least one connecting member 3 may be disposed between the first substrate 1 and the second substrate 2, specifically, the connecting member 3
  • the number may be determined according to the number of the first guide block 12 and the second guide block 22.
  • the positional relationship between the at least one connecting member 3 and the at least one thermoelectric element 4 may include, but is not limited to, the following:
  • the at least one connecting member 3 is distributed around the periphery of the at least one thermoelectric element 4, as shown in FIG.
  • a cross-sectional view taken along the line MM' in Fig. 8 is shown in Fig. 9.
  • FIG. 9 is merely an example, and the specific implementation is not limited thereto, and for example, the connection member 3 may be disposed around the thermoelectric element 4 or the like.
  • the connecting member 3 is distributed on the periphery of the pyroelectric element 4. Since the temperature difference between the two substrates of the TEC is relatively small, the heat between the two ends of the TEC can be reduced, thereby reducing the power consumption of the TEC itself.
  • thermoelectric element 4 is distributed around the periphery of the at least one connecting member 3, as shown in FIG.
  • a cross-sectional view taken along the line MM' in Fig. 10 is shown in Fig. 11.
  • FIG. 11 is merely an example, and the specific implementation is not limited thereto, and for example, the thermoelectric element 4 may be disposed around the connecting member 3 or the like.
  • This optional implementation can reduce the propagation path of the high frequency electrical signal through the TEC, thereby reducing the delay and attenuation caused by the high frequency signal.
  • thermoelectric element 4 is staggered with the at least one connecting member 3, as shown in FIG.
  • a cross-sectional view of the cross section taken along line MM' in Fig. 12 is shown in Fig. 13.
  • FIG. 13 is merely an example, and the specific implementation is not limited thereto. This optional implementation can combine the advantages of the first mode and the second mode described above, and can effectively utilize the space of the TEC substrate to reduce the area of the TEC.
  • thermoelectric elements 4 are disposed on the periphery of a part of the connecting member 3, another part of the thermoelectric element 4 is interlaced with the connecting member 3, and the like.
  • thermoelectric element 4 is interlaced with the connecting member 3 and the like.
  • the baffle 5 overlaps the pads of the connecting member 3; in fact, the two are staggered.
  • an embodiment of the present invention further provides an IOI chip.
  • the IOI chip shown in Figure 14 includes:
  • An electric chip is disposed on a surface of the main substrate and has a signal connection with the main substrate Connect
  • the optical chip is embedded in the main substrate and disposed opposite to the electric chip;
  • thermoelectric refrigeration module provided by any one of the foregoing technical solutions provided by the first aspect is further disposed between the optical chip and the electrical chip; wherein at least one first pad disposed on the first substrate of the thermoelectric refrigeration module and the electrical chip are disposed
  • the pin has a signal connection; at least one second pad disposed on the second substrate of the thermoelectric refrigeration module is in signal connection with the pin of the optical chip; and the thermoelectric refrigeration module is configured to absorb heat emitted by the optical chip.
  • the IOI chip may further include a chip cover; the chip cover covers the electrical chip and is fixedly connected to the main substrate.
  • FIG. 14 the number of optical chips and electrical chips on both sides of the TEC is described by taking an electric chip on one side of the TEC and two optical chips on the other side as an example. Not limited.
  • FIG. 14 is an example in which the chip cover is included in the IOI chip.
  • the heat transfer path in the IOI chip provided by the embodiment of the present invention is: from the optical chip to the cold end of the TEC, from the cold end of the TEC to the hot end of the TEC, and then from the hot end of the TEC to the electric chip, and finally from the electric The path from the chip to the chip housing. That is, the direction from bottom to top in FIG.
  • the TEC can be turned on and off according to actual needs. For example, when the IOI chip is difficult to dissipate heat, the TEC is activated, that is, the TEC is energized, that is, the thermoelectric element in the TEC is energized, so that one end of the TEC connected to the electric chip is a hot end, and one end connected to the optical chip is cold.
  • the terminal further realizes rapid heat dissipation of the IOI chip through the above heat transfer path.
  • the method for determining the heat dissipation of the IIO chip is not limited in the embodiment of the present invention, and can be implemented, for example, by measuring the temperature of the chip case.
  • the IOI chip provided by the embodiment of the invention includes a TEC fixed between the optical chip and the electric chip.
  • the TEC cold junction temperature can be made lower than the light.
  • the junction temperature of the chip, the junction temperature required by the thermal chip of the TEC hot end is roughly equal, so that the shell temperature of the IOI chip is no longer low by the optical chip.
  • the shell temperature is limited to achieve rapid heat dissipation.
  • an IOI chip including a TEC is also provided in the prior art, as shown in FIG. Specifically, a TEC is embedded in the chip cover. Since the neck temperature of the IOI chip is at the optical chip, by controlling the temperature difference between the hot end and the cold end of the TEC, the TEC cold junction temperature is lower than the temperature required by the optical chip, and the TEC hot end temperature is higher than the cold end. 10 to 20 ° C, so that the shell temperature of the IOI chip is no longer limited by the low shell temperature of the optical chip.
  • this method requires the TEC to undertake part of the cooling of the electric chip, which results in a large volume and power consumption of the TEC, and the practical application effect is limited.
  • the TEC is disposed between the electric chip and the optical chip, the TEC does not need to undertake cooling of the electric chip, thereby making the volume and work of the TEC. The consumption is small.
  • the embodiment of the invention provides a communication device, including:
  • the IOI chip is provided on the circuit board; the IOI includes a TEC; wherein the TEC is any TEC provided by the embodiment of the present invention;
  • thermoelectric refrigeration module a heat sink for dissipating heat from the hot end of the thermoelectric refrigeration module
  • Power supply module power supply module is used to supply power to the thermoelectric cooling module and the circuit board.
  • the communication device provided by the embodiment of the present invention includes the IOI chip provided above, so that the same technical effect of the above IOI chip can be achieved, that is, the IOI chip can be quickly dissipated, so that the communication device can quickly dissipate heat.

Abstract

一种热电制冷模块、集成光接口芯片和通信设备，用以实现快速散热。热电制冷模块包括第一基板（1）和与第一基板相对设置的第二基板（2）；第一基板的外表面设置有至少一个第一焊盘（11），第二基板的外表面设置有至少一个第二焊盘（21）；第一基板内嵌有至少一个第一导块（12），第二基板内嵌有至少一个第二导块（22）；第一基板与第二基板之间设置有至少一个连接部件（3）；第一焊盘经第一导块与连接部件有信号连接，第二焊盘经第二导块与连接部件有信号连接；还包括至少一个热电素子（4），至少一个热电素子固定于第一基板和第二基板之间；至少一个热电素子在通电时一端吸热一端放热，以使第一基板和第二基板之间产生温差；任一个热电素子与任一个连接部件之间互不导通。

Description

一种热电制冷模块、集成光接口芯片和通信设备
本申请要求于2015年12月25日提交中国专利局、申请号为201510992902.2、发明名称为“一种热电制冷模块、集成光接口芯片和通信设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及光电通信技术领域，尤其涉及一种热电制冷模块(thermoelectric cooler，TEC)、集成光接口(integrated optical interface，IOI)芯片和通信设备。
背景技术
IOI芯片，即光电混合芯片，其集成了光芯片与电芯片，通过电芯片实现数据的逻辑处理等功能，通过光芯片出光实现高速互连。一种IOI芯片的侧视图如图1所示，其中，图1中的IOI芯片包括主基板、光芯片和电芯片，电芯片位于光芯片的上方，电芯片与光芯片之间，以及电芯片与基板之间可以通过焊球连接；另外IOI芯片还包括芯片盖体(lid)等。
由于光芯片的结温较低；且光、电芯片传热路径一致，加之传热路径热阻的影响，导致IOI芯片的壳温一般较低。例如，光芯片的结温一般不超过85℃，由于传热路径热阻的影响，使得IOI芯片的壳温大概只有70℃；其中，作为对比，电芯片的结温壳达105℃，同功耗同尺寸的电芯片的壳温可达90℃。由于IOI芯片功能复杂，因此其功耗也相对较大。功耗大使得IOI芯片散热困难。
发明内容
本发明的实施例提供一种TEC、IOI芯片和通信设备，用以实现快速散热。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明实施例提供一种TEC，包括：第一基板和第二基板，第一基板与第二基板相对设置；
第一基板的外表面上设置有至少一个第一焊盘，第二基板的外表面上设置有至少一个第二焊盘；
第一基板上内嵌有至少一个第一导块，第二基板上内嵌有至少一个第二导块；
第一基板与第二基板之间设置有至少一个连接部件；第一焊盘经第一导块与连接部件有信号连接，第二焊盘经第二导块与连接部件有信号连接；
热电制冷模块还包括至少一个热电素子；该至少一个热电素子固定于第一基板与第二基板之间；其中，该至少一个热电素子用于在通电时一端吸热一端放热，以使第一基板与第二基板之间产生温差；任意一个热电素子与任意一个连接部件之间互不导通。
本发明实施例提供的TEC，包含有固定在第一基板与第二基板之间的热电素子，通过热电素子在通电时一端吸热一端放热，使得第一基板与第二基板之间产生温差(即形成TEC的热端和冷端，或形成TEC的热面和冷面)；通过内嵌于第一基板的第一导块、固定在第一基板与第二基板之间的连接部件，以及内嵌于第二基板的第二导块，实现第一基板的外表面上设置的第一焊盘与第二基板的外表面上设置的第二焊盘之间的信号连接，从而实现TEC两端之间的信号互连。这样，当IOI芯片中设置了该TEC之后，能够加快IOI芯片的散热速度。
可选的，至少一个热电素子通过附在第一基板的内表面的导流片和附在第二基板的内表面的导流片固定在第一基板与第二基板之间。
关于焊盘与导块之间的连接关系，本发明实施例提供了以下几 种可选的技术方案：
基于上述任意一种技术方案，第一焊盘与第一导块之间可以直接连接；同理，第二焊盘与第二导块之间可以直接连接。
基于上述任意一种技术方案，在可选的实现方式1中，第一焊盘经第一导块与连接部件有信号连接，具体可以包括：第一焊盘经第一走线与第一导块有信号连接，第一导块与连接部件有信号连接。
基于上述任意一种技术方案，在可选的实现方式2中，第二焊盘经第二导块与连接部件有信号连接，具体可以包括：第二焊盘经第二走线与第二导块有信号连接，第二导块与连接部件有信号连接。
上述可选的实现方式1和上述可选的实现方式2中，均通过走线连接焊盘与连接部件，这样，同一焊盘可以通过不同的走线连接在连接部件上，具体实现时可以根据实际需要布局走线，另外，还可以根据实际进行表层布线或多层布线，布线宽度和间距等可以根据传输的电信号的速率进行调整。因此，具有实现灵活的有益效果。
关于焊盘与导块之间的数量关系，本发明实施例提供了以下几种可选的技术方案：
基于上述任意一种技术方案，在可选的实现方式3中，第一焊盘经第一导块与连接部件有信号连接，具体可以包括：一个第一焊盘与一个第一导块有信号连接，第一导块与连接部件有信号连接。
示例的，基于上述可选的实现方式2，在该可选的实现方式3中，一个第一焊盘与一个第一导块与信号连接，具体可以是：一个第一焊盘经第一走线与一个第一导块有信号连接。
基于上述任意一种技术方案，在可选的实现方式4中，第二焊盘经第二导块与连接部件有信号连接，具体可以包括：一个第二焊盘与一个第二导块有信号连接，第二导块与连接部件有信号连接。
示例的，基于上述可选的实现方式2，在该可选的实现方式4中，一个第二焊盘与一个第二导块有信号连接，具体可以是：一个第二焊盘经第二走线与一个第二导块有信号连接。
上述可选的实现方式3和上述可选的实现方式4中，一个焊盘与一个导块之间有信号连接，这样能够达到实现简单，检修方便的有益效果。
基于上述任意一种技术方案，在可选的实现方式5中，第一焊盘经第一导块与连接部件有信号连接，具体可以包括：同电平的多个第一焊盘与一个第一导块有信号连接，第一导块与连接部件有信号连接。
示例的，基于上述可选的实现方式2，在该可选的实现方式5中，同电平的多个第一焊盘与一个第一导块有信号连接，具体可以是：同电平的多个第一焊盘经一条或多条第一走线与一个第一导块有信号连接。
基于上述任意一种技术方案，在可选的实现方式6中，第二焊盘经第二导块与连接部件有信号连接，具体可以包括：同电平的多个第二焊盘与一个第二导块有信号连接，第二导块与连接部件有信号连接。
示例的，基于上述可选的实现方式2，在该可选的实现方式6中，同电平的多个第二焊盘与一个第二导块有信号连接，具体可以是：同电平的多个第二焊盘经一条或多条第二走线与一个第二导块有信号连接。
上述可选的实现方式5和上述可选的实现方式6中，多个焊盘与一个导块之间有信号连接，这样能够通过减少连接部件的数量，减小TEC热量倒灌，从而降低TEC的功耗。
关于焊盘与连接部件之间的数量关系，本发明实施例提供了以下几种可选的技术方案：
基于上述任意一种技术方案，在一种可选的实现方式中，第一焊盘经第一导块与连接部件有信号连接，具体可以包括：同电平的多个第一焊盘经一个或多个第一导块与一个连接部件连接。
基于上述任意一种技术方案，在一种可选的实现方式中，第二焊盘经第二导块与连接部件有信号连接，具体可以包括：同电平的多个第二焊盘经一个或多个第二导块与一个连接部件连接。
关于连接部件与热电素子之间的位置关系，本发明实施例提供了以下几种可选的技术方案：
第一种：至少一个连接部件分布在至少一个热电素子的外围。
第二种：至少一个热电素子分布在至少一个连接部件的外围。
第三种：至少一个热电素子与至少一个连接部件交错分布。
该第一种可选的方式能够减少TEC两端之间的热量倒灌，从而降低TEC自身功耗。第二种可选的方式能够减小流入第一焊盘(或第二焊盘)的高频电信号通过TEC时的传播路径，从而降低对高频信号造成的时延和衰减。第三种可选的方式能够综合上述第一种方式和第二种方式的有益效果，并且能够有效利用TEC基板的空间，减小TEC的面积。
本发明实施例还提供了关于为热电素子供电的可选的技术方案：
基于上述任意一种技术方案，可选的，第一基板上还内嵌有至少一个第三导块和/或第二基板上还包含有至少一个第三导块；至少一个热电素子的供电电源经第三导块为至少一个热电素子供电。
该可选的实现方式通过在第一基板和/或第二基板上设置第三导块，从而通过第三导块为该至少一个热电素子供电，与现有技术中的通过在第一基板与第二基板之间向外引导线，从而为热电素子供电相比，具有实现简单，操作方便的有益效果。
另外，基于上述任意一种技术方案，可选的，第一基站上内嵌 有多个第一导块，任意两个第一导块之间互不导通；和/或，第二基板上内嵌有多个第二导块，任意两个第二导块之间互不导通；和/或，第一基板与第二基板之间设置有多个连接部件，则任意两个连接部件之间互不导通。
基于上述任意一种技术方案，可选的，第一走线内嵌在第一基板上，和/或，第二走线内嵌在第二基板上。
基于上述任意一种技术方案，可选的，有信号连接可以包括：电连接或光连接等。
需要说明的是，具体实现时，在不冲突的情况下，上述任意两种或两种以上的技术方案中的部分或全部技术特征之间可以进行组合，从而得到新的技术方案。例如，部分第一焊盘与部分第一导块之间直接连接，另一部分第一焊盘与另一部分第一导块之间通过第一走线连接等。
第二方面，本发明实施例提供一种集成光接口芯片IOI，包括：
主基板；
电芯片；电芯片设置于在主基板的表面，并与主基板有信号连接；
光芯片；光芯片内嵌于主基板,并与电芯片相对设置；
光芯片与电芯片之间还设置有上述第一方面提供的任意一种技术方案所提供的热电制冷模块；其中，热电制冷模块的第一基板上设置的至少一个第一焊盘与电芯片的引脚有信号连接；热电制冷模块的第二基板上设置的至少一个第二焊盘与光芯片的引脚有信号连接；热电制冷模块用于吸收光芯片散发出来的热量。
可选的，该集成光接口芯片还可以包括芯片盖体；芯片盖体覆盖在电芯片上，并与主基板固定连接。
本发明实施例提供的IOI中包含上述第一方面提供的TEC，因此能够达到与上述TEC相同的技术效果，此处不再赘述。
第三方面，本发明实施例提供一种通信设备，包括：
电路板；
如上述第二方面的任意一种技术方案所提供的集成光接口芯片；集成光芯片设置于电路板上；集成光接口芯片中包含热电制冷模块；
散热器；散热器用于将来自热电制冷模块的热端的热量散发出去；
供电模块；供电模块用于为热电制冷模块和电路板供电。
本发明实施例提供的通信设备中包含上述第一方面提供的TEC，因此能够达到与上述TEC相同的技术效果，此处不再赘述。
附图说明
图1为现有技术中提供的IOI芯片的侧视图一；
图2为本发明实施例提供的TEC的侧视图一；
图3为本发明实施例提供的基于图2所示的TEC的一种俯视图；
图4为本发明实施例提供的TEC的侧视图二；
图5为本发明实施例提供的基于图4所示的TEC的一种俯视图；
图6为本发明实施例提供的TEC的侧视图三；
图7为本发明实施例提供的基于图6所示的TEC的一种俯视图；
图8为本发明实施例提供的TEC的侧视图四；
图9为本发明实施例提供的基于图8所示的TEC的沿MM'的一种剖面图；
图10为本发明实施例提供的TEC的侧视图五；
图11为本发明实施例提供的基于图10所示的TEC的沿MM'的一种剖面图；
图12为本发明实施例提供的TEC的侧视图六；
图13为本发明实施例提供的基于图11所示的TEC的沿MM'的一种剖面图；
图14为本发明实施例提供的IOI芯片的侧视图；
图15为现有技术中提供的IOI芯片的侧视图二。
具体实施方式
本发明实施例所提供的TEC可以应用于高结温规格芯片(也可称为高结温热源)与低结温规格芯片(也可称为低结温热源)集成封装，并且光芯片与电芯片的传输路径一致的装置中，具体可以设置在高结温规格芯片与低结温规格芯片之间。其中，光芯片与电芯片的传输路径一致是指光芯片与电芯片的主要热量往一个方向传输，例如，在如图1所示的IOI芯片中，光芯片与电芯片的主要热量均是按照由下到上的方向传输。
其中，“高结温”和“低结温”是相对的概念。例如，相对于结温是95℃的电芯片来说，结温是100℃的电芯片属于高结温规格芯片；相对于结温是105℃的电芯片来说，结温是100℃的电芯片属于低结温规格芯片。
“高结温规格芯片”和“低结温规格芯片”的类型可以相同也可以不同，例如，可以是具有不同结温的两个电芯片；也可以是具有不同结温的两个光芯片；还可以一个是具有第一结温的光芯片，另一个是具有第二结温的电芯片，其中，第一结温与第二结温不相等。
需要说明的是，下文中将高结温规格芯片和低结温规格芯片中的其中一个称为第一结温规格芯片，另一个称为第二结温规格芯片。
本申请中的术语“多个”除非特别说明的情况外，其他均是指两个或者两个以上。例如多个连接部件是指两个或两个以上的连接部件。
本申请中的术语“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本申请中的字符“/”，一般表示前后关联对象是一种“或者”的关系。例如，A/B可以理解为A或者B。
本申请中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一基板和第二基板是为了区分不同的基板，而不是用于描述基板的特定顺序。
下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行示例性描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在不冲突的情况下，下述各可选的实现方式之间的部分特征可以结合使用。
参见图2，为本发明实施例提供的一种热电制冷模块TEC的侧视图。图2所示的TEC包括：第一基板1和第二基板2，第一基板1与第二基板2相对设置。
第一基板1的外表面上设置有至少一个第一焊盘11，第二基板2的外表面上设置有至少一个第二焊盘21。
第一基板1上内嵌有至少一个第一导块12，第二基板2上内嵌有至少一个第二导块22。
第一基板1与第二基板2之间设置有至少一个连接部件3；第一焊盘11经第一导块12与连接部件3有信号连接，第二焊盘21经第二导块22与连接部件3有信号连接。
该TEC还包括至少一个热电素子4；该至少一个热电素子4固定于第一基板1与第二基板2之间；其中，该至少一个热电素子用 于在通电时一端吸热一端放热，以使第一基板1与第二基板2之间产生温差；任意一个热电素子4与任意一个连接部件3之间互不导通。
其中，TEC包括上基板和下基板；本发明实施例中的第一基板1可以是TEC的上基板，该情况下，第二基板2是TEC的下基板；另外，第一基板1也可以是TEC的下基板，该情况下，第二基板2是TEC的上基板。
在本发明实施例中，将第一基板1上的与第二基板2距离较近的一个表面称为第一基板1的内表面，与第二基板2距离较远的一个表面称为第一基板1的外表面；同理，将第二基板2上的与第一基板1距离较近的一个表面称为第二基板2的内表面，与第二基板2距离较远的一个表面称为第二基板2的外表面。
可选的，第一基板1的外表面上设置的第一焊盘11的数量，以及第二基板2的外表面上设置的第二焊盘21的数量，与TEC的实际应用场景有关。以第一基板1与第一结温规格芯片连接，第二基板2与第二结温规格芯片连接为例，第一基板1的外表面上设置的一个第一焊盘11可以与第一结温规格芯片上的需要与第二结温规格芯片之间进行互连的一个引脚/焊球有信号连接；第二基板2的外表面上设置的一个第二焊盘21可以与第二结温规格芯片上的需要与第一结温规格芯片之间进行互连的一个引脚/焊球有信号连接。实际应用中，每个第一焊盘11上可以连接一个焊球，以与第一结温规格芯片连接；每个第二焊盘21上也可以连接一个焊球，以与第二结温规格芯片连接。
导块(包括第一导块12和第二导块22)具体可以是过孔等。基板中内嵌导块可以理解为：在基板所包含的一个通孔的内侧壁附上一层绝缘层，然后在该通孔内填充导电物质(例如铜等)，该导电物质即为导块。
本发明实施例对第一导块12和第二导块22的形状和大小不进行限定。第一导块12(或第二导块22)与第一焊盘11(或第二焊盘21)之间的位置关系和数量关系可以参考下文。
具体实现时，第一基站1上内嵌有多个第一导块12时，任意两个第一导块12之间互不导通。类似的，第二基板2上内嵌有多个第二导块22，任意两个第二导块22之间互不导通。
连接部件3，可以称为连接导体，用于实现第一焊盘11与第二焊盘21之间的信号连接。本申请附图中均以连接部件3是焊球以及用于焊连该焊球的附在第一基板1的内表面上的焊盘和附在第二基板2的内表面上的焊盘为例进行说明，当然具体实现时，不限于此。例如，还可以是包含在第一基板和/或第二基板上的凸块/凹块，以及用于焊连该凸块/凹块的附在第一基板1的内表面上的焊盘和符在第二基板2的内表面上的焊盘。另外还可以是设置在第一基板1和第二基板2之间的任一种导电部件等。
具体实现时，第一基板1与第二基板2之间设置有多个连接部件3时，任意两个连接部件3之间互不导通
至少一个热电素子4用于在通电时一端吸热一端放热，以使第一基板1与第二基板2之间产生温差，从而形成TEC的热端和冷端，或称为TEC的热面或冷面，以实现TEC的基本功能。可选的，该至少一个热电素子可以通过附在第一基板1内表面的导流片5和附在第二基板2内表面的导流片5固定在第一基板1与第二基板2之间。具体实现时，第一基板1与第二基板2之间所设置的热电素子4的数量以及多个热电素子4之间的串并联关系等可以根据实际使用场景进行设置。至少一个热电素子4与至少一个连接部件3之间的连接可以参考下文。
具体实现时，任意一个连接部件3与任意一个热电素子4之间互不导通。在图2中，导流片5与部分连接部件3的焊盘重合；实 际上，二者是错开设置的。
需要说明的是，本发明实施例提供的TEC中包含两套导电系统，其中一套是热电素子4的供电电路，用以通过为热电素子4供电，实现在第一基板1与第二基板2之间产生温差；另一套是第一焊盘11与第二焊盘21之间的导通电路，用以实现TEC两端的信号连接。该两个导电系统之间独立存在，互不干扰。
可选的，有信号连接可以包括：电连接或光连接等。
本发明实施例提供的TEC，包含有固定在第一基板与第二基板之间的热电素子，通过热电素子在通电时一端吸热一端放热，使得第一基板与第二基板之间产生温差；通过内嵌于第一基板的第一导块、固定在第一基板与第二基板之间的连接部件，以及内嵌于第二基板的第二导块，实现第一基板的外表面上设置的第一焊盘与第二基板的外表面上设置的第二焊盘之间的信号连接，从而实现TEC两端之间的信号互连。这样，当IOI芯片中设置了该TEC之后，能够加快IOI芯片的散热速度。
第一导块12(或第二导块22)与第一焊盘11(或第二焊盘21)之间的位置关系可包括但不限于以下方式1、2；
方式1：第一焊盘11设置在第一基板1的外表面的能够部分或全部覆盖第一导块12的位置上，该情况下，第一焊盘11可以直接通过第一导块12与连接部件3连接。类似地，第二焊盘21设置在第二基板2的外表面的能够部分或全部覆盖第二导块22的位置上，该情况下，第二焊盘21可以直接通过第二导块22与连接部件3连接。如图2所示。在图2中，第一导块12在第一焊盘11的正下方；第一焊盘11可以依次通过第一导块12、连接部件3、第二导块22与第二焊盘21连接。其中，图2所示的TEC的一种俯视图如图3所示，其中，图3仅是一种示例，具体实现时不限于此。该可选的实现方式1具有实现简单的有益效果。
方式2：第一焊盘11设置在第一基板1的外表面的不能覆盖第一导块12的位置上，该情况下，第一焊盘11经第一导块12与连接部件3有信号连接，具体可以包括：第一焊盘11经第一走线13与第一导块12有信号连接，第一导块12与连接部件3有信号连接。类似地，第二焊盘21设置在第二基板2的外表面的不能覆盖第二导块22的位置上，该情况下，第二焊盘21经第二导块22与连接部件3有信号连接，具体可以包括：第二焊盘21经第二走线23与第二导块22有信号连接，第二导块22与连接部件3有信号连接。如图4或图6所示。在图4或图6中，第一焊盘11上连接有第一走线13，第二焊盘21上连接有第二走线23；第一焊盘11可以依次通过第一走线13、第一导块12、连接部件3、第二导块22、第二走线23与第二焊盘21连接。
该方式2中通过走线连接焊盘与连接部件，这样，同一焊盘可以通过不同的走线连接在不同的连接部件上，具体实现时可以根据实际需要布局走线，另外，还可以根据实际进行表层布线或多层布线，布线宽度和间距等可以根据传输的电信号的速率进行调整。因此，具有实现灵活的有益效果。可选的，走线可以内嵌在基板上，例如，第一走线13可以内嵌在第一基板1上，第二走线23可以内嵌在第二基板2上。
图4所示的TEC的一种俯视图如图5所示。在图5中，一个第一焊盘11与一个第一导块12有信号连接。当然具体实现时，不限于此。
该方式1、2的部分特征可以组合使用，例如，一部分第一导块12和一部分第一焊盘11的位置关系按照可选的方式1设置，另一部分第一导块12和另一部分第一焊盘11的位置关系按照可选的方式2设置。另外，还可以有其他的组合方式，此处不再一一列举。
第一导块12(或第二导块22)与第一焊盘11(或第二焊盘21) 之间的数量关系(或称为对应关系)可包括但不限于以下可选的方式3、4。
方式3：第一焊盘11经第一导块12与连接部件3有信号连接，具体可以包括：一个第一焊盘11与一个第一导块12有信号连接，第一导块12与连接部件3有信号连接。类似的，第二焊盘21经第二导块22与连接部件3有信号连接，具体可以包括：一个第二焊盘21与一个第二导块22有信号连接，第二导块22与连接部件3有信号连接。如图2或图4所示。该可选的实现方式具有实现简单，检修方便的有益效果。
示例的，基于上述方式2，在该方式3中，一个第一焊盘11与一个第一导块12与信号连接，具体可以是：一个第一焊盘11经第一走线13与一个第一导块12有信号连接。类似的，一个第二焊盘21与一个第二导块22有信号连接，具体可以是：一个第二焊盘21经第二走线23与一个第二导块22有信号连接。
方式4：第一焊盘11经第一导块12与连接部件3有信号连接，具体可以包括：同电平的多个第一焊盘11与一个第一导块12有信号连接，第一导块12与连接部件3有信号连接。类似的，第二焊盘21经第二导块22与连接部件3有信号连接，具体可以包括：同电平的多个第二焊盘21与一个第二导块22有信号连接，第二导块22与连接部件3有信号连接。
示例的，基于上述方式2，在该方式4中，同电平的多个第一焊盘11与一个第一导块12有信号连接，具体可以是：同电平的多个第一焊盘11经一条或多条第一走线13与一个第一导块12有信号连接。类似的，同电平的多个第二焊盘21与一个第二导块22有信号连接，具体可以是：同电平的多个第二焊盘21经一条或多条第二走线23与一个第二导块22有信号连接。
该方式能够节约导块(包括第一导块12和第二导块22)和连接 部件3的数量，因此，由于连接部件3的数量越多，TEC上的热量倒灌现象(即热量从TEC的热端向冷端传输的现象)就越严重，这样需要消耗更多的功耗来维持TEC两端的温差恒定；因此，该可选的实施例通过减少连接部件3的数量，能够减小TEC热量倒灌，并降低TEC的功耗。
第一焊盘11和第二焊盘21均用于连接芯片的引脚，因此具有一定的电压。固定电压是指固定不变的电压，其与可变电压(或称为待调节电压)相比，可以是高电压也可以是低电压。例如，当固定电压是某一高电压时，可以将多个具有该固定高电压的焊盘与同一个过孔有信号连接，该情况下，具有可变电压的每个焊盘可以与一个过孔有信号连接，如图7所示。图7是图6所示的TEC的局部俯视图；在图7中，多个具有同一固定高电压的第一焊盘11a与同一第一导块12a有信号连接，该多个第一焊盘11a与第一导块12a之间的第一走线13标记为13a；具有可变低电压的一个第一焊盘11b与一个第一导块12b有信号连接，第一焊盘11b与第一导块12b之间的第一走线13标记为13b。
该可选的实现方式3、4的部分特征可以组合使用，例如，一部分第一导块12和一部分第一焊盘11之间的数量关系(或称为对应关系)按照可选的方式3设置，另一部分第一导块12和另一部分第一焊盘11的数量关系按照可选的方式4设置。另外，还可以有其他的组合方式，此处不再一一列举。
第一焊盘11(或第二焊盘21)与连接部件3之间的数量关系可以包括但不限于以下方式5、6：
方式5、第一焊盘11经第一导块12与连接部件13有信号连接，具体可以包括：一个第一焊盘11或同电平的多个第一焊盘11与一个第一导块12有信号连接，一个第一导块12与一个连接部件13有信号连接；也就是说，同电平的多个第一焊盘11与一个连接部件13 有信号连接。类似的，第二焊盘21经第二导块22与连接部件13有信号连接，具体可以包括：一个第二焊盘21或同电平的多个第二焊盘21与一个第二导块22有信号连接，一个第二导块22与一个连接部件13有信号连接；也就是说，同电平的多个第二焊盘21与一个连接部件13有信号连接。
方式6、第一焊盘11经第一导块12与连接部件13有信号连接，具体可以包括：同电平的多个第一焊盘11经一个或多个第一导块12与一个连接部件13连接。类似的，第二焊盘21经第二导块22与连接部件13有信号连接，具体可以包括：同电平的多个第二焊盘21经一个或多个第二导块22与一个连接部件13连接。
在一种可选的实现方式中，第一基板1上还内嵌有至少一个第三导块和/或第二基板2上还包含有至少一个第三导块；至少一个热电素子4的供电电源经第三导块为至少一个热电素子4供电。
示例的，第三导块可以内嵌在第一基板1上，也可以内嵌在第二基板2上，例如，若与第一基板1连接的芯片是电芯片，则第三导块可以内嵌在第一基板1上；若与第一基板2连接的芯片是电芯片，则第三导块可以内嵌在第二基板2上。第三导块的数量可以根据实际需要进行确定，一般地，第三导块的数量大于或等于2。如图8所示，为该可选的实现方式提供的一种TEC，该TEC中的第三导块内嵌在第一基板1上，并且被标记为14，其中，以第一基板1上内嵌了2个第三导块14为例进行说明。另外，图8中，以连接部件3分布在热电素子4的外围为例进行说明。
连接部件3与热电素子4均设置在第一基板1与第二基板2之间，并且，第一基板1与第二基板2之间可以设置至少一个连接部件3，具体的，连接部件3的数量可以根据第一导块12与第二导块22的数量确定。该至少一个连接部件3与该至少一个热电素子4之间的位置关系可以包括但不限于以下几种：
第一种：该至少一个连接部件3分布在该至少一个热电素子4的外围，如图8所示。以图8中的MM'为剖面的剖面图如图9所示。图9仅仅是一种示例，具体实现时不限于此，例如还可以是连接部件3环绕热电素子4设置等方式。该可选的实现方式，连接部件3分布在热电素子4的外围，由于TEC两基板外围的温差相对较小，这样能够减少TEC两端之间的热量倒灌，从而降低TEC自身功耗。
第二种：该至少一个热电素子4分布在该至少一个连接部件3的外围，如图10所示。以图10中的MM'为剖面的剖面图如图11所示。图11仅仅是一种示例，具体实现时不限于此，例如还可以是热电素子4环绕连接部件3设置等方式。该可选的实现方式，能够减小高频电信号通过TEC时的传播路径，从而降低对高频信号造成的时延和衰减。
第三种：该至少一个热电素子4与该至少一个连接部件3交错分布，如图12所示。以图12中的MM'为剖面的剖面图如图13所示。图13仅仅是一种示例，具体实现时不限于此。该可选的实现方式，能够综合上述第一种方式和第二种方式的有益效果，并且能够有效利用TEC基板的空间，减小TEC的面积。
该三种方式之间的部分特征可以结合使用，例如，一部分热电素子4设置在一部分连接部件3的外围，另一部分热电素子4与连接部件3之间交错设置等。另外，还可以有其他的组合方式，此处不再一一列举。
需要说明的是，在图10和图12所示的侧视图中，导流片5与连接部件3的焊盘重合；实际上，二者是错开设置的。
如图14所示，本发明实施例还提供了一种IOI芯片。图14所示的IOI芯片包括：
主基板；
电芯片；电芯片设置于在主基板的表面，并与主基板有信号连 接；
光芯片；光芯片内嵌于主基板,并与电芯片相对设置；
光芯片与电芯片之间还设置有上述第一方面提供的任意一种技术方案所提供的热电制冷模块；其中，热电制冷模块的第一基板上设置的至少一个第一焊盘与电芯片的引脚有信号连接；热电制冷模块的第二基板上设置的至少一个第二焊盘与光芯片的引脚有信号连接；热电制冷模块用于吸收光芯片散发出来的热量。
可选的，该IOI芯片还可以包括芯片盖体；芯片盖体覆盖在电芯片上，并与主基板固定连接。
需要说明的是，图14中是以一个TEC的一侧是一个电芯片，另一侧是两个光芯片为例进行说明的，本发明实施例对TEC两侧的光芯片和电芯片的数量不进行限定。另外，图14中是以IOI芯片中包含芯片盖体为例进行说明的。
在本发明实施例提供的IOI芯片中的传热路径是：从光芯片到TEC的冷端，从TEC的冷端到TEC的热端，再从TEC的热端到电芯片，最后由从电芯片到芯片壳体所在的路径。即图14中的由下至上的方向。
具体实现时，可以根据实际需要控制TEC开启和关闭。例如，当IOI芯片散热困难时，控制TEC启动，即：为TEC通电，即为TEC中的热电素子通电，从而使得TEC的与电芯片连接的一端是热端，与光芯片连接的一端是冷端，进而通过上述传热路径实现IOI芯片的快速散热。其中，本发明实施例对判断IOI芯片散热困难的方法不进行限定，例如可以通过测量芯片壳体的温度等方式实现。
本发明实施例提供的IOI芯片中，包括固定在光芯片和电芯片之间的TEC，具体实现时，通过控制TEC的热端和冷端之间的温差，能够使得TEC冷端温度低于光芯片的结温，TEC热端的温度电芯片要求的结温或大致相当，从而使得IOI芯片的壳温不再受光芯片低 壳温的限制，以实现快速散热的目的。
需要说明的是，现有技术中还提供了一种包含TEC的IOI芯片，如图15所示。具体是在芯片盖体内内嵌一个TEC。由于IOI芯片的壳温的瓶颈在光芯片处，这样，通过控制TEC的热端和冷端之间的温差，使TEC冷端温度低于光芯片要求的温度，TEC热端的温度高于冷端10～20℃，从而使得IOI芯片的壳温不再受光芯片低壳温的限制。但是，这种方法需要TEC承担电芯片的部分制冷，从而导致TEC的体积和功耗都较大，实际应用效果受限。与该现有技术相比，本发明实施例提供的IOI芯片中，由于将TEC设置在了电芯片与光芯片之间，因此，TEC不需要承担电芯片的制冷，从而使得TEC的体积和功耗都较小。
本发明实施例提还提供了一种通信设备，包括：
电路板；
如本发明实施例提供的任一种IOI芯片；该IOI芯片设置于电路板上；该IOI中包含TEC；其中，该TEC是本发明实施例提供的任一种TEC；
散热器；散热器用于将来自热电制冷模块的热端的热量散发出去；
供电模块；供电模块用于为热电制冷模块和电路板供电。
本发明实施例提供的通信设备中包含上述提供的IOI芯片，因此能够达到上述IOI芯片相同的技术效果，即能够使得IOI芯片快速散热，从而使得该通信设备能够快速散热。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换； 而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (11)

  1. 一种热电制冷模块，其特征在于，包括：第一基板和第二基板，所述第一基板与所述第二基板相对设置；
    所述第一基板的外表面上设置有至少一个第一焊盘，所述第二基板的外表面上设置有至少一个第二焊盘；
    所述第一基板上内嵌有至少一个第一导块，所述第二基板上内嵌有至少一个第二导块；
    所述第一基板与所述第二基板之间设置有至少一个连接部件；所述第一焊盘经所述第一导块与所述连接部件有信号连接，所述第二焊盘经所述第二导块与所述连接部件有信号连接；
    所述热电制冷模块还包括至少一个热电素子；所述至少一个热电素子固定于所述第一基板与所述第二基板之间；其中，所述至少一个热电素子用于在通电时一端吸热一端放热，以使所述第一基板与所述第二基板之间产生温差；任意一个所述热电素子与任意一个所述连接部件之间互不导通。
  2. 根据权利要求1所述的热电制冷模块，其特征在于，
    所述第一焊盘经所述第一导块与所述连接部件有信号连接，具体包括：
    所述第一焊盘经第一走线与所述第一导块有信号连接，所述第一导块与所述连接部件有信号连接；
    和/或，所述第二焊盘经所述第二导块与所述连接部件有信号连接，具体包括：
    所述第二焊盘经第二走线与所述第二导块有信号连接，所述第二导块与所述连接部件有信号连接。
  3. 根据权利要求1或2所述的热电制冷模块，其特征在于，
    所述第一焊盘经所述第一导块与所述连接部件有信号连接，具体包括：
    一个所述第一焊盘与一个所述第一导块有信号连接，所述第一导块与所述连接部件有信号连接；
    和/或，所述第二焊盘经所述第二导块与所述连接部件有信号连接，具体包括：
    一个所述第二焊盘与一个所述第二导块有信号连接，所述第二导块与所述连接部件有信号连接。
  4. 根据权利要求1或2所述的热电制冷模块，其特征在于，
    所述第一焊盘经所述第一导块与所述连接部件有信号连接，具体包括：
    同电平的多个所述第一焊盘与一个所述第一导块有信号连接，所述第一导块与所述连接部件有信号连接；
    和/或，所述第二焊盘经所述第二导块与所述连接部件有信号连接，具体包括：
    同电平的多个所述第二焊盘与一个所述第二导块有信号连接，所述第二导块与所述连接部件有信号连接。
  5. 根据权利要求1-3任意一项所述的热电制冷模块，其特征在于，
    所述第一焊盘经所述第一导块与所述连接部件有信号连接，具体包括：
    同电平的多个所述第一焊盘经一个或多个所述第一导块与一个所述连接部件连接；
    和/或，所述第二焊盘经所述第二导块与所述连接部件有信号连接，具体包括：
    同电平的多个所述第二焊盘经一个或多个所述第二导块与一个所述连接部件连接。
  6. 根据权利要求1-5任意一项所述的热电制冷模块，其特征在于，
    所述至少一个所述连接部件分布在所述至少一个热电素子的外围；
    或，所述至少一个热电素子分布在所述至少一个所述连接部件的外围；
    或，所述至少一个热电素子与所述至少一个连接部件交错分布。
  7. 根据权利要求1-6任意一项所述的热电制冷模块，其特征在于，
    所述第一基板上还内嵌有至少一个第三导块和/或所述第二基板上还包含有至少一个第三导块；所述至少一个热电素子的供电电源经所述第三导块为所述至少一个热电素子供电。
  8. 根据权利要求1-7任意一项所述的热电制冷模块，其特征在于，
    所述第一基站上内嵌有多个所述第一导块，任意两个所述第一导块之间互不导通；和/或，
    所述第二基板上内嵌有多个所述第二导块，任意两个所述第二导块之间互不导通；和/或，
    所述第一基板与所述第二基板之间设置有多个所述连接部件，则任意两个所述连接部件之间互不导通。
  9. 一种集成光接口芯片，其特征在于，包括：
    主基板；
    电芯片；所述电芯片设置于在所述主基板的表面，并与所述主基板有信号连接；
    光芯片；所述光芯片内嵌于所述主基板,并与所述电芯片相对设置；
    所述光芯片与所述电芯片之间还设置有如权利要求1-8任意一项所述的热电制冷模块；其中，所述热电制冷模块的第一基板上设置的至少一个第一焊盘与所述电芯片的引脚有信号连接；所述热电制冷模 块的第二基板上设置的至少一个第二焊盘与所述光芯片的引脚有信号连接；所述热电制冷模块用于吸收所述光芯片散发出来的热量。
  10. 根据权利要求9所述的集成光芯片，其特征在于，还包括：
    芯片盖体；所述芯片盖体覆盖在所述电芯片上，并与所述主基板固定连接。
  11. 一种通信设备，其特征在于，包括：
    电路板；
    如权利要求9或10所述的集成光接口芯片；所述集成光芯片设置于所述电路板上；所述集成光接口芯片中包含热电制冷模块；
    散热器；所述散热器用于将来自所述热电制冷模块的热端的热量散发出去；
    供电模块；所述供电模块用于为所述热电制冷模块和所述电路板供电。
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