WO2024066360A1 - 光模块 - Google Patents

光模块 Download PDF

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Publication number
WO2024066360A1
WO2024066360A1 PCT/CN2023/092454 CN2023092454W WO2024066360A1 WO 2024066360 A1 WO2024066360 A1 WO 2024066360A1 CN 2023092454 W CN2023092454 W CN 2023092454W WO 2024066360 A1 WO2024066360 A1 WO 2024066360A1
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WO
WIPO (PCT)
Prior art keywords
chip
optical
electrical
circuit board
solder ball
Prior art date
Application number
PCT/CN2023/092454
Other languages
English (en)
French (fr)
Inventor
陈思涛
隋少帅
张华�
Original Assignee
青岛海信宽带多媒体技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202211209940.2A external-priority patent/CN117849960A/zh
Priority claimed from CN202222623786.5U external-priority patent/CN218767433U/zh
Application filed by 青岛海信宽带多媒体技术有限公司 filed Critical 青岛海信宽带多媒体技术有限公司
Publication of WO2024066360A1 publication Critical patent/WO2024066360A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements

Definitions

  • the present disclosure relates to the field of optical communication technology, and in particular to an optical module.
  • optical communication technology optical modules are devices that realize photoelectric signal conversion and are one of the key components in optical communication equipment.
  • the performance of optical modules is also constantly improving.
  • an optical module which includes a circuit board, an electric chip and an optical chip.
  • the electric chip is stacked on the surface of the circuit board through a first solder ball.
  • the electric chip includes a first front side and a first back side.
  • a plurality of conductive through holes penetrating the first front side and the first back side are formed on the electric chip, and one side of the conductive through holes is connected to the first solder ball.
  • a signal line is arranged on the side of the electric chip facing away from the circuit board, and one side of the signal line is connected to the other side of the conductive through hole.
  • the area of the optical chip is smaller than that of the electric chip.
  • the optical chip includes a second front side and a second back side. The second front side is stacked on the electric chip through a second solder ball, and the second solder ball is connected to the other side of the signal line.
  • FIG1 is a partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure.
  • FIG2 is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure.
  • FIG3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure.
  • FIG4 is a partial exploded view of an optical module provided according to some embodiments of the present disclosure.
  • FIG5 is an assembly diagram of a circuit board, an optical component, and an optical fiber adapter in an optical module according to some embodiments of the present disclosure
  • FIG6 is a 2D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG7 is a 2.5D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG8 is a 3D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG. 9 is another 3D packaging structure of an optoelectronic chip in an optical module provided according to some embodiments of the present disclosure.
  • FIG. 10 is another 3D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG. 11 is another 3D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG. 12 is a top view of a 3D packaging structure of a light engine in an optical module according to some embodiments of the present disclosure.
  • first and second are configured only for descriptive purposes and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used to indicate that two or more components are in direct or indirect physical or electrical contact with each other.
  • the term “coupled” may be used to indicate that two or more components are in direct or indirect physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • optical communication technology in order to establish information transmission between information processing devices, it is necessary to load information onto light and use the propagation of light to achieve information transmission.
  • the light loaded with information is an optical signal.
  • the signals that information processing equipment can recognize and process are electrical signals.
  • Information processing equipment usually includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc.
  • information transmission equipment usually includes optical fibers and optical waveguides.
  • the optical module can realize the mutual conversion between optical signals and electrical signals between information processing equipment and information transmission equipment.
  • at least one of the optical signal input end or the optical signal output end of the optical module is connected to an optical fiber, and at least one of the electrical signal input end or the electrical signal output end of the optical module is connected to an optical network terminal;
  • the first optical signal from the optical fiber is transmitted to the optical module, and the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the optical network terminal;
  • the second electrical signal from the optical network terminal is transmitted to the optical module, and the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.
  • the information processing device directly connected to the optical module is called the upper computer of the optical module.
  • the optical signal input end or the optical signal output end of the optical module can be called an optical port
  • the electrical signal input end or the electrical signal output end of the optical module can be called an electrical port.
  • FIG1 is a partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure.
  • the optical communication system mainly includes a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 and a network cable 103 .
  • One end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200.
  • the optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the total reflection direction can almost maintain the original optical power.
  • the optical signal undergoes multiple total reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance, low-power loss information transmission.
  • the optical communication system may include one or more optical fibers 101, and the optical fibers 101 are detachably connected or fixedly connected to the optical module 200.
  • the host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the working state of the optical module 200.
  • the host computer 100 includes a substantially rectangular housing and an optical module interface 102 disposed on the housing.
  • the optical module interface 102 is configured to connect to the optical module 200 so that the host computer 100 and the optical module 200 can communicate with each other. Establish a unidirectional or bidirectional electrical signal connection.
  • the host computer 100 also includes an external electrical interface, which can be connected to an electrical signal network.
  • the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104, which is configured to be connected to a network cable 103 so that the host computer 100 establishes a unidirectional or bidirectional electrical signal connection with the network cable 103.
  • USB Universal Serial Bus
  • One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103.
  • the third electrical signal sent by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103, and the host computer 100 generates a second electrical signal according to the third electrical signal.
  • the second electrical signal from the host computer 100 is transmitted to the optical module 200, and the optical module 200 converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber 101, and the second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.
  • the first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to the optical module 200, and the optical module 200 converts the first optical signal into a first electrical signal, and the optical module 200 transmits the first electrical signal to the host computer 100, and the host computer 100 generates a fourth electrical signal according to the first electrical signal, and transmits the fourth electrical signal to the local information processing device 2000.
  • the optical module is a tool for realizing the mutual conversion between optical signals and electrical signals. During the conversion process between the optical signals and electrical signals, the information does not change, but the encoding and decoding methods of the information can change.
  • the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT), or a data center server.
  • OLT optical line terminal
  • ONT optical network device
  • data center server a data center server
  • FIG2 is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure.
  • the host computer 100 also includes a PCB circuit board 105 arranged in the housing, a cage 106 arranged on the surface of the PCB circuit board 105, a heat sink 107 arranged on the cage 106, and an electrical connector arranged inside the cage 106.
  • the electrical connector is configured to access the electrical port of the optical module 200; the heat sink 107 has a protruding structure such as fins that increase the heat dissipation area.
  • the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200.
  • the heat generated by the optical module 200 is transferred to the cage 106 and then diffused through the heat sink 107.
  • the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, so that the optical module 200 establishes a bidirectional electrical signal connection with the host computer 100.
  • the optical port of the optical module 200 is connected to the optical fiber 101, so that the optical module 200 establishes a bidirectional optical signal connection with the optical fiber 101.
  • FIG3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure
  • FIG4 is a partial exploded diagram of an optical module provided according to some embodiments of the present disclosure.
  • the optical module 200 includes a shell, a circuit board 300 disposed in the shell, an optical component 400 disposed on the circuit board 300, a fiber coupler 600, and a fiber adapter 700.
  • the housing comprises an upper housing 201 and a lower housing 202 .
  • the upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 .
  • the outer contour of the housing is generally a square body.
  • the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 located on both sides of the bottom plate 2021 and arranged perpendicular to the bottom plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.
  • the lower housing 202 includes a bottom plate 2021 and two sides of the bottom plate 2021. Two lower side plates 2022 are vertically arranged; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and vertically arranged with the cover plate 2011, and the two upper side plates are combined with the two lower side plates 2022 so that the upper shell 201 covers the lower shell 202.
  • the direction of the connection line of the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or inconsistent with the length direction of the optical module 200.
  • the opening 204 is located at the end of the optical module 200 (the left end of FIG. 3), and the opening 205 is also located at the end of the optical module 200 (the right end of FIG. 3).
  • the opening 204 is located at the end of the optical module 200, and the opening 205 is located at the side of the optical module 200.
  • the opening 204 is an electrical port, and the gold finger 301 of the circuit board 300 extends from the electrical port and is inserted into the electrical connector of the host computer 100; the opening 205 is an optical port, which is configured to access the external optical fiber 101 so that the external optical fiber 101 is connected to the optical component 400 inside the optical module 200.
  • the upper shell 201 and the lower shell 202 are combined to facilitate installation of components such as the circuit board 300, the optical component 400, the optical fiber coupler 600 and the optical fiber adapter 700 into the above-mentioned shell, and these components are encapsulated and protected by the upper shell 201 and the lower shell 202.
  • the above-mentioned upper shell 201 and the lower shell 202 are combined to facilitate the deployment of the positioning components, heat dissipation components and electromagnetic shielding components of these components, which is conducive to the automated production.
  • the upper shell 201 and the lower shell 202 are generally made of metal materials, which is conducive to electromagnetic shielding and heat dissipation.
  • the optical module 200 further includes an unlocking component 203 located outside its housing, and the unlocking component 203 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.
  • the unlocking component 203 is located on the outer wall of the two lower side plates 2022 of the lower housing 202, and has a snap-fit component that matches the cage 106 of the host computer 100.
  • the snap-fit component of the unlocking component 203 fixes the optical module 200 in the cage 106 of the host computer; when the unlocking component 203 is pulled, the snap-fit component of the unlocking component 203 moves accordingly, thereby changing the connection relationship between the snap-fit component and the host computer, so as to release the snap-fit relationship between the optical module 200 and the host computer, so that the optical module 200 can be pulled out of the cage 106.
  • the circuit board 300 includes circuit traces, electronic components and chips, etc.
  • the electronic components and chips are connected together according to the circuit design through the circuit traces to realize the functions of power supply, electrical signal transmission and grounding.
  • Electronic components include capacitors, resistors, transistors, metal-oxide-semiconductor field-effect transistors (MOSFET).
  • Chips include microcontroller units (MCU), laser driver chips, limiting amplifiers (LA), clock and data recovery (CDR) chips, power management chips, and digital signal processing (DSP) chips.
  • MCU microcontroller units
  • LA limiting amplifiers
  • CDR clock and data recovery
  • DSP digital signal processing
  • the circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.
  • the circuit board 300 also includes a gold finger 301 formed on the end surface thereof, and the gold finger 301 is composed of a plurality of independent pins.
  • the circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106.
  • the gold finger 301 can be set only on the surface of one side of the circuit board 300 (such as the upper surface shown in FIG. 4), or can be set on the upper and lower surfaces of the circuit board 300 to provide a larger number of pins, so as to adapt to occasions where a large number of pins are required.
  • the gold finger 301 is configured to establish an electrical connection with the host computer to realize power supply, grounding, and Wire-based synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, etc.
  • I2C Inter-Integrated Circuit
  • flexible circuit boards are also used in some optical modules.
  • Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.
  • a flexible circuit board can be used to connect a rigid circuit board to an optical transceiver component.
  • the optical component 400 may have light emitting and light receiving functions.
  • the optical signal output by the optical component 400 is coupled to the internal optical fiber via the optical fiber coupler 600, and the optical signal is then coupled to the optical fiber adapter 700 via the internal optical fiber to achieve light emission;
  • the external optical signal transmitted by the optical fiber adapter 700 is transmitted to the optical fiber coupler via the internal optical fiber, and the external optical signal is then transmitted to the optical component 400 via the optical fiber coupler, and the optical component 400 converts the optical signal into an electrical signal to achieve light reception.
  • the optical component 400 has one of the light emitting function and the light receiving function.
  • the optical component 400 may be integrated on a chip, which is disposed on the circuit board 300 and has a transmitting circuit and/or a receiving circuit formed therein to realize light transmission and/or reception.
  • FIG5 is an assembly diagram of a circuit board, an optical component, and an optical fiber adapter in an optical module provided according to some embodiments of the present disclosure.
  • the optical component 400 generally includes a silicon photonic chip and an electrical chip, and the silicon photonic chip, the electrical chip, and the circuit board 300 are packaged to realize signal transmission between the circuit board 300, the electrical chip, and the silicon photonic chip.
  • the silicon photonic chip has a light source entrance, an optical fiber entrance, and an optical fiber exit, and the light source entrance corresponds to the light source 500, so that the light generated by the light source 500 is injected into the silicon photonic chip through the light source entrance, and the light is modulated inside the silicon photonic chip to generate an optical signal; the optical signal is transmitted to the optical fiber coupler 600 through the optical fiber exit, and the optical fiber coupler 600 couples the optical signal output by the silicon photonic chip to the internal optical fiber, and then couples to the optical fiber adapter 700 through the internal optical fiber to realize light emission.
  • the optical fiber adapter 700 is connected to the second optical fiber coupler through the internal optical fiber, and the second optical fiber coupler is connected to the optical fiber entrance.
  • the external optical signal transmitted by the optical fiber adapter 700 is emitted into the silicon photonic chip via the internal optical fiber, the second optical fiber coupler, and the optical fiber entrance.
  • the silicon photonic chip converts the optical signal into an electrical signal, which is transmitted to the circuit board 300 and then transmitted to the host computer 100 via the gold finger 301 on the circuit board 300 to realize light reception.
  • FIG6 is a 2D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG7 is a 2.5D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure
  • FIG8 is a 3D packaging structure diagram of an optoelectronic chip in an optical module according to some embodiments of the present disclosure.
  • FIG6 and FIG8 there are three main packaging forms for the silicon photonic chip, the electrical chip and the circuit board 300: 2D packaging, 2.5D packaging and 3D packaging, among which,
  • 2D packaging uses a gold wire bonding process to attach the optical chip 420 and the electrical chip 410 to the circuit board 300.
  • Gold wires are used to connect the optical chip 420 to the circuit board 300, the optical chip 420 to the electrical chip 410, and the electrical chip 410 to the circuit board 300.
  • This is the mainstream solution for single-wave 100G rate products and can meet the use requirements.
  • the circuit board 300 is usually unable to be wired at the patch position of the optical chip 420 and the electrical chip 410, and it may even be necessary to hollow out the circuit board 300 to place the optical chip 420 and/or the electrical chip 410. In this way, in high-density packaging application scenarios, the circuit board may have wiring difficulties.
  • the 2.5D package adopts a flip-chip process to attach the optical chip 420 and the electrical chip 410 to the adapter board 800.
  • the solder balls on the upper and lower surfaces of the adapter board 800 are interconnected through internal through silicon vias (TSV), and the adapter board 800 is flip-chip attached to the circuit board 300.
  • TSV through silicon vias
  • This 2.5D package form is mainly used for high-speed coherent optical In the engine component product, since gold wire bonding is completely eliminated, its high-frequency performance can be optimized. However, since the optical chip 420 and the electrical chip 410 are laid flat on the adapter board 800, they occupy a large space.
  • one of the 3D packages uses a flip-chip process to attach the electrical chip 410 to the upper surface of the optical chip 420, ensuring the optimization of high-frequency signals between the optical chip 420 and the electrical chip 410. Since the process of the optical chip 420 itself cannot support the TSV process, the pins on the optical chip 420 need to be connected to the circuit board 300 through a gold wire bonding process. In this way, on the one hand, the gold wire bonding process leads to the sacrifice of high-frequency performance, and on the other hand, the circuit board 300 under the optical chip 420 cannot be wired, and it may even be necessary to hollow out the circuit board 300 to place the optical chip 420. In this way, in high-density packaging application scenarios, the circuit board may have wiring difficulties.
  • the first version of the standardization document for the 3.2T optical engine used in co-packaged optics (CPO) is being formulated.
  • the size of the internal space has been preliminarily determined.
  • the typical value of the space that can be used for the optical engine layout is about 15.6mm ⁇ 5.4mm. Since 2D packaging and 2.5D packaging occupy a large space, they are not considered as the preferred solution.
  • a local reference solution for 3D packaging is as follows:
  • the 3.2T optical engine uses 4 groups of 800G optical engines arranged horizontally in a row. In a single group of 800G optical engines, the electrical chip is located above the optical chip.
  • the minimum width limit of the electrical chip is about 3.26mm.
  • the optical chip needs to reserve at least 260 ⁇ m of wire bonding pads.
  • some embodiments of the present disclosure provide an optical module, in which the optoelectronic chip adopts a new 3D packaging form, and the optical chip is flip-chip mounted on the electrical chip.
  • the optoelectronic chip adopts a new 3D packaging form
  • the optical chip is flip-chip mounted on the electrical chip.
  • FIG9 is another 3D packaging structure diagram of an optoelectronic chip in an optical module provided according to some embodiments of the present disclosure.
  • the optical module provided by some embodiments of the present disclosure includes an electric chip 410 and an optical chip 420.
  • a first solder ball 430 is provided between the electric chip 410 and the circuit board 300, and the electric chip 410 is connected to the circuit board 300 through the first solder ball 430;
  • a second solder ball 440 is provided between the optical chip 420 and the electric chip 410, and the optical chip 420 is connected to the electric chip 410 through the second solder ball 440.
  • the optical chip 420, the electric chip 410 and the circuit board 300 are stacked from top to bottom.
  • the first solder ball 430 and the second solder ball 440 are packaged in a ball grid array (BGA).
  • the ball grid array package is an array made at the bottom of the package substrate.
  • the first solder ball 430 serves as the I/O terminal of the circuit to realize the interconnection between the electrical chip 410 and the circuit board 300.
  • the second solder ball 440 serves as the I/O terminal of the circuit to realize the interconnection between the electrical chip 410 and the optical chip 420.
  • the ball grid array is a surface mount package for multi-pin LSI, with spherical contacts as pins in an array on the back of the substrate and large-scale integrated circuits (LSI) assembled on the front of the substrate (some BGA chips and lead ends are on the same side of the substrate).
  • LSI large-scale integrated circuits
  • BGA has a variety of packaging types, and its appearance is square or rectangular. It can be divided into peripheral, staggered and full array BGA according to the arrangement of the solder balls.
  • the material of the first solder ball 430 and the second solder ball 440 is a mixture of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel.
  • the optical chip 420 is attached to the electrical chip 410 by the flip-chip bonding process, that is, the front side of the optical chip 420 is attached to the electrical chip 410, so that the circuits, pads, etc. on the front side of the optical chip 420 are directly connected to the electrical chip 410 through the second solder balls 440, thereby avoiding the sacrifice of high-frequency performance caused by gold wire bonding.
  • the area of the optical chip 420 needs to be smaller than the area of the electrical chip 410.
  • the application scenarios of 3D packaging include the application of short-distance direct intensity detection systems in data centers and the application of long-distance coherent systems. Therefore, the optical chip is usually a silicon photonic chip and uses an MZ modulator. However, the size of the silicon photonic chip using the MZ modulator is often very large, and the flip-chip bonding process cannot be used to attach the silicon photonic chip using the MZ modulator to the electrical chip.
  • the present disclosure is mainly aimed at the emerging application scenario of optoelectronic sealing, which is characterized by very limited structural space of the optical engine, but very high total communication capacity requirement (such as 3.2T).
  • the modulator of the optical chip 420 needs to adopt a more compact micro-ring modulator.
  • the area of the optical chip using the micro-ring modulator is much smaller than that of the electrical chip.
  • the electrical chip 410 has a mature TSV process.
  • the electrical chip 410 includes a first front side 4101 and a first back side 4102.
  • a plurality of conductive vias penetrating the first front side 4101 and the first back side 4102 are formed in the electrical chip 410. Signals can be transmitted between the first front side 4101 and the first back side 4102 of the electrical chip 410 through the conductive vias.
  • the optical chip 420 includes a second front side 4201 and a second back side 4202 .
  • the second front side 4201 is stacked on the electrical chip 410 through second solder balls 440 , so that the optical chip 420 is attached to the electrical chip 410 by a flip-chip bonding process.
  • the circuit board 300 transmits the high-frequency signal to the first back side 4102 of the electrical chip 410 through the first solder ball 430, the electrical chip 410 transmits the high-frequency signal from the first back side 4102 to the first front side 4101 through the conductive through hole, and the first front side 4101 then transmits the high-frequency signal to the optical chip 420 through the second solder ball 440, so as to realize the high-frequency signal transmission between the circuit board 300 and the optical chip 420.
  • the electric chip 410 is an electric chip made of silicon.
  • the through hole is etched on the silicon and then a conductive material is filled in the through hole.
  • the conductive material can realize electrical connection between the first front side 4101 and the first back side 4102 of the electric chip 410.
  • a TSV process may be used to etch the through hole on the electrical chip 410 .
  • the through hole is a straight through hole, and the depth dimension of the through hole has a preset ratio to its diameter dimension, so that the through hole is relatively slender.
  • the electric chip 410 when a conductive through hole is provided on the electric chip 410, the electric chip 410 may be provided in layers, that is, a conductive layer is provided in the electric chip 410, and the conductive through hole may include a first blind hole and a second blind hole, the first blind hole extends from the first front side 4101 of the electric chip 410 to the conductive layer, the second blind hole extends from the first back side 4102 of the electric chip 410 to the conductive layer, and the first blind hole and the second blind hole are staggered, and the first blind hole is electrically connected to the second blind hole through the conductive layer. In this way, the first front side 4101 and the first back side 4102 of the electric chip 410 are electrically connected through the first blind hole, the conductive layer, and the second blind hole.
  • the conductive via on the electrical chip 410 may correspond to the first solder ball 430, that is, the first solder ball 430 is connected to one end of the conductive via.
  • the circuit board 300 transmits the high-frequency signal directly from one side of the electrical chip 410 to the other side of the electrical chip 410 through the first solder ball 430 and the conductive via.
  • the conductive through hole on the electrical chip 410 may not correspond to the first solder ball 430.
  • a first signal line is arranged on the side of the electrical chip 410 where the first solder ball 430 is arranged. One end of the first signal line is connected to one end of the conductive through hole, and the other end of the first signal line is connected to the first solder ball 430.
  • the circuit board 300 transmits the high-frequency signal from one side of the electrical chip 410 to the other side of the electrical chip 410 through the first solder ball 430, the first signal line and the conductive through hole.
  • a second signal line is arranged on the side of the second solder ball 440 on the electrical chip 410, and one end of the second signal line is connected to the other end of the conductive through hole, and the other end of the second signal line is connected to the second solder ball 440.
  • the high-frequency signal transmitted by the conductive through hole is transmitted to the optical chip 420 through the second signal line and the second solder ball 440 to realize signal transmission between the electrical chip 410 and the optical chip 420.
  • the second front side 4201 of the optical chip 420 needs to be connected to the second solder ball 440, that is, the front side of the optical chip 420 faces downward.
  • the electrical chip 410 is connected between the first front side 4101 and the first back side 4102 through a conductive through hole, so the first solder ball 430 can be arranged between the circuit board 300 and the first back side 4102 of the electrical chip 410, and the second solder ball 440 is arranged between the first front side 4101 of the electrical chip 410 and the second front side 4201 of the optical chip 420, that is, the front side of the electrical chip 410 faces upward, so that the first front side 4101 of the electrical chip 410 is connected to the second front side 4201 of the optical chip 420 through the second solder ball 440, and the first back side 4102 of the electrical chip 410 is connected to the circuit board 300 through the first solder ball 430, so as to maximize the high-frequency signal integrity between the optical chip 420 and the electrical chip 410.
  • FIG10 is another 3D packaging structure diagram of an optoelectronic chip in an optical module provided according to some embodiments of the present disclosure.
  • the first solder ball 430 can also be arranged between the circuit board 300 and the first front side 4101 of the electric chip 410
  • the second solder ball 440 is arranged between the first back side 4102 of the electric chip 410 and the second front side 4201 of the optical chip 420, that is, the front side of the electric chip 410 faces downward, so that the first back side 4102 of the electric chip 410 is connected to the second front side 4201 of the optical chip 420 through the second solder ball 440, and the first front side 4101 of the electric chip 410 is connected to the circuit board 300 through the first solder ball 430, and the high-frequency signal transmitted by the circuit board 300 is transmitted from the first front side 4101 of the electric chip 410 to the first back side 4102 of the electric chip 410 through the TSV, and the high-frequency signal is then transmitted to the optical chip 420 through the second sold
  • Fig. 11 is another 3D packaging structure diagram of an optoelectronic chip in an optical module provided according to some embodiments of the present disclosure.
  • a heat conductive block can also be arranged on the first back side 4102 of the electric chip 410, and the heat conductive block is arranged side by side with the optical chip 420, and the heat conductive block can contact the upper housing 201.
  • the heat generated by the operation of the electric chip 410 can be dissipated upwards through the heat conductive block, and the heat is conducted to the upper housing 201 through the heat conductive block, so as to enhance the heat dissipation efficiency of the light engine.
  • the optical chip 420 adopts a silicon optical chip.
  • the electrical chip 410 integrates a driver chip and a trans-impedance amplifier (TIA), that is, a transmitting circuit and a receiving circuit are provided in the silicon photonic chip.
  • TIA trans-impedance amplifier
  • the driver chip in the electrical chip 410 receives the electrical signal transmitted by the circuit board 300 through the first solder ball 430, and the driver chip generates a driving signal according to the electrical signal.
  • the driving signal is transmitted to the optical chip 420 via the second solder ball 440.
  • the optical chip 420 performs signal modulation according to the light generated by the light source 500 and the driving signal, and generates a transmission light signal through the transmitting circuit.
  • the transmission light signal is coupled to the optical fiber adapter 700 via the optical fiber coupler 600 and the internal optical fiber, thereby realizing light emission.
  • the receiving circuit in the optical chip 420 converts the external optical signal into an electrical signal, and the electrical signal is transmitted to the TIA chip in the electrical chip 410 via the second solder ball 440.
  • the electrical signal is transmitted to the circuit board 300 via the first solder ball 430, and then transmitted to the gold finger 301 via the circuit board 300, and then transmitted to the host computer 100 via the gold finger 301, thereby realizing the reception of light.
  • FIG12 is a top view of a 3D packaging structure of an optical engine in an optical module provided according to some embodiments of the present disclosure.
  • the 3.2T optical engine applied to CPO uses 4 groups of 800G optical engines, and the 4 groups of optical engines are arranged horizontally in a row along the left and right directions. Since each group of optical engines includes an electrical chip 410 and an optical chip 420, and the optical chip 420 is attached to the top of the electrical chip 410, the 4 electrical chips 410 are arranged side by side along the left and right directions.
  • the left and right direction is the width direction of the optoelectronic chip (the width direction is the direction perpendicular to the paper in FIG9 ), and the up and down direction is the length direction of the optoelectronic chip (the length direction is the left and right direction in FIG9 ).
  • the width dimension L3 of the gap is reserved to be 400 ⁇ m.
  • the maximum width of the four electric chips 410 on the circuit board 300 is about 15.6mm.
  • the minimum width limit of the electric chip 410 is about 3.26mm, so the width dimension L1 of the electric chip 410 is 3260 ⁇ m to 3500 ⁇ m.
  • the length dimension of the electric chip 410 is about 4500 ⁇ m to 5000 ⁇ m, and the length dimension of the optical chip 420 is about 1000 ⁇ m to 2000 ⁇ m. Since the area of the optical chip 420 is smaller than the area of the electric chip 410, and the length dimension of the optical chip 420 is smaller than the length dimension of the electric chip 410, the width dimension L2 of the optical chip 420 can be less than or equal to the width dimension L1 of the electric chip 410, and therefore the width dimension L2 of the optical chip 420 is about 3200 ⁇ m to 3500 ⁇ m.
  • the width of each group of 800G optical engines that is, the width of the electrical chip 410 is 3.26mm, and 400 ⁇ m is reserved between each group of 800G optical engines.
  • the circuit board under the optical engine can be wired normally at this time, and the difficulty of wiring layout on the circuit board in the whole solution is significantly improved.
  • the optical module provided by the embodiment of the present disclosure includes a circuit board, an electric chip and an optical chip.
  • the electric chip is stacked on the surface of the circuit board through a first solder ball, and the optical chip is stacked on the electric chip through a second solder ball, so that the optical chip, the electric chip and the circuit board are stacked from top to bottom, and the electric chip is connected to the circuit board through the first solder ball, and the optical chip is connected to the electric chip through the second solder ball, so that the electric chip is used as a transfer board to realize the connection between the optical chip and the circuit board;
  • the electric chip includes a first front side and a first back side, and a plurality of conductive through holes penetrating the first front side and the first back side are formed on the electric chip, and one side of the conductive through hole is connected to the first solder ball; a signal line is arranged on the first front side or the first back side, and one side of the signal line is connected to the other side of the conductive through hole, so as to
  • the present invention uses the electric chip as a transfer board, and mounts the optical chip on the electric chip by using the flip-chip welding process.
  • the electric chip By utilizing the mature TSV process of the electric chip, high-frequency signal transmission between the optical chip, the electric chip and the circuit board is achieved with the shortest path, thereby ensuring the integrity of the high-frequency signal to the greatest extent.
  • the optical chip Since the optical chip is mounted on the electric chip by using the flip-chip welding process, the gold wire bonding process is completely eliminated, thereby improving the connection port density between the optoelectronic chip and the circuit board, thereby achieving a high-density layout of the circuit board to the greatest extent.

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Abstract

一种光模块（200），包括电路板（300）及光芯片（420）、电芯片（410），电芯片（410）通过第一焊球（430）堆叠在电路板（300）的表面，电芯片（410）包括第一正面（4101）、第一背面（4102）及多个导电通孔，导电通孔的一侧与第一焊球（430）连接，电芯片（410）背向电路板（300）的侧面上设有与导电通孔连接的信号线；光芯片（420）的面积小于电芯片（410）的面积，光芯片（420）包括第二正面（4201）与第二背面（4202），第二正面（4201）通过第二焊球（440）堆叠在电芯片（410）上，第二焊球（430）与信号线的另一侧连接。通过将电芯片（410）作为转接板，将光芯片（420）采用倒装焊工艺贴装在电芯片（410）上，利用电芯片（410）成熟的TSV工艺，以最短路径实现了光芯片（420）、电芯片（410）及电路板（300）之间的高频信号传送，保证了高频信号完整性；消除了金线键合工艺，提高了光芯片（420）、电芯片（410）与电路板（300）的连接端口密度，实现了电路板（300）的高密度布局。

Description

光模块
本申请要求在2022年09月30日提交中国专利局、申请号为202211209940.2的优先权；在2022年09月30日提交中国专利局、申请号为202222623786.5的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及光通信技术领域，尤其涉及一种光模块。
背景技术
随着云计算、移动互联网、视频等新型业务和应用模式的发展，光通信技术的进步变的愈加重要，在光通信技术中，光模块是实现光电信号转换的器件，是光通信设备中的关键器件之一。在光通信技术的不断进步下，光模块的性能也不断提高。
发明内容
本公开一些实施例提供了一种光模块，该光模块包括电路板、电芯片与光芯片，电芯片通过第一焊球堆叠在电路板的表面，电芯片包括第一正面与第一背面，电芯片上形成有贯穿第一正面与第一背面的多个导电通孔，导电通孔的一侧与第一焊球连接；电芯片背向电路板的侧面上布设有信号线，信号线的一侧与导电通孔的另一侧连接；光芯片的面积小于电芯片的面积，光芯片包括第二正面与第二背面，第二正面通过第二焊球堆叠在电芯片上，第二焊球与信号线的另一侧连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非是对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等进行限制。
图1为根据本公开一些实施例提供的一种光通信系统的局部架构图；
图2为根据本公开一些实施例提供的一种上位机的局部结构图；
图3为根据本公开一些实施例提供的一种光模块的结构图；
图4为根据本公开一些实施例提供的一种光模块的局部分解图；
图5为根据本公开一些实施例提供的一种光模块中电路板、光部件与光纤适配器的装配图；
图6为根据本公开一些实施例提供的一种光模块中光电芯片的2D封装结构图；
图7为根据本公开一些实施例提供的一种光模块中光电芯片的2.5D封装结构图；
图8为根据本公开一些实施例提供的一种光模块中光电芯片的一种3D封装结构图；
图9为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结 构图一；
图10为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结构图二；
图11为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结构图三；
图12为根据本公开一些实施例提供的一种光模块中光引擎的3D封装结构俯视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、详细地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅被配置为描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接或间接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接或间接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适被配置为或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所 确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
在光通信技术中，为了在信息处理设备之间建立信息传递，需要将信息加载到光上，利用光的传播实现信息的传递。这里，加载有信息的光就是光信号。光信号在信息传输设备中传输时可以减少光功率的损耗，因此可以实现高速度、远距离、低成本的信息传递。信息处理设备能够识别和处理的信号是电信号。信息处理设备通常包括光网络终端(Optical Network Unit，ONU)、网关、路由器、交换机、手机、计算机、服务器、平板电脑、电视机等，信息传输设备通常包括光纤及光波导等。
光模块可以实现信息处理设备与信息传输设备之间的光信号与电信号的相互转换。例如，光模块的光信号输入端或光信号输出端中的至少一个连接有光纤，光模块的电信号输入端或电信号输出端中的至少一个连接有光网络终端；来自光纤的第一光信号传输至光模块，光模块将该第一光信号转换为第一电信号，并将该第一电信号传输至光网络终端；来自光网络终端的第二电信号传输至光模块，光模块将该第二电信号转换为第二光信号，并将该第二光信号传输至光纤。由于多个信息处理设备之间可以通过电信号进行信息传输，因此，需要多个信息处理设备中的至少一个信息处理设备直接与光模块连接，而无需所有的信息处理设备直接与光模块连接。这里，直接连接光模块的信息处理设备被称为光模块的上位机。另外，光模块的光信号输入端或光信号输出端可被称为光口，光模块的电信号输入端或电信号输出端可被称为电口。
图1为根据本公开一些实施例提供的一种光通信系统的局部架构图。如图1所示，光通信系统主要包括远端信息处理设备1000、本地信息处理设备2000、上位机100、光模块200、光纤101以及网线103。
光纤101的一端向远端信息处理设备1000的方向延伸，且光纤101的另一端通过光模块200的光口与光模块200连接。光信号可以在光纤101中全反射，且光信号在全反射方向上的传播几乎可以维持原有光功率，光信号在光纤101中发生多次的全反射，以将来自远端信息处理设备1000的光信号传输至光模块200中，或将来自光模块200的光信号传输至远端信息处理设备1000，从而实现远距离、低功率损耗的信息传递。
光通信系统可以包括一根或多根光纤101，且光纤101与光模块200可拆卸连接，或固定连接。上位机100被配置为向光模块200提供数据信号，或从光模块200接收数据信号，或对光模块200的工作状态进行监测或控制。
上位机100包括大致呈长方体的壳体(housing)，以及设置在该壳体上的光模块接口102。光模块接口102被配置为接入光模块200，以使上位机100与光模块200 建立单向或双向的电信号连接。
上位机100还包括对外电接口，该对外电接口可以接入电信号网络。例如，该对外电接口包括通用串行总线接口(Universal Serial Bus，USB)或网线接口104，网线接口104被配置为接入网线103，以使上位机100与网线103建立单向或双向的电信号连接。网线103的一端连接本地信息处理设备2000，且网线103的另一端连接上位机100，以通过网线103在本地信息处理设备2000与上位机100之间建立电信号连接。例如，本地信息处理设备2000发出的第三电信号通过网线103传入上位机100，上位机100根据该第三电信号生成第二电信号，来自上位机100的该第二电信号传输至光模块200，光模块200将该第二电信号转换为第二光信号，并将该第二光信号传输至光纤101，该第二光信号在光纤101中传输至远端信息处理设备1000。例如，来自远端信息处理设备1000的第一光信号通过光纤101传播，来自光纤101的第一光信号传输至光模块200，光模块200将该第一光信号转换为第一电信号，光模块200将该第一电信号传输至上位机100，上位机100根据该第一电信号生成第四电信号，并将该第四电信号传入本地信息处理设备2000。需要说明的是，光模块是实现光信号与电信号相互转换的工具，在上述光信号与电信号的转换过程中，信息并未发生变化，信息的编码和解码方式可以发生变化。
上位机100除了包括光网络终端之外，还包括光线路终端(Optical Line Terminal，OLT)、光网络设备(Optical Network Terminal，ONT)、或数据中心服务器等。
图2为根据本公开一些实施例提供的一种上位机的局部结构图。为了清楚地显示光模块200与上位机100的连接关系，图2仅示出了上位机100的与光模块200相关的结构。如图2所示，上位机100还包括设置于壳体内的PCB电路板105、设置在PCB电路板105的表面的笼子106、设置于笼子106上的散热器107、以及设置于笼子106内部的电连接器。该电连接器被配置为接入光模块200的电口；散热器107具有增大散热面积的翅片等凸起结构。
光模块200插入上位机100的笼子106中，由笼子106固定光模块200，光模块200产生的热量传导给笼子106，然后通过散热器107进行扩散。光模块200插入笼子106中后，光模块200的电口与笼子106内部的电连接器连接，从而使光模块200与上位机100建立双向的电信号连接。此外，光模块200的光口与光纤101连接，从而使得光模块200与光纤101建立双向的光信号连接。
图3为根据本公开一些实施例提供的一种光模块的结构图，图4为根据本公开一些实施例提供的一种光模块的局部分解图。如图3与图4所示，光模块200包括壳体(shell)、设置于壳体内的电路板300、设置于电路板300上的光部件400、光纤耦合器600及光纤适配器700。
壳体包括上壳体201和下壳体202，上壳体201盖合在下壳体202上，以形成具有两个开口204和205的上述壳体；壳体的外轮廓一般呈现方形体。
在本公开的一些实施例中，下壳体202包括底板2021以及位于底板2021两侧、与底板2021垂直设置的两个下侧板2022；上壳体201包括盖板2011，盖板2011盖合在下壳体202的两个下侧板2022上，以形成上述壳体。
在一些实施例中，下壳体202包括底板2021以及位于底板2021两侧、与底板2021 垂直设置的两个下侧板2022；上壳体201包括盖板2011以及位于盖板2011两侧、与盖板2011垂直设置的两个上侧板，由两个上侧板与两个下侧板2022结合，以使上壳体201盖合在下壳体202上。
两个开口204和205的连线所在的方向可以与光模块200的长度方向一致，也可以与光模块200的长度方向不一致。例如，开口204位于光模块200的端部(图3的左端)，开口205也位于光模块200的端部(图3的右端)。或者，开口204位于光模块200的端部，而开口205则位于光模块200的侧部。开口204为电口，电路板300的金手指301从电口伸出，插入上位机100的电连接器中；开口205为光口，被配置为接入外部光纤101，以使外部光纤101连接光模块200内部的光部件400。
采用上壳体201、下壳体202结合的装配方式，便于将电路板300、光部件400、光纤耦合器600及光纤适配器700等器件安装到上述壳体中，由上壳体201、下壳体202对这些器件进行封装保护。此外，在装配电路板300和光部件400等器件时，上述上壳体201、下壳体202结合的装配方式也便于这些器件的定位部件、散热部件以及电磁屏蔽部件的部署，有利于自动化地实施生产。
在一些实施例中，上壳体201及下壳体202一般采用金属材料制成，利于实现电磁屏蔽以及散热。
在一些实施例中，光模块200还包括位于其壳体外部的解锁部件203，解锁部件203被配置为实现光模块200与上位机之间的固定连接，或解除光模块200与上位机之间的固定连接。
示例地，解锁部件203位于下壳体202的两个下侧板2022的外壁上，具有与上位机100的笼子106匹配的卡合部件。当光模块200插入笼子106中时，由解锁部件203的卡合部件将光模块200固定在上位机的笼子106里；拉动解锁部件203时，解锁部件203的卡合部件随之移动，进而改变卡合部件与上位机的连接关系，以解除光模块200与上位机的卡合关系，从而可以将光模块200从笼子106中抽出。
电路板300包括电路走线、电子元件及芯片等，通过电路走线将电子元件和芯片按照电路设计连接在一起，以实现供电、电信号传输及接地等功能。电子元件例如包括电容、电阻、三极管、金属氧化物半导体场效应管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。芯片例如包括微控制单元(Microcontroller Unit，MCU)、激光驱动芯片、限幅放大器(Limiting Amplifier，LA)、时钟数据恢复(Clock and Data Recovery，CDR)芯片、电源管理芯片、数字信号处理(Digital Signal Processing，DSP)芯片。
电路板300一般为硬性电路板，硬性电路板由于其相对坚硬的材质，还可以实现承载作用，如硬性电路板可以平稳地承载上述电子元件和芯片；硬性电路板还可以插入上位机100的笼子106中的电连接器中。
电路板300还包括形成在其端部表面的金手指301，金手指301由相互独立的多个引脚组成。电路板300插入笼子106中，由金手指301与笼子106内的电连接器导通连接。金手指301可以仅设置在电路板300一侧的表面(例如图4所示的上表面)，也可以设置在电路板300上下两侧的表面，以提供更多数量的引脚，从而适应引脚数量需求大的场合。金手指301被配置为与上位机建立电连接，以实现供电、接地、二 线制同步串行(Inter-Integrated Circuit，I2C)信号传递、数据信号传递等。
当然，部分光模块中也会使用柔性电路板。柔性电路板一般与硬性电路板配合使用，以作为硬性电路板的补充。例如，硬性电路板与光收发组件之间可以采用柔性电路板连接。
在一些实施例中，光部件400可具有光发射与光接收功能，光部件400输出的光信号经光纤耦合器600耦合至内部光纤，光信号再经由内部光纤耦合至光纤适配器700，以实现光的发射；光纤适配器700传输的外部光信号经内部光纤传输至光纤耦合器，外部光信号再经由光纤耦合器传输至光部件400，光部件400将光信号转换为电信号，以实现光的接收。但本公开并不局限于此，在一些实施例中，光部件400具有光发射功能与光接收功能之一。
为了提高光部件400的封装密度，可将光部件400集成在一个芯片上，该芯片设置在电路板300上，且该芯片内形成有发射电路和/或接收电路，以实现光的发射和/或接收。
图5为根据本公开一些实施例提供的一种光模块中电路板、光部件与光纤适配器的装配图。如图5所示，光部件400一般包括硅光芯片与电芯片，硅光芯片、电芯片与电路板300进行封装，以实现电路板300、电芯片与硅光芯片之间的信号传输。硅光芯片具有光源入口、光纤入口与光纤出口，光源入口与光源500相对应，如此光源500产生的光经由光源入口射入硅光芯片，硅光芯片内部对光进行调制，以产生光信号；光信号经由光纤出口传输至光纤耦合器600，光纤耦合器600将硅光芯片输出的光信号耦合至内部光纤，再经由内部光纤耦合至光纤适配器700，以实现光的发射。
光纤适配器700通过内部光纤与第二光纤耦合器连接，第二光纤耦合器与光纤入口连接，如此，光纤适配器700传输的外部光信号经由内部光纤、第二光纤耦合器、光纤入口射入硅光芯片，硅光芯片将光信号转换为电信号，电信号传输至电路板300，经由电路板300上的金手指301传输至上位机100，以实现光的接收。
图6为根据本公开一些实施例提供的一种光模块中光电芯片的2D封装结构图，图7为根据本公开一些实施例提供的一种光模块中光电芯片的2.5D封装结构图，图8为根据本公开一些实施例提供的一种光模块中光电芯片的一种3D封装结构图。如图6、图7及图8所示，硅光芯片、电芯片与电路板300的封装方式主要有三种封装形态：2D封装、2.5D封装与3D封装，其中，
如图6所示，2D封装采用金线键合工艺，将光芯片420、电芯片410贴在电路板300上，光芯片420与电路板300、光芯片420与电芯片410、电芯片410与电路板300之间均采用金线连接，是目前在单波100G速率产品上的主流方案，能够满足使用需求。但是，由于采用金线键合连接，其高频性能是有牺牲的；另一方面，电路板300在光芯片420、电芯片410的贴片位置通常无法布线，甚至可能需要挖空电路板300来放置光芯片420和/或电芯片410，如此，在高密度封装应用场景中，电路板可能存在布线困难的情况。
如图7所示，2.5D封装采用倒装焊工艺，将光芯片420、电芯片410贴在转接板800上，转接板800上下表面的焊球通过内部硅通孔(Through Silicon Via，TSV)互连，并将转接板800倒装焊贴在电路板300上。该2.5D封装形态主要用于高速相干光 引擎组件产品上，由于完全消除了金线键合，其高频性能能达到最优化，但是由于光芯片420、电芯片410是平铺在转接板800上，其占用空间较大。
如图8所示，在一些实施例中，其中一种3D封装采用倒装焊工艺，将电芯片410贴在光芯片420的上表面，保证了光芯片420、电芯片410之间高频信号的最优化，由于光芯片420的工艺本身无法支持TSV工艺，光芯片420上的引脚需要通过金线键合工艺连接至电路板300上。如此，一方面金线键合工艺导致高频性能的牺牲，另一方面光芯片420下方的电路板300无法布线，甚至可能需要挖空电路板300来放置光芯片420，如此，在高密度封装应用场景中，电路板可能存在布线困难的情况。
应用于共封装光学(co-packaged optics，CPO)的3.2T光引擎第一版标准化文件正在制定中，内部空间大小已初步确定，能够应用于光引擎布局的空间典型值约为15.6mm×5.4mm，由于2D封装、2.5D封装占用空间较大，不做首选方案考虑。一种3D封装的局部参考方案如下：3.2T光引擎采用4组800G光引擎水平一字排开，单组800G光引擎中，电芯片位于光芯片的上面，电芯片的最小宽度极限约为3.26mm，光芯片需要额外预留至少260μm的打线焊盘，则光芯片的最小总宽度约为3.52mm，每组800G光引擎之间需要预留400μm，在该预留位置形成电路板300上的金线键合焊盘，因此，3.2T光引擎总宽度约为(3.52+0.4)×4＝15.68mm。
可以看出，3.2T光引擎的空间布局尺寸已经超出标准协议的尺寸要求，完全没有余量，此时光引擎下方的电路板表层无法布线，导致电路板300上的走线布置非常困难。
针对上述问题，本公开一些实施例提供了一种光模块，该光模块中的光电芯片采用新型3D封装形态，将光芯片倒装贴在电芯片上，借助电芯片成熟的TSV工艺，将光电芯片的全部引脚连接至电芯片下表面，并将电芯片直接贴装在电路板300上，该方案既能保证光引擎的高频性能的最优化，又能保证芯片占用面积的最优化。
图9为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结构图一。如图9所示，本公开一些实施例提供的光模块包括电芯片410与光芯片420，电芯片410与电路板300之间设置有第一焊球430，电芯片410通过第一焊球430与电路板300连接；光芯片420与电芯片410之间设置有第二焊球440，光芯片420通过第二焊球440与电芯片410连接。如此光芯片420、电芯片410与电路板300由上至下层叠设置。
在一些实施例中，第一焊球430与第二焊球440采用球栅阵列封装(Ball Grid Array，BGA)，球栅阵列封装是在封装体基板的底部制作阵列，第一焊球430作为电路的I/O端实现电芯片410与电路板300的互连，第二焊球440作为电路的I/O端实现电芯片410与光芯片420的互连。
采用BGA技术封装的器件是一种表面贴装型器件，球栅阵列是在基板的背面按阵列方式制出球形触点作为引脚，在基板正面装配大规模集成电路(Large Scale Integration，LSI)(部分BGA芯片与引出端在基板同一面)是多引脚LSI用的一种表面贴装型封装。BGA的封装类型多种多样，其外形结构为方形或矩形，根据焊接球的排布方式可分为周边型、交错型和全阵列型BGA。
在一些实施例中，为了适应高密度输入输出端(Input/Output，IO)数目的应用场 景，第一焊球430、第二焊球440的材质为钛、铜、铝、银、钯、金、铊、锡或镍中的一种或多种混合。
在一些实施例中，由于光芯片420的电路、焊盘一般设置在光芯片420的正面，光芯片420的背面主要起到支撑的作用，因此为了实现光芯片420不通过金线键合工艺与电芯片410连接，采用倒装焊工艺将光芯片420贴在电芯片410上，即将光芯片420的正面贴在电芯片410上，使得光芯片420正面的电路、焊盘等通过第二焊球440与电芯片410直接连接，避免了金线键合导致的高频性能的牺牲。
采用倒装焊工艺将光芯片420贴在电芯片410上时，由于光芯片420与电芯片410之间还需要填充胶水进行粘接固定，且根据目前的3D封装应用场景，需要满足光芯片420的面积小于电芯片410的面积。
3D封装应用场景中包括数据中心短距离直接强度检测系统的应用，以及长距离相干系统的应用，因此，光芯片通常为硅光芯片，并且采用MZ调制器，然而，采用MZ调制器的硅光芯片的尺寸往往非常大，无法采用倒装焊工艺将采用MZ调制器的硅光芯片贴在电芯片上。
本公开主要面向光电合封这一新兴应用场景，其特点是光引擎结构空间非常受限，但是总通信容量要求非常高(如3.2T)，针对这些应用特点，光芯片420的调制器需要采用结构更加紧凑的微环调制器，采用微环调制器的光芯片的面积远小于电芯片的面积。
电芯片410具有成熟的TSV工艺，电芯片410包括第一正面4101与第一背面4102，电芯片410内形成有贯穿第一正面4101与第一背面4102的多个导电通孔，通过导电通孔能够实现电芯片410的第一正面4101与第一背面4102之间的信号传输。
光芯片420包括第二正面4201与第二背面4202，第二正面4201通过第二焊球440堆叠在电芯片410上，以采用倒装焊工艺将光芯片420贴在电芯片410上。
示例性地，电路板300通过第一焊球430将高频信号传输至电芯片410的第一背面4102，电芯片410通过导电通孔将高频信号由第一背面4102传输至第一正面4101，第一正面4101再将高频信号通过第二焊球440传输至光芯片420，以实现电路板300与光芯片420之间的高频信号传输。
在一些实施例中，电芯片410是由硅制成的电芯片，在电芯片410上设置导电通孔时，在硅上刻蚀通孔，然后在通孔内填充导电材料，通过该导电材料能够实现电芯片410的第一正面4101与第一背面4102之间的电连接。
在一些实施例中，在电芯片410上设置导电通孔时，可采用TSV工艺在电芯片410上刻蚀通孔，该通孔为直通孔，且通孔的深度尺寸与其直径尺寸具有预设比例，使得通孔比较细长。
示例性地，在电芯片410上设置导电通孔时，电芯片410可分层设置，即在电芯片410内设置一层导电层，导电通孔可包括第一盲孔与第二盲孔，第一盲孔由电芯片410的第一正面4101延伸至导电层，第二盲孔由电芯片410的第一背面4102延伸至导电层，且第一盲孔与第二盲孔错位设置，第一盲孔通过导电层与第二盲孔电连接。如此，电芯片410的第一正面4101与第一背面4102之间通过第一盲孔、导电层、第二盲孔实现电连接。
在一些实施例中，电芯片410上的导电通孔可与第一焊球430相对应，即第一焊球430与导电通孔的一端连接，如此，电路板300通过第一焊球430、导电通孔将高频信号直接由电芯片410的一侧传输至电芯片410的另一侧。
电芯片410上的导电通孔还可与第一焊球430不对应，电芯片410上设置第一焊球430的侧面上布设有第一信号线，该第一信号线的一端与导电通孔的一端连接，第一信号线的另一端与第一焊球430连接，如此电路板300通过第一焊球430、第一信号线及导电通孔将高频信号由电芯片410的一侧传输至电芯片410的另一侧。
由于光芯片420的面积小于电芯片410的面积，因此光芯片420的两侧边缘与电芯片410的两侧边缘之间存在间隙，第二焊球440与导电通孔无法完全对应，因此电芯片410上设置第二焊球440的侧面上布设有第二信号线，该第二信号线的一端与导电通孔的另一端连接，第二信号线的另一端与第二焊球440连接，如此导电通孔传输的高频信号通过第二信号线和第二焊球440传输至光芯片420，以实现电芯片410与光芯片420之间的信号传输。
在一些实施例中，由于光芯片420的电路、焊盘等设置在光芯片420的第二正面4201上，为了避免金线键合工艺，因此光芯片420的第二正面4201需与第二焊球440连接，即光芯片420的正面朝下。
电芯片410是通过导电通孔实现第一正面4101与第一背面4102之间的连接，因此第一焊球430可设置于电路板300与电芯片410的第一背面4102之间，第二焊球440设置于电芯片410的第一正面4101与光芯片420的第二正面4201之间，即电芯片410的正面朝上，使得电芯片410的第一正面4101通过第二焊球440与光芯片420的第二正面4201连接，电芯片410的第一背面4102通过第一焊球430与电路板300连接，以最大程度保证光芯片420与电芯片410之间的高频信号完整性。
图10为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结构图二。如图10所示，第一焊球430还可设置于电路板300与电芯片410的第一正面4101之间，第二焊球440设置于电芯片410的第一背面4102与光芯片420的第二正面4201之间，即电芯片410的正面朝下，使得电芯片410的第一背面4102通过第二焊球440与光芯片420的第二正面4201连接，电芯片410的第一正面4101通过第一焊球430与电路板300连接，电路板300传输的高频信号通过TSV由电芯片410的第一正面4101传输至电芯片410的第一背面4102，高频信号再通过第二焊球440传输至光芯片420。
图11为根据本公开一些实施例提供的一种光模块中光电芯片的另一种3D封装结构图。如图11所示，当第一焊球430设置于电芯片410的第一正面4101与电路板300之间，第二焊球440设置于电芯片410的第一背面4102与光芯片420的第二正面4201之间时，由于电芯片410的背面较硬，起到支撑的作用，且光芯片420的尺寸较小，只会覆盖电芯片410的一部分，因此还可在电芯片410的第一背面4102上设置导热块，该导热块与光芯片420并排设置，且导热块可与上壳体201接触。
如此，电芯片410工作产生的热量可通过导热块向上散热，将热量通过导热块传导至上壳体201，以增强这个光引擎的散热效率。
在一些实施例中，为了适应高密度IO数目的应用场景，光芯片420采用硅光芯片， 电芯片410内集成有驱动芯片与跨阻放大器(Trans-impedance amplifier，TIA)，即硅光芯片内设置有发射电路与接收电路，电芯片410与光芯片420进行信号互连时，电芯片410中的驱动芯片接收电路板300通过第一焊球430传输的电信号，驱动芯片根据电信号产生驱动信号，驱动信号经由第二焊球440传输至光芯片420，光芯片420根据光源500产生的光与驱动信号进行信号调制，通过发射电路产生发射光信号，发射光信号经由光纤耦合器600、内部光纤耦合至光纤适配器700，实现了光的发射。
光纤适配器700传输的外部光信号经由内部光纤、第二光纤耦合器传输至光芯片420后，光芯片420内的接收电路将外部光信号转换为电信号，电信号经由第二焊球440传输至电芯片410中的TIA芯片，电信号经由TIA芯片处理后通过第一焊球430传输至电路板300，再经由电路板300传输至金手指301，通过金手指301传输至上位机100，实现了光的接收。
图12为根据本公开一些实施例提供的一种光模块中光引擎的3D封装结构俯视图。如图12所示，应用于CPO的3.2T光引擎采用4组800G光引擎，4组光引擎沿左右方向水平一字排开，由于每组光引擎包括一个电芯片410与一个光芯片420，光芯片420贴在电芯片410的上方，因此4个电芯片410沿左右方向并排设置。在一些实施例中，左右方向为光电芯片的宽度方向(该宽度方向为图9中垂直于纸面的方向)，上下方向为光电芯片的长度方向(该长度方向为图9中的左右方向)。
在一些实施例中，由于4个电芯片410沿左右方向并排设置，为了防止电芯片410贴在电路板300上时发生物料干涉，相邻电芯片410之间存在间隙，该间隙的宽度尺寸L3预留400μm，为了满足应用于光引擎布局的空间典型值15.6mm×5.4mm，即4个电芯片410在电路板300上的最大宽度约为15.6mm。如此，一个电芯片410的宽度尺寸约为15.6÷4-0.4＝3.5mm，而电芯片410的最小宽度极限约为3.26mm，因此电芯片410的宽度尺寸L1为3260μm～3500μm。
在一些实施例中，根据电芯片410、光芯片420的加工工艺，电芯片410的长度尺寸约为4500μm～5000μm，光芯片420的长度尺寸约为1000μm～2000μm。由于光芯片420的面积小于电芯片410的面积，且光芯片420的长度尺寸小于电芯片410的长度尺寸，如此光芯片420的宽度尺寸L2可小于或等于电芯片410的宽度尺寸L1，因此光芯片420的宽度尺寸L2约为3200μm～3500μm。
采用本公开的新型3D封装方案，每组800G光引擎的宽度，即电芯片410的宽度为3.26mm，每组800G光引擎之间预留400μm，3.2T光引擎总宽度约为(3.26+0.4)×4＝14.64mm，相比标准协议要求略有余量。更重要的是，此时光引擎下方的电路板可以正常布线，整个方案中电路板上的走线布设难度得到明显改善。
本公开实施例提供的光模块包括电路板、电芯片与光芯片，电芯片通过第一焊球堆叠在电路板的表面，光芯片通过第二焊球堆叠在电芯片上，使得光芯片、电芯片与电路板由上至下层叠设置，且电芯片通过第一焊球与电路板连接，光芯片通过第二焊球与电芯片连接，使得电芯片作为转接板实现光芯片与电路板的连接；电芯片包括第一正面与第一背面，电芯片上形成有贯穿第一正面与第一背面的多个导电通孔，导电通孔的一侧与第一焊球连接；第一正面或第一背面上布设有信号线，信号线的一侧与导电通孔的另一侧连接，以通过导电通孔实现电芯片的第一正面与第一背面之间的信 号传输；光芯片包括第二正面与第二背面，第二正面通过第二焊球堆叠在电芯片上，且第二焊球与信号线的另一侧连接，如此电芯片通过信号线、第二焊球将信号传输至光芯片，以实现光电芯片之间的信号传输。
本公开将电芯片作为转接板，将光芯片采用倒装焊工艺贴装在电芯片上，利用电芯片成熟的TSV工艺，以最短路径实现了光芯片、电芯片与电路板之间的高频信号传送，最大程度保证了高频信号完整性；由于光芯片采用倒装焊工艺贴装在电芯片上，完全消除了金线键合工艺，提高了光电芯片与电路板的连接端口密度，最大程度实现了电路板的高密度布局。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种光模块，包括：
    电路板；
    电芯片，通过第一焊球堆叠在所述电路板的表面；所述电芯片包括第一正面与第一背面，所述电芯片上形成有贯穿所述第一正面与所述第一背面的多个导电通孔，所述导电通孔的一侧与所述第一焊球连接；所述电芯片背向所述电路板的侧面上布设有信号线，所述信号线的一侧与所述导电通孔的另一侧连接；
    光芯片，包括第二正面与第二背面，所述第二正面通过第二焊球堆叠在所述电芯片上，所述第二焊球与所述信号线的另一侧连接；所述光芯片的面积小于所述电芯片的面积。
  2. 根据权利要求1所述的光模块，其中，所述第一焊球设置于所述电路板与所述第一背面之间，所述电芯片通过所述第一焊球与所述电路板信号连接；
    所述第二焊球设置于所述第一正面与所述第二正面之间，所述光芯片通过所述第二焊球与所述电芯片信号连接。
  3. 根据权利要求1所述的光模块，其中，所述第一焊球设置于所述电路板与所述第一正面之间，所述电芯片通过所述第一焊球与所述电路板信号连接；
    所述第二焊球设置于所述第一背面与所述第二正面之间，所述光芯片通过所述第二焊球与所述电芯片信号连接。
  4. 根据权利要求1所述的光模块，其中，所述电芯片的宽度尺寸大于或等于所述光芯片的宽度尺寸，所述电芯片的长度尺寸大于所述光芯片的长度尺寸。
  5. 根据权利要求4所述的光模块，其中，所述电芯片的宽度尺寸为3260μm～3500μm，所述电芯片的长度尺寸为4500μm～5000μm；
    所述光芯片的宽度尺寸为3200μm～3500μm，所述光芯片的长度尺寸为1000μm～2000μm。
  6. 根据权利要求1所述的光模块，其中，沿所述电芯片的宽度方向上，所述电路板上并排设置有多个所述电芯片，每个所述电芯片通过所述第一焊球堆叠在所述电路板上，相邻所述电芯片之间存在间隙。
  7. 根据权利要求6所述的光模块，其中，相邻所述电芯片之间的间隙为400μm。
  8. 根据权利要求1所述的光模块，其中，所述光芯片通过所述第二焊球堆叠在所述电芯片的第一背面上，所述第一背面上还设置有导热块，所述导热块用于对所述电芯片进行散热。
  9. 根据权利要求1所述的光模块，其中，所述电芯片集成有驱动芯片与跨阻放大芯片。
  10. 根据权利要求1所述的光模块，其中，所述光芯片为硅光芯片，所述硅光芯片采用微环调制器进行光信号调制。
PCT/CN2023/092454 2022-09-30 2023-05-06 光模块 WO2024066360A1 (zh)

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