TWI364832B - Ic apparatus, system and method for measuring - Google Patents

Description

1364832 P51970082TW 28926twf.doc/n Nine, invention description: [Technical field to which the invention belongs]

The present invention is an integrated circuit device, and more particularly to a system and method. J [Prior Art] As electronic system products have been gradually reduced, various components from conventional electricity have gradually become shrink-fitted into a single package, a heterogeneous integrated single-chip. In the process of integration, a single wafer structure with ## function and different f needs different processes depending on different materials. However, it takes a lot of time to overcome this problem' and investment. In the face of the current market cycle with short product cycles and low-cost production, it seems that the development of system integration of heterogeneous chips is not easy. Therefore, integrating a functional wafer into a package structure has become a development path. Currently, technologies for integrating different chips into the same package structure include technologies such as System on Chip (SoC) and System in Package (SiP). In these techniques, φ is usually packaged into a package component. The wafers may be uniformly distributed on the substrate or stacked directly by the wafer. In addition, there is a solution in which different wafers are stacked in a complete stack of bumps into a complete set of wafers (usually matched with wafer thinning). In the structure of the bump stack, since the multilayer wafers are stacked by bump bonding, the complexity of the structure is increased. In order to observe the thermal stress/strain state of each wafer and bump caused by the difference in thermal expansion coefficient of various wafers after observing each wafer by bumps, or 5 1364832 P51970082TW 28926twf.doc/n force or gravity The mechanical stress/strain that is extracted must develop some new measurement methods. U纟 has a political and immediate knowledge of the stress/strain state of the crystal #(四)' and these instant information speeds up the design or process improvement time. Improve competitiveness. [Summary of the Invention]

The present invention can provide a method of measuring money: ===_, in a two-dimensional plane of the first body!:; set: at least - substrate and - on, and the first wafer has a plurality of layers stacked on the substrate The conductive elements may be respectively formed in the middle of the second to the second and may be electrically connected to the corresponding two through holes, and the parallel device may be disposed in the first layer, wherein ~ The first - sense and produce - the first group salty %. </ RTI> to sense the resistance value of the first wafer, and

- Sensor electrical connection::: Two external transmission: The first-wire pair can transmit the first:: bump to the substrate component and the other to the output. Applicable to a stacking system that also provides a measurement system having at least two first-lead edges and including a sensed resistance value: the parallel strip has a plurality of first-conductor, 罘-groups TEST ¥ through hole, sub-and multiple conductive elements 6 1364832 P51970082TW 28926ην[«^ο/η can be divided into the first - through hole 0 - the frame = the first conductive element and a plurality of bumps electrical connection The substrate 对应 corresponds to the first sensor connected to the corresponding conductive element, and the number is transmitted through the corresponding conductive tree and the corresponding bump: at the heart end: an output end. The analysis module can electrically connect the first set of sensitivities and strains from the first output to detect the stress of W/

From another point of view, the present invention further provides a measuring method which can measure the stress/strain of a wafer inside the integrated circuit device. The middle wafer can be stacked on the substrate through a plurality of bumps, and the wafer has a plurality of through holes. In addition, a conductive element is disposed in each of the via holes to be electrically connected to the corresponding bump. The measurement method provided by the present invention includes measuring the resistance value of the -first surface of the wafer and generating - a first set of sensing signals. In addition, the present invention can transmit the first set of sensing signals to the plurality of first substrates on the substrate through the corresponding conductive elements and corresponding bumps.

Output: By this, the present invention can measure the stress/strain of the first surface according to the change in the resistance value of the first surface. Since the present invention can be configured with a sensor&apos; on the wafer to measure the resistance value on the wafer. Therefore, the present invention can measure the stress/strain experienced by the wafer based on the measured resistance 2. Furthermore, since the guide turns of the present invention are connected to the conductive member, the present invention directly utilizes the conductive member and the bump to transmit signals without having to rely on additional wires to transmit signals. The above and other features and advantages of the present invention will become more apparent and understood from the following description. The measurement system 100 ~ τ is intended to be a preferred embodiment of the present invention. Referring to Fig. 1', the measuring system 1 2 of the present embodiment is used to measure an integrated circuit device 1 having a stacked structure. At least one sensor is disposed in the two-body circuit device 1() 2 (hereinafter, the resistance value of the internal chip of the integrated circuit 1〇2 is measured in detail, and the signal is called S1, and the sensing signal is received. The internal stress/strain changes of the S1//, the quadrature circuit device 102. Group 1〇4, is a hardware measurement device, and may also be a sub-person-'or more 疋-single crystal&gt;; The present invention is not limited to the mathematical formula of Xiangcho, and analyzes the variation of internal and external stress/strain of the integrated circuit device: inner R -5§々^ +[α,Γ+α2Γ2+ .·__·.] ( 1) is the electric _, @ resistance: the amount of change of the wafer inside the integrated circuit device 102. In addition, the meaning is the conversion matrix stress value, which can also be expressed in the form of a matrix. The thermal expansion coefficient of the force, and τ In the case of the coffin, it can be seen from the above formula (1) that the resistance value and the amount of change of the internal wafer of the device 102 in the analysis module 1 are the stress/strain to which the body circuit circuit device 102 is subjected. The following is a description of the integrated circuit device provided by the present invention:: lean application 8 1364832 P51970082TW 28926twf.doc/n • first real 2 is a package structure diagram of an integrated circuit according to a first embodiment of the present invention. Referring to FIG. 2, the integrated circuit &amp; 200 provided in this embodiment includes a substrate 202 and a wafer 204. The wafer 204 can be stacked on the substrate 202 by a plurality of bumps 206. The wafer 204 has a plurality of through silicon vias, such as TSV1, TSV2, TSV3, and TSV4, and the interior of each via can be Forming a conductive element, such as 210, 212, 214, 216. The material of the conductive elements 21, 212, 214, 216 may be a conductive material, such as copper. The structure of the conductive element may be divided into several The conductive element 210 is taken as an example, and its structure includes a conductor post 21〇a and a contact pad 21〇b. The conductor post 210a may be inserted in the via hole TSV1, and the contact pad 210b may be disposed on the wafer 204. The upper surface and the lower surface. In the present embodiment, the contact pads 2i〇b positioned on the lower surface of the wafer 204 can electrically connect the connection bumps 206, and the wafers 204 can be stacked on the substrate 2〇2. With multiple outputs, For example, 222, it can be coupled to the analysis module 1〇4 as shown in FIG. 1. In this embodiment, the upper surface of the substrate 222 can be configured with a plurality of pads, such as 224 [1:4], which can be respectively Installed on each of the wheel ends 222. In addition, a plurality of guides 226' can be disposed on the substrate, which can electrically connect the respective bumps 2 () 6 to the corresponding soldering 2, 4 such as 'wire 226 [1 ] and 226[2] can connect the bumps 2〇6(1) and 2〇6[2] to the corresponding pads and chat]. In general, the material can be steel. In addition, the material of the contact pad 210b and the pad 224 may be a material having better conductivity, such as gold, copper, copper, 9 1364832 P51970082TW 28926t\vf.d〇c/n ' or inscription. The present invention, in order to measure the stress/strain experienced by the wafer in the integrated circuit, therefore includes at least one sensed state in the integrated circuit device provided by the present invention. In the present embodiment, the wafer 204 is provided with a sensor 32_234 which can be worn on the upper surface of the wafer 204. The sensors 232 and 234 are used to sense the resistance value of the upper surface of the wafer 2〇4, and generate corresponding sensing signals, such as the sensing signal S1 in FIG. In the actual palladium example, 'sensors 232 and 234 can benefit conductors and semi-conductor materials, Lu is made by process technology such as wafer thick film and semiconductor, and its materials are, for example, copper, aluminum, polysilicon, etc. Larger material. Additionally, a plurality of pairs of wires, such as 236 and 240, may be disposed on wafer 204. Wherein, the wires 236[1] and 236[2] can electrically connect the sensor 232 to the adjacent conductive elements 21A and 212, respectively, and the wires 240^] and 240[2] can electrically connect the sensor 234. The plurality of sets of sensing signals generated by the sensing states 232 and 234 can be connected to the pads on the substrate 202 through corresponding wires, corresponding conductive elements and corresponding bumps. 224 and sent from output 222 to an external analysis group. For example, a set of sensing signals output by the sensor 232 can be sent to the output through the conductive elements 210 and 212, the bumps 206[1] and 206[2], the wires 226[1] and 226[2], respectively. Pads 224(1) and 224[2] on end 222. In contrast, a set of sensing signals output by the sensor 234 can be respectively sent through the conductive elements 214 and 216, the bumps 206[3] and 206[4], the wires 226[3] and 226[4]. Pads 224[3] and 224[4] 轮i〇1364832 P5197〇〇g2TW 28926twf.doc/n on the wheel end 222. Second Embodiment FIGS. 3A and 3B illustrate a second embodiment in accordance with the present invention. A package junction of a circuit. In the present invention, the sensing signal is sent to the wheel end by transmitting the sensing element and the bump. Thus, some of the implementations of the present invention can be configured on any bit of the wafer = for example, in Figure 3, sensors 232 and 234 can be disposed on different surfaces of the die 204, respectively. And in some alternative embodiments

The position of the lower surface of the wafer 204 can be relative to the sensor and the position of the upper surface of the wafer 204, such as shown in Figure 3B. Since the present embodiment can configure the sensors 232 and 234, respectively, at opposite positions of the upper and lower surfaces of the wafer 204. Therefore, the present embodiment can sense not only the stress/strain that the wafer 204 is subjected to in the plane of the upper surface or the lower surface, but also the stress/distribution generated by the wafer 2G4 in the three-dimensional direction. However, in the present embodiment, the sensors 232 and 234 appear in Fig. 3b to transmit the sensed signal to the output 222 through the same bumps (1) and [2], and the bumps are not. Those of ordinary skill in the art should know that

The sensing signals generated by the sensing conditions and 234 are transmitted to the wheel end 222 through different transmission paths. Figure 4A is a schematic illustration of the stress/strain of a wafer in three dimensions. As is clear from Fig. 4A, the upper surface of the wafer 2〇4 is subjected to stress' so that strain is generated in the χ_γ plane, and the displacement amount is assumed to be ul°, and the lower surface of the wafer 2〇4 is also due to stress. Strain is generated in the plane, and the displacement can be u2. On the other hand, while the upper surface and the lower surface of the wafer 2〇4 are strained, the wafer 2〇4 is also in the z-square 1364832 P51970082TW 28926twf.doc/n:= degree Chu and if the length of z2 is required, then It can be obtained by using the Beth's theorem, and its mathematical expression can be expressed as follows: z2 = ^z? +(^^7^2)7 (2) and its equivalent geometry can refer to Figure 4B. Therefore, it can be seen that the present embodiment requires stress/strain on the upper surface and the lower surface of the crystal 2G4.

In this case, it is possible to simultaneously analyze the case where the wafer 204 is subjected to stress/strain in a three-dimensional direction. However, if it is only necessary to analyze the case where the wafer 204 is subjected to stress/strain in the z direction, the structure of the following third embodiment can also be employed. ~ Third Embodiment FIG. 5 is a view showing a package structure of a $3 implementation lazy-integrated circuit of the present invention. Referring to Figure 5, as previously described, the sensor can be placed anywhere on the wafer. For example, in the integrated circuit device φ 500 provided in the present embodiment, a sensing benefit 502 can be disposed on the side of the wafer 204. In addition, the sensor 5〇2 can also be electrically connected to the guiding members 210 and 212 through the wires 5〇4[1] and .5〇4[2]. Similar to the foregoing, the sensor 5〇2 can also sense the resistance value on the side of the wafer 204 and generate a set of sense signals. The set of sensing signals can be transmitted to the substrate by wires 5〇4[1] and 5〇4[2], conducting pieces 210 and 212, bumps 2〇6[1] and 2〇6[2]. 2〇2^ pads 224(1) and 224[2] on output 222. Thereby, it is possible to measure the stress/strain that the wafer is subjected to in the vertical direction. 12 1364832 P51970082TW 28926twf.doc/n Further, the above advantages of the additional wire structure are not extended. The present invention also provides the structure of the following fourth embodiment. Fourth Embodiment FIG. 6 is a view showing a package structure of an integrated circuit in accordance with a fourth embodiment of the present invention. Referring to FIG. 6, the integrated circuit device 600 provided in this embodiment differs from the integrated circuit device in the foregoing embodiment in that, in this embodiment, the sensors 602 and 604 can be mounted in a wafer and can be They are electrically connected to the conductive elements 210, 212, 214, and 216 through corresponding wires 606 [1], 606 [2], 610 [1], and 61 〇 [2i, respectively. Similarly, sensors 602 and 604 can sense the resistance value in a particular direction within wafer 204. Thus, the present embodiment can measure the stress/strain experienced by the inside of the wafer 204. [Fifth Embodiment] Fig. 7 is a view showing an integrated body assembly structure W according to a fifth embodiment of the present invention. Referring to FIG. 7, the integrated circuit insertion 700 provided in this embodiment is the same as the integrated circuit device provided in the foregoing embodiments. In the present embodiment, the substrate 2〇2* However, at the upper surface, the output end 222 can be configured, and an additional output end 702 can be disposed on the lower surface. Because "=3:: such as 712 and Μ, etc., the vias are configured for the vias' such as TSV5, TSV6, TSV7, and TSV8. Similarly, in these vias, respectively, - conduction can be formed. Element 13 1364832 P51970082TW 28926twf.doc/n piece 706 [1.4] In addition, the welding head (eg 710 [1.4]), and multiple wires [1:4] can also be configured on the wheel end 7〇2. In the embodiment, each of the wires 7_:4] may be electrically connected to the conductive elements 706 [1:4], respectively, and by these wires [1:4], the soldering wires 710 may be respectively used. [1:4] correspondingly electrically connected to the conducting element 7〇6[1:4]. In this example, 'sensing|| 712 can pass through the wire 714(1) and

7M[2] is electrically connected to the conductive element jaws and WO. The conductive elements W and 72, respectively, can pass through the bumps 2〇6[5] and 2 and the wires 722(1) and 722[2 dirty to the conductive elements, respectively. Thereby, the sensing signal 'outputted by the sensor 712 can be sent to the output terminal through the conductive element view and the different wires 708 [1] and 708 [2]. Pads on 〇 2, such as 7 and 710 [2]. Sixth Embodiment Fig. 8 is a view showing a package structure® of an integrated circuit in accordance with a sixth embodiment of the present invention. Referring to Figure 8, the _body circuit device 800' provided by the present embodiment is a multi-layer stacked structure. In other words, the integrated circuit device not only has the wafer 2〇4, but also the wafer. In the present embodiment, the wafer 8〇2 is stacked on the wafer 2〇4 by a plurality of bumps 8〇4. Similarly, wafer 802 has a plurality of vias, such as TSVs 9, in which conductive elements such as 808 and 810 can be formed. These conductive elements 808 can be electrically connected to the corresponding bumps 8〇4[1] and 8〇4[2]. Additionally, a sensor, such as 814, can be disposed on wafer 802 that can be mounted on the upper surface of wafer 802. Similarly, the sensor 814 can sense the resistance value of the upper surface of the wafer 8〇2 14 1364832 P51970082TW 28926twf.doc/n ' and generate a sensing signal. The sense signal can be sent to adjacent conductive elements 808 and 810 through wires such as 816[1] and 816[2]. Thereby, the sensing signal can be sent to the output end 222 of the substrate 202 through the corresponding conductive elements and bumps on the wafer 8〇2 and through the corresponding conductive elements and germanium blocks on the wafer 2〇4 or 7〇2. The detailed principle can be referred to the above description, and will not be described here. As described above, in the above embodiments, the sensor is used to measure the resistance value of the wafer during deformation and to generate a corresponding sensing signal. • This sense signal can be sent to the output of the substrate through the conductive elements and bumps. Thereby, the present invention can analyze the stress/strain experienced by the calculation wafer based on the sensing signals. # In addition, since the sensing signal is transmitted through the conductive element and the bump, the embodiment does not need to use an additional wire bonding method to transmit the signal, which makes the position of the sensing state 4 more flexible. Further, the present invention allows the position at which the sensor is placed to be more flexible, so that the present invention can measure the stress/strain of the wafer in three dimensions in summer. The present invention has been described in its preferred embodiments as a matter of course, and is not intended to limit the invention, and it is obvious to those skilled in the art that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a system for measuring a quantity in accordance with a preferred embodiment of the present invention. 2 is a package structure diagram of an integrated circuit 1513664832 P51970082TW 28926twf.d〇c/n according to a first embodiment of the present invention. FIGS. 3A and 3β are diagrams showing a second embodiment of the present invention. Package structure diagram of the integrated circuit. - Figure 4 is a schematic diagram showing the stress/strain of a wafer in three dimensions. Figure 4A shows an equivalent geometry.

Fig. 5 is a green block diagram showing the package structure of an integrated circuit in accordance with a third embodiment of the present invention. Fig. 6 is a green block diagram showing the package structure of an integrated circuit in accordance with a fourth embodiment of the present invention. Fig. 7 is a view showing a package structure of an integrated circuit in accordance with a fifth embodiment of the present invention. Figure 8 is a block diagram showing the structure of an integrated circuit in accordance with a sixth embodiment of the present invention. ' [Main component symbol description] 100 : Measurement system

800: integrated battery device 102, 200, 300, 500, 600, 700, 104: analysis module 202 · substrate 204, 802: wafer 206, 804: bumps 210, 212, 214, 216, 706, 718 , 720, 808: Conduction _ 210a: conductor post 16 1364832 P51970082TW 28926twf.doc / n • 210b: contact pads 222, 702: output terminals 224, 710: pads 226, 236, 240, 504, 606, 610, 708, 714: wires 232, 234, 502, 602, 604, 712, 814: sensor S1+, S1-··sensing signal TSV, TSV2, TSV3, TSV4, TSV5, TSV6, TSV7, TSV8, TSV9: via hole

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Claims (1)

1364832 (c〇年^月艺日修(爱)本本----1-0040^____ X. Patent application scope: 1. An integrated circuit device comprising: a substrate having a plurality of first output ends; a first wafer is stacked on the substrate by a plurality of first bumps, and the first wafer has a plurality of first via holes; a plurality of first conductive elements respectively formed corresponding to the first conductive lines One of the holes is electrically connected to the first bumps; a first sensor is disposed on the first wafer for sensing a change amount of the resistance value of the first wafer, corresponding to a first set of sensing signals; and a first pair of wires electrically connecting the first sensor to the corresponding first conducting element to respectively pass the first set of sensing signals by the corresponding first conducting The component and the corresponding first bump are transferred to the first output terminals. 2. The integrated circuit device according to claim 1, wherein the first sensor is disposed on the first wafer 3. The integrated circuit device according to claim 1, wherein the A sensor is disposed on the lower surface of the first wafer. The integrated circuit device of claim 1, wherein the first sensor is disposed inside the first wafer. The integrated circuit device of claim 1, wherein the first sensor is disposed on a side of the first wafer. 6. The integrated circuit device according to claim 1, further comprising a second sensor disposed on the upper surface and the lower surface of the 18 1364832 100-12-8 of the wafer, and the second sensor is also used to sense the first chip a change amount of the resistance value corresponding to a second set of sensing signals; and a second pair of wires respectively connecting the second sensor to the corresponding first conducting element 'to sense the second group The signal is transmitted to the first output terminals through the corresponding first conductive element and the corresponding first bump. The integrated circuit device of claim 6, wherein the position of the second sensor on the lower surface of the first wafer is relative to the first sensor on the upper surface of the first wafer s position. 8. The integrated circuit device of claim 1, further comprising: a second wafer having a plurality of second vias stacked on the first wafer by a plurality of second bumps, Each of the second bumps is electrically connected to one of the first conductive elements; and the plurality of second conductive elements are respectively formed in one of the second conductive vias and electrically connected The second bumps; a third sensor is disposed on the second wafer for sensing a change amount of the resistance value of the second wafer, corresponding to the third group of sensing signals; The sensor is electrically connected to the corresponding second conductive element to transmit the third set of sensing signals to the corresponding second transmitting element, the corresponding second protruding block, the corresponding first conductive element and the corresponding one of the bumps Transfer to the first outputs. Brother 9. If you apply for a patent (four)! In the integrated circuit device of the above aspect, the first output terminals are disposed on the substrate in the same silk surface as the first bumps. The integrated circuit device of claim 1, further comprising: a plurality of first pads, respectively disposed on the first wheel ends; And a plurality of fourth wires electrically connecting the first pads to the first bumps. The integrated circuit device of claim i, further comprising: a plurality of second output ends disposed on the substrate and not facing the first bumps; A plurality of second pads ' are respectively disposed on the second wheel ends. 12. The integrated circuit device of claim 11, wherein the substrate further comprises: ~ a plurality of third via holes; and a plurality of third conductive elements respectively corresponding to one of the third via holes And each of the third conductive elements is respectively coupled to one of the first bumps; and a plurality of fifth 'wires, respectively electrically connecting the third conductive elements to the second pads . 13. A measuring system for an integrated circuit device having a stacked structure, having a substrate and a plurality of wafers, and the wafers are sequentially stacked on the substrate, and the measuring system comprises: - The sensor is electrically connected to the plurality of wafers for sensing a change amount of a resistance value of the corresponding wafer, which corresponds to a first set of sensing signals, wherein each of the plurality of wafers has a plurality of first conductions a hole, and a plurality of conductive layers 20 100-12-8, respectively, corresponding to the plurality of conductive holes formed in the first conductive vias, such that the wafers are connected to the substrate through the plurality of material elements and the plurality of bumps; a first pair of wires electrically connecting the first sensor to the conductive element to transmit the sensed signal through the corresponding conductive bump to the -first output terminal on the substrate; and i analyzing The module is electrically connected to the first output ends, and is connected to the first domain signal outputted from the Lth. And points μ. The measurement system described in claim 13 of the patent application, the complex stress/strain measurement system. The measuring system according to claim 13 is characterized in that the first sensor is disposed on the upper surface of the corresponding wafer. The reading system of claim 13, wherein the first sensor is disposed on a lower surface of the corresponding wafer. The reading system described in claim 13 is characterized in that the first sensor is disposed inside the corresponding wafer. ,read 18. The measurement system of claim 13, wherein the first sensor is disposed on a side of the corresponding wafer. 5 Hai, 19. The measurement system of claim 13, wherein the = analysis module is used to detect the stress/strain change of the corresponding wafer. The measuring system of claim 13, wherein the substrate further comprises: /, reading a plurality of first pads, disposed at the first output ends; and a plurality of third wires The first pad is electrically connected to the protrusions 21 - a measuring method, which is suitable for measuring the inside of an integrated circuit device ^ 21 1364832 100-12-8 and is transparent to a substrate. One, and the corresponding, respectively, corresponding to the electrical connection configuration has a measurement method including the following steps: · u block in which one of the first 矣--------the measurement signal of the wafer is measured; the resistance value of the surface The change amount 'corresponds to the first group of sensing signals through the corresponding conductive elements and the plurality of blocks transmitted to the substrate by the apostrophes, and the first output terminal receives the first group of sensing signals, The amount of change in the resistance value of a surface. Jump to obtain the service 22. If the scope of the patent application is based on the resistance value of the first-surface, it includes the stress/strain. The value is changed to obtain the first surface. 23. The second step of the patent application scope is as follows: The method of the method further includes measuring the second product of the wafer &amp;&amp; - the second group signal; The amount of change in the resistance value corresponding to the first set of first sensing signals transmitted to the substrate through the corresponding conductive element and the corresponding number is received by the first output terminals. The amount of change in the resistance value: -H峨, to obtain 24. According to the claim 23 of the patent scope, the resistance value according to the second surface is more included in the stress/calendar. U tilting (four) the second surface is 25. The measuring apparatus according to claim 23 includes 22 1364832 100-12-8, according to the change amount of the resistance value of the first surface and the second surface, the wafer is The stress/strain experienced in the three-dimensional direction. Measurement twenty three